80 lines
2.4 KiB
Markdown
80 lines
2.4 KiB
Markdown
# ST-LAB
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FIsica - Laboratorio III - Esperimentazioni di Elettronica
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```mermaid
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flowchart TD
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%% --- STILI ---
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classDef hw fill:#ffcccc,stroke:#333,stroke-width:2px;
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classDef memory fill:#e1f5fe,stroke:#333,stroke-width:1px;
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classDef logic fill:#fff9c4,stroke:#333,stroke-width:1px;
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Start((START)) --> Init
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%% --- BLOCCO INIZIALIZZAZIONE ---
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subgraph Init [1. Inizializzazione Bare Metal]
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direction TB
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RCC[RCC AHB4ENR & APB1ENR\nAbilita Clock GPIO & USART]:::hw
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GPIO[GPIO MODER & AFR\nButton=Input, LED=Output, TX=AF]:::hw
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UART[USART3 CR1 & BRR\nConfigura Baud & Abilita UE]:::hw
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NVIC[NVIC_EnableIRQ\nAbilita Interrupts al processore]:::hw
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RCC --> GPIO --> UART --> NVIC
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end
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Init --> MainLoop
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%% --- BLOCCO MAIN LOOP ---
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subgraph Main [2. Main Loop (Polling Button)]
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direction TB
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MainLoop(while 1)
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ReadIDR[Leggi GPIOC->IDR\n(Stato Bottone)]:::hw
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Debounce[Debounce Delay]:::logic
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EdgeCheck{Rising Edge?\n(Curr=1 && Prev=0)}:::logic
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ToggleOps[Toggle Logic]:::memory
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UpdatePrev[Prev = Curr]:::logic
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MainLoop --> ReadIDR --> EdgeCheck
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EdgeCheck -- NO --> UpdatePrev
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EdgeCheck -- SI --> ToggleOps
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subgraph Toggle [Logica XOR LED]
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ReadODR[Leggi GPIOB->ODR]:::hw
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XOR[Calcola: ODR ^ LED_MASK]:::logic
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WriteODR[Scrivi GPIOB->ODR]:::hw
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ReadODR --> XOR --> WriteODR
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end
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ToggleOps --> UpdatePrev
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UpdatePrev --> Debounce --> MainLoop
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end
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%% --- BLOCCO INTERRUPT ---
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subgraph ISR [3. USART3 IRQ Handler]
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direction TB
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Trigger((IRQ))
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CheckTXE{Flag TXE?\n(Data Reg Empty)}:::logic
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CheckTC{Flag TC?\n(Tx Complete)}:::logic
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LoadDR[Scrivi USART3->DR\n(Invia Byte)]:::hw
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EnableTC[Abilita TCIE\nDisabilita TXEIE]:::hw
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DisableTC[Disabilita TCIE\nClear TC Flag]:::hw
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FreeBusy[Set tx_busy = 0]:::memory
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Trigger --> CheckTXE
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CheckTXE -- SI: Buffer Pieno --> LoadDR
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CheckTXE -- SI: Buffer Finito --> EnableTC
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CheckTXE -- NO --> CheckTC
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CheckTC -- SI: Fine Trasmissione --> DisableTC --> FreeBusy
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CheckTC -- NO --> Return((RTI))
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end
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%% --- CONNESSIONI LOGICHE ---
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WriteODR -.-> |Opzionale: Avvia TX| Trigger
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