PanSi21/ST-LAB-H7
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions
ST-LAB-H7/Debug/ST-LAB-H7.list
PanSi21 bea9ab0a3c
new muori
2025-11-13 02:45:43 +01:00

12121 lines
545 KiB
Text
Raw Blame History

ST-LAB-H7.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 00000298 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00005380 08000298 08000298 00001298 2**3
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000038 08005618 08005618 00006618 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM 00000008 08005650 08005650 00006650 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
4 .init_array 00000004 08005658 08005658 00006658 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .fini_array 00000004 0800565c 0800565c 0000665c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
6 .data 00000010 24000000 08005660 00007000 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .bss 00000168 24000010 08005670 00007010 2**3
ALLOC
8 ._user_heap_stack 00000600 24000178 08005670 00007178 2**0
ALLOC
9 .ARM.attributes 0000002e 00000000 00000000 00007010 2**0
CONTENTS, READONLY
10 .debug_info 00025c7c 00000000 00000000 0000703e 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
11 .debug_abbrev 00003d8b 00000000 00000000 0002ccba 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
12 .debug_loclists 0001376a 00000000 00000000 00030a45 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_aranges 00001200 00000000 00000000 000441b0 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_rnglists 00002166 00000000 00000000 000453b0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_macro 0003a1df 00000000 00000000 00047516 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_line 00027c93 00000000 00000000 000816f5 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_str 00178733 00000000 00000000 000a9388 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .comment 00000043 00000000 00000000 00221abb 2**0
CONTENTS, READONLY
19 .debug_frame 00003424 00000000 00000000 00221b00 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
20 .debug_line_str 00000060 00000000 00000000 00224f24 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
08000298 <__do_global_dtors_aux>:
8000298: b510 push {r4, lr}
800029a: 4c05 ldr r4, [pc, #20] @ (80002b0 <__do_global_dtors_aux+0x18>)
800029c: 7823 ldrb r3, [r4, #0]
800029e: b933 cbnz r3, 80002ae <__do_global_dtors_aux+0x16>
80002a0: 4b04 ldr r3, [pc, #16] @ (80002b4 <__do_global_dtors_aux+0x1c>)
80002a2: b113 cbz r3, 80002aa <__do_global_dtors_aux+0x12>
80002a4: 4804 ldr r0, [pc, #16] @ (80002b8 <__do_global_dtors_aux+0x20>)
80002a6: f3af 8000 nop.w
80002aa: 2301 movs r3, #1
80002ac: 7023 strb r3, [r4, #0]
80002ae: bd10 pop {r4, pc}
80002b0: 24000010 .word 0x24000010
80002b4: 00000000 .word 0x00000000
80002b8: 08005600 .word 0x08005600
080002bc <frame_dummy>:
80002bc: b508 push {r3, lr}
80002be: 4b03 ldr r3, [pc, #12] @ (80002cc <frame_dummy+0x10>)
80002c0: b11b cbz r3, 80002ca <frame_dummy+0xe>
80002c2: 4903 ldr r1, [pc, #12] @ (80002d0 <frame_dummy+0x14>)
80002c4: 4803 ldr r0, [pc, #12] @ (80002d4 <frame_dummy+0x18>)
80002c6: f3af 8000 nop.w
80002ca: bd08 pop {r3, pc}
80002cc: 00000000 .word 0x00000000
80002d0: 24000014 .word 0x24000014
80002d4: 08005600 .word 0x08005600
080002d8 <__aeabi_uldivmod>:
80002d8: b953 cbnz r3, 80002f0 <__aeabi_uldivmod+0x18>
80002da: b94a cbnz r2, 80002f0 <__aeabi_uldivmod+0x18>
80002dc: 2900 cmp r1, #0
80002de: bf08 it eq
80002e0: 2800 cmpeq r0, #0
80002e2: bf1c itt ne
80002e4: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
80002e8: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
80002ec: f000 b988 b.w 8000600 <__aeabi_idiv0>
80002f0: f1ad 0c08 sub.w ip, sp, #8
80002f4: e96d ce04 strd ip, lr, [sp, #-16]!
80002f8: f000 f806 bl 8000308 <__udivmoddi4>
80002fc: f8dd e004 ldr.w lr, [sp, #4]
8000300: e9dd 2302 ldrd r2, r3, [sp, #8]
8000304: b004 add sp, #16
8000306: 4770 bx lr
08000308 <__udivmoddi4>:
8000308: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
800030c: 9d08 ldr r5, [sp, #32]
800030e: 468e mov lr, r1
8000310: 4604 mov r4, r0
8000312: 4688 mov r8, r1
8000314: 2b00 cmp r3, #0
8000316: d14a bne.n 80003ae <__udivmoddi4+0xa6>
8000318: 428a cmp r2, r1
800031a: 4617 mov r7, r2
800031c: d962 bls.n 80003e4 <__udivmoddi4+0xdc>
800031e: fab2 f682 clz r6, r2
8000322: b14e cbz r6, 8000338 <__udivmoddi4+0x30>
8000324: f1c6 0320 rsb r3, r6, #32
8000328: fa01 f806 lsl.w r8, r1, r6
800032c: fa20 f303 lsr.w r3, r0, r3
8000330: 40b7 lsls r7, r6
8000332: ea43 0808 orr.w r8, r3, r8
8000336: 40b4 lsls r4, r6
8000338: ea4f 4e17 mov.w lr, r7, lsr #16
800033c: fa1f fc87 uxth.w ip, r7
8000340: fbb8 f1fe udiv r1, r8, lr
8000344: 0c23 lsrs r3, r4, #16
8000346: fb0e 8811 mls r8, lr, r1, r8
800034a: ea43 4308 orr.w r3, r3, r8, lsl #16
800034e: fb01 f20c mul.w r2, r1, ip
8000352: 429a cmp r2, r3
8000354: d909 bls.n 800036a <__udivmoddi4+0x62>
8000356: 18fb adds r3, r7, r3
8000358: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
800035c: f080 80ea bcs.w 8000534 <__udivmoddi4+0x22c>
8000360: 429a cmp r2, r3
8000362: f240 80e7 bls.w 8000534 <__udivmoddi4+0x22c>
8000366: 3902 subs r1, #2
8000368: 443b add r3, r7
800036a: 1a9a subs r2, r3, r2
800036c: b2a3 uxth r3, r4
800036e: fbb2 f0fe udiv r0, r2, lr
8000372: fb0e 2210 mls r2, lr, r0, r2
8000376: ea43 4302 orr.w r3, r3, r2, lsl #16
800037a: fb00 fc0c mul.w ip, r0, ip
800037e: 459c cmp ip, r3
8000380: d909 bls.n 8000396 <__udivmoddi4+0x8e>
8000382: 18fb adds r3, r7, r3
8000384: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
8000388: f080 80d6 bcs.w 8000538 <__udivmoddi4+0x230>
800038c: 459c cmp ip, r3
800038e: f240 80d3 bls.w 8000538 <__udivmoddi4+0x230>
8000392: 443b add r3, r7
8000394: 3802 subs r0, #2
8000396: ea40 4001 orr.w r0, r0, r1, lsl #16
800039a: eba3 030c sub.w r3, r3, ip
800039e: 2100 movs r1, #0
80003a0: b11d cbz r5, 80003aa <__udivmoddi4+0xa2>
80003a2: 40f3 lsrs r3, r6
80003a4: 2200 movs r2, #0
80003a6: e9c5 3200 strd r3, r2, [r5]
80003aa: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80003ae: 428b cmp r3, r1
80003b0: d905 bls.n 80003be <__udivmoddi4+0xb6>
80003b2: b10d cbz r5, 80003b8 <__udivmoddi4+0xb0>
80003b4: e9c5 0100 strd r0, r1, [r5]
80003b8: 2100 movs r1, #0
80003ba: 4608 mov r0, r1
80003bc: e7f5 b.n 80003aa <__udivmoddi4+0xa2>
80003be: fab3 f183 clz r1, r3
80003c2: 2900 cmp r1, #0
80003c4: d146 bne.n 8000454 <__udivmoddi4+0x14c>
80003c6: 4573 cmp r3, lr
80003c8: d302 bcc.n 80003d0 <__udivmoddi4+0xc8>
80003ca: 4282 cmp r2, r0
80003cc: f200 8105 bhi.w 80005da <__udivmoddi4+0x2d2>
80003d0: 1a84 subs r4, r0, r2
80003d2: eb6e 0203 sbc.w r2, lr, r3
80003d6: 2001 movs r0, #1
80003d8: 4690 mov r8, r2
80003da: 2d00 cmp r5, #0
80003dc: d0e5 beq.n 80003aa <__udivmoddi4+0xa2>
80003de: e9c5 4800 strd r4, r8, [r5]
80003e2: e7e2 b.n 80003aa <__udivmoddi4+0xa2>
80003e4: 2a00 cmp r2, #0
80003e6: f000 8090 beq.w 800050a <__udivmoddi4+0x202>
80003ea: fab2 f682 clz r6, r2
80003ee: 2e00 cmp r6, #0
80003f0: f040 80a4 bne.w 800053c <__udivmoddi4+0x234>
80003f4: 1a8a subs r2, r1, r2
80003f6: 0c03 lsrs r3, r0, #16
80003f8: ea4f 4e17 mov.w lr, r7, lsr #16
80003fc: b280 uxth r0, r0
80003fe: b2bc uxth r4, r7
8000400: 2101 movs r1, #1
8000402: fbb2 fcfe udiv ip, r2, lr
8000406: fb0e 221c mls r2, lr, ip, r2
800040a: ea43 4302 orr.w r3, r3, r2, lsl #16
800040e: fb04 f20c mul.w r2, r4, ip
8000412: 429a cmp r2, r3
8000414: d907 bls.n 8000426 <__udivmoddi4+0x11e>
8000416: 18fb adds r3, r7, r3
8000418: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
800041c: d202 bcs.n 8000424 <__udivmoddi4+0x11c>
800041e: 429a cmp r2, r3
8000420: f200 80e0 bhi.w 80005e4 <__udivmoddi4+0x2dc>
8000424: 46c4 mov ip, r8
8000426: 1a9b subs r3, r3, r2
8000428: fbb3 f2fe udiv r2, r3, lr
800042c: fb0e 3312 mls r3, lr, r2, r3
8000430: ea40 4303 orr.w r3, r0, r3, lsl #16
8000434: fb02 f404 mul.w r4, r2, r4
8000438: 429c cmp r4, r3
800043a: d907 bls.n 800044c <__udivmoddi4+0x144>
800043c: 18fb adds r3, r7, r3
800043e: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
8000442: d202 bcs.n 800044a <__udivmoddi4+0x142>
8000444: 429c cmp r4, r3
8000446: f200 80ca bhi.w 80005de <__udivmoddi4+0x2d6>
800044a: 4602 mov r2, r0
800044c: 1b1b subs r3, r3, r4
800044e: ea42 400c orr.w r0, r2, ip, lsl #16
8000452: e7a5 b.n 80003a0 <__udivmoddi4+0x98>
8000454: f1c1 0620 rsb r6, r1, #32
8000458: 408b lsls r3, r1
800045a: fa22 f706 lsr.w r7, r2, r6
800045e: 431f orrs r7, r3
8000460: fa0e f401 lsl.w r4, lr, r1
8000464: fa20 f306 lsr.w r3, r0, r6
8000468: fa2e fe06 lsr.w lr, lr, r6
800046c: ea4f 4917 mov.w r9, r7, lsr #16
8000470: 4323 orrs r3, r4
8000472: fa00 f801 lsl.w r8, r0, r1
8000476: fa1f fc87 uxth.w ip, r7
800047a: fbbe f0f9 udiv r0, lr, r9
800047e: 0c1c lsrs r4, r3, #16
8000480: fb09 ee10 mls lr, r9, r0, lr
8000484: ea44 440e orr.w r4, r4, lr, lsl #16
8000488: fb00 fe0c mul.w lr, r0, ip
800048c: 45a6 cmp lr, r4
800048e: fa02 f201 lsl.w r2, r2, r1
8000492: d909 bls.n 80004a8 <__udivmoddi4+0x1a0>
8000494: 193c adds r4, r7, r4
8000496: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff
800049a: f080 809c bcs.w 80005d6 <__udivmoddi4+0x2ce>
800049e: 45a6 cmp lr, r4
80004a0: f240 8099 bls.w 80005d6 <__udivmoddi4+0x2ce>
80004a4: 3802 subs r0, #2
80004a6: 443c add r4, r7
80004a8: eba4 040e sub.w r4, r4, lr
80004ac: fa1f fe83 uxth.w lr, r3
80004b0: fbb4 f3f9 udiv r3, r4, r9
80004b4: fb09 4413 mls r4, r9, r3, r4
80004b8: ea4e 4404 orr.w r4, lr, r4, lsl #16
80004bc: fb03 fc0c mul.w ip, r3, ip
80004c0: 45a4 cmp ip, r4
80004c2: d908 bls.n 80004d6 <__udivmoddi4+0x1ce>
80004c4: 193c adds r4, r7, r4
80004c6: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff
80004ca: f080 8082 bcs.w 80005d2 <__udivmoddi4+0x2ca>
80004ce: 45a4 cmp ip, r4
80004d0: d97f bls.n 80005d2 <__udivmoddi4+0x2ca>
80004d2: 3b02 subs r3, #2
80004d4: 443c add r4, r7
80004d6: ea43 4000 orr.w r0, r3, r0, lsl #16
80004da: eba4 040c sub.w r4, r4, ip
80004de: fba0 ec02 umull lr, ip, r0, r2
80004e2: 4564 cmp r4, ip
80004e4: 4673 mov r3, lr
80004e6: 46e1 mov r9, ip
80004e8: d362 bcc.n 80005b0 <__udivmoddi4+0x2a8>
80004ea: d05f beq.n 80005ac <__udivmoddi4+0x2a4>
80004ec: b15d cbz r5, 8000506 <__udivmoddi4+0x1fe>
80004ee: ebb8 0203 subs.w r2, r8, r3
80004f2: eb64 0409 sbc.w r4, r4, r9
80004f6: fa04 f606 lsl.w r6, r4, r6
80004fa: fa22 f301 lsr.w r3, r2, r1
80004fe: 431e orrs r6, r3
8000500: 40cc lsrs r4, r1
8000502: e9c5 6400 strd r6, r4, [r5]
8000506: 2100 movs r1, #0
8000508: e74f b.n 80003aa <__udivmoddi4+0xa2>
800050a: fbb1 fcf2 udiv ip, r1, r2
800050e: 0c01 lsrs r1, r0, #16
8000510: ea41 410e orr.w r1, r1, lr, lsl #16
8000514: b280 uxth r0, r0
8000516: ea40 4201 orr.w r2, r0, r1, lsl #16
800051a: 463b mov r3, r7
800051c: 4638 mov r0, r7
800051e: 463c mov r4, r7
8000520: 46b8 mov r8, r7
8000522: 46be mov lr, r7
8000524: 2620 movs r6, #32
8000526: fbb1 f1f7 udiv r1, r1, r7
800052a: eba2 0208 sub.w r2, r2, r8
800052e: ea41 410c orr.w r1, r1, ip, lsl #16
8000532: e766 b.n 8000402 <__udivmoddi4+0xfa>
8000534: 4601 mov r1, r0
8000536: e718 b.n 800036a <__udivmoddi4+0x62>
8000538: 4610 mov r0, r2
800053a: e72c b.n 8000396 <__udivmoddi4+0x8e>
800053c: f1c6 0220 rsb r2, r6, #32
8000540: fa2e f302 lsr.w r3, lr, r2
8000544: 40b7 lsls r7, r6
8000546: 40b1 lsls r1, r6
8000548: fa20 f202 lsr.w r2, r0, r2
800054c: ea4f 4e17 mov.w lr, r7, lsr #16
8000550: 430a orrs r2, r1
8000552: fbb3 f8fe udiv r8, r3, lr
8000556: b2bc uxth r4, r7
8000558: fb0e 3318 mls r3, lr, r8, r3
800055c: 0c11 lsrs r1, r2, #16
800055e: ea41 4103 orr.w r1, r1, r3, lsl #16
8000562: fb08 f904 mul.w r9, r8, r4
8000566: 40b0 lsls r0, r6
8000568: 4589 cmp r9, r1
800056a: ea4f 4310 mov.w r3, r0, lsr #16
800056e: b280 uxth r0, r0
8000570: d93e bls.n 80005f0 <__udivmoddi4+0x2e8>
8000572: 1879 adds r1, r7, r1
8000574: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
8000578: d201 bcs.n 800057e <__udivmoddi4+0x276>
800057a: 4589 cmp r9, r1
800057c: d81f bhi.n 80005be <__udivmoddi4+0x2b6>
800057e: eba1 0109 sub.w r1, r1, r9
8000582: fbb1 f9fe udiv r9, r1, lr
8000586: fb09 f804 mul.w r8, r9, r4
800058a: fb0e 1119 mls r1, lr, r9, r1
800058e: b292 uxth r2, r2
8000590: ea42 4201 orr.w r2, r2, r1, lsl #16
8000594: 4542 cmp r2, r8
8000596: d229 bcs.n 80005ec <__udivmoddi4+0x2e4>
8000598: 18ba adds r2, r7, r2
800059a: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
800059e: d2c4 bcs.n 800052a <__udivmoddi4+0x222>
80005a0: 4542 cmp r2, r8
80005a2: d2c2 bcs.n 800052a <__udivmoddi4+0x222>
80005a4: f1a9 0102 sub.w r1, r9, #2
80005a8: 443a add r2, r7
80005aa: e7be b.n 800052a <__udivmoddi4+0x222>
80005ac: 45f0 cmp r8, lr
80005ae: d29d bcs.n 80004ec <__udivmoddi4+0x1e4>
80005b0: ebbe 0302 subs.w r3, lr, r2
80005b4: eb6c 0c07 sbc.w ip, ip, r7
80005b8: 3801 subs r0, #1
80005ba: 46e1 mov r9, ip
80005bc: e796 b.n 80004ec <__udivmoddi4+0x1e4>
80005be: eba7 0909 sub.w r9, r7, r9
80005c2: 4449 add r1, r9
80005c4: f1a8 0c02 sub.w ip, r8, #2
80005c8: fbb1 f9fe udiv r9, r1, lr
80005cc: fb09 f804 mul.w r8, r9, r4
80005d0: e7db b.n 800058a <__udivmoddi4+0x282>
80005d2: 4673 mov r3, lr
80005d4: e77f b.n 80004d6 <__udivmoddi4+0x1ce>
80005d6: 4650 mov r0, sl
80005d8: e766 b.n 80004a8 <__udivmoddi4+0x1a0>
80005da: 4608 mov r0, r1
80005dc: e6fd b.n 80003da <__udivmoddi4+0xd2>
80005de: 443b add r3, r7
80005e0: 3a02 subs r2, #2
80005e2: e733 b.n 800044c <__udivmoddi4+0x144>
80005e4: f1ac 0c02 sub.w ip, ip, #2
80005e8: 443b add r3, r7
80005ea: e71c b.n 8000426 <__udivmoddi4+0x11e>
80005ec: 4649 mov r1, r9
80005ee: e79c b.n 800052a <__udivmoddi4+0x222>
80005f0: eba1 0109 sub.w r1, r1, r9
80005f4: 46c4 mov ip, r8
80005f6: fbb1 f9fe udiv r9, r1, lr
80005fa: fb09 f804 mul.w r8, r9, r4
80005fe: e7c4 b.n 800058a <__udivmoddi4+0x282>
08000600 <__aeabi_idiv0>:
8000600: 4770 bx lr
8000602: bf00 nop
08000604 <MX_ADC3_Init>:
ADC_HandleTypeDef hadc3;
/* ADC3 init function */
void MX_ADC3_Init(void)
{
8000604: b510 push {r4, lr}
/* USER CODE BEGIN ADC3_Init 0 */
/* USER CODE END ADC3_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
8000606: 2300 movs r3, #0
{
8000608: b088 sub sp, #32
/* USER CODE END ADC3_Init 1 */
/** Common config
*/
hadc3.Instance = ADC3;
800060a: 481d ldr r0, [pc, #116] @ (8000680 <MX_ADC3_Init+0x7c>)
hadc3.Init.Resolution = ADC_RESOLUTION_16B;
hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE;
hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
hadc3.Init.LowPowerAutoWait = DISABLE;
hadc3.Init.ContinuousConvMode = DISABLE;
hadc3.Init.NbrOfConversion = 1;
800060c: 2201 movs r2, #1
hadc3.Instance = ADC3;
800060e: 4c1d ldr r4, [pc, #116] @ (8000684 <MX_ADC3_Init+0x80>)
hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
8000610: 2104 movs r1, #4
ADC_ChannelConfTypeDef sConfig = {0};
8000612: 9301 str r3, [sp, #4]
hadc3.Instance = ADC3;
8000614: 6004 str r4, [r0, #0]
hadc3.Init.LowPowerAutoWait = DISABLE;
8000616: 8283 strh r3, [r0, #20]
hadc3.Init.NbrOfConversion = 1;
8000618: 6182 str r2, [r0, #24]
hadc3.Init.DiscontinuousConvMode = DISABLE;
800061a: 7703 strb r3, [r0, #28]
hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START;
hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
hadc3.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR;
hadc3.Init.Overrun = ADC_OVR_DATA_PRESERVED;
hadc3.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
800061c: 6343 str r3, [r0, #52] @ 0x34
hadc3.Init.OversamplingMode = DISABLE;
800061e: f880 3038 strb.w r3, [r0, #56] @ 0x38
hadc3.Init.Oversampling.Ratio = 1;
8000622: 63c2 str r2, [r0, #60] @ 0x3c
hadc3.Init.Resolution = ADC_RESOLUTION_16B;
8000624: e9c0 3301 strd r3, r3, [r0, #4]
hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
8000628: e9c0 3103 strd r3, r1, [r0, #12]
hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
800062c: e9c0 3309 strd r3, r3, [r0, #36] @ 0x24
hadc3.Init.Overrun = ADC_OVR_DATA_PRESERVED;
8000630: e9c0 330b strd r3, r3, [r0, #44] @ 0x2c
ADC_ChannelConfTypeDef sConfig = {0};
8000634: e9cd 3302 strd r3, r3, [sp, #8]
8000638: e9cd 3304 strd r3, r3, [sp, #16]
800063c: e9cd 3306 strd r3, r3, [sp, #24]
if (HAL_ADC_Init(&hadc3) != HAL_OK)
8000640: f000 ffe8 bl 8001614 <HAL_ADC_Init>
8000644: b9a0 cbnz r0, 8000670 <MX_ADC3_Init+0x6c>
Error_Handler();
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
8000646: 4810 ldr r0, [pc, #64] @ (8000688 <MX_ADC3_Init+0x84>)
sConfig.Rank = ADC_REGULAR_RANK_1;
8000648: 2206 movs r2, #6
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
800064a: 2300 movs r3, #0
sConfig.SingleDiff = ADC_SINGLE_ENDED;
800064c: f240 74ff movw r4, #2047 @ 0x7ff
sConfig.OffsetNumber = ADC_OFFSET_NONE;
sConfig.Offset = 0;
sConfig.OffsetSignedSaturation = DISABLE;
if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
8000650: a901 add r1, sp, #4
sConfig.OffsetSignedSaturation = DISABLE;
8000652: f88d 301d strb.w r3, [sp, #29]
sConfig.Rank = ADC_REGULAR_RANK_1;
8000656: e9cd 0201 strd r0, r2, [sp, #4]
sConfig.OffsetNumber = ADC_OFFSET_NONE;
800065a: 2204 movs r2, #4
if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
800065c: 4808 ldr r0, [pc, #32] @ (8000680 <MX_ADC3_Init+0x7c>)
sConfig.SingleDiff = ADC_SINGLE_ENDED;
800065e: e9cd 3403 strd r3, r4, [sp, #12]
sConfig.Offset = 0;
8000662: e9cd 2305 strd r2, r3, [sp, #20]
if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
8000666: f000 fd17 bl 8001098 <HAL_ADC_ConfigChannel>
800066a: b920 cbnz r0, 8000676 <MX_ADC3_Init+0x72>
}
/* USER CODE BEGIN ADC3_Init 2 */
/* USER CODE END ADC3_Init 2 */
}
800066c: b008 add sp, #32
800066e: bd10 pop {r4, pc}
Error_Handler();
8000670: f000 f968 bl 8000944 <Error_Handler>
8000674: e7e7 b.n 8000646 <MX_ADC3_Init+0x42>
Error_Handler();
8000676: f000 f965 bl 8000944 <Error_Handler>
}
800067a: b008 add sp, #32
800067c: bd10 pop {r4, pc}
800067e: bf00 nop
8000680: 2400002c .word 0x2400002c
8000684: 58026000 .word 0x58026000
8000688: cb840000 .word 0xcb840000
0800068c <HAL_ADC_MspInit>:
void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
{
if(adcHandle->Instance==ADC3)
800068c: 4b0f ldr r3, [pc, #60] @ (80006cc <HAL_ADC_MspInit+0x40>)
800068e: 6802 ldr r2, [r0, #0]
8000690: 429a cmp r2, r3
8000692: d000 beq.n 8000696 <HAL_ADC_MspInit+0xa>
8000694: 4770 bx lr
{
/* USER CODE BEGIN ADC3_MspInit 0 */
/* USER CODE END ADC3_MspInit 0 */
/* ADC3 clock enable */
__HAL_RCC_ADC3_CLK_ENABLE();
8000696: f5a3 53e0 sub.w r3, r3, #7168 @ 0x1c00
/* ADC3 interrupt Init */
HAL_NVIC_SetPriority(ADC3_IRQn, 0, 0);
800069a: 2200 movs r2, #0
800069c: 207f movs r0, #127 @ 0x7f
800069e: 4611 mov r1, r2
{
80006a0: b510 push {r4, lr}
__HAL_RCC_ADC3_CLK_ENABLE();
80006a2: f8d3 40e0 ldr.w r4, [r3, #224] @ 0xe0
{
80006a6: b082 sub sp, #8
__HAL_RCC_ADC3_CLK_ENABLE();
80006a8: f044 7480 orr.w r4, r4, #16777216 @ 0x1000000
80006ac: f8c3 40e0 str.w r4, [r3, #224] @ 0xe0
80006b0: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0
80006b4: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
80006b8: 9301 str r3, [sp, #4]
80006ba: 9b01 ldr r3, [sp, #4]
HAL_NVIC_SetPriority(ADC3_IRQn, 0, 0);
80006bc: f001 f8d2 bl 8001864 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(ADC3_IRQn);
80006c0: 207f movs r0, #127 @ 0x7f
/* USER CODE BEGIN ADC3_MspInit 1 */
/* USER CODE END ADC3_MspInit 1 */
}
}
80006c2: b002 add sp, #8
80006c4: e8bd 4010 ldmia.w sp!, {r4, lr}
HAL_NVIC_EnableIRQ(ADC3_IRQn);
80006c8: f001 b908 b.w 80018dc <HAL_NVIC_EnableIRQ>
80006cc: 58026000 .word 0x58026000
080006d0 <MX_GPIO_Init>:
PH1-OSC_OUT (PH1) ------> RCC_OSC_OUT
PA13 (JTMS/SWDIO) ------> DEBUG_JTMS-SWDIO
PA14 (JTCK/SWCLK) ------> DEBUG_JTCK-SWCLK
*/
void MX_GPIO_Init(void)
{
80006d0: b570 push {r4, r5, r6, lr}
GPIO_InitTypeDef GPIO_InitStruct = {0};
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
80006d2: 4b3e ldr r3, [pc, #248] @ (80007cc <MX_GPIO_Init+0xfc>)
{
80006d4: b08c sub sp, #48 @ 0x30
GPIO_InitTypeDef GPIO_InitStruct = {0};
80006d6: 2400 movs r4, #0
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, LD1_Pin|LD3_Pin, GPIO_PIN_RESET);
80006d8: 4d3d ldr r5, [pc, #244] @ (80007d0 <MX_GPIO_Init+0x100>)
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
80006da: 4e3e ldr r6, [pc, #248] @ (80007d4 <MX_GPIO_Init+0x104>)
HAL_GPIO_WritePin(GPIOB, LD1_Pin|LD3_Pin, GPIO_PIN_RESET);
80006dc: f244 0101 movw r1, #16385 @ 0x4001
GPIO_InitTypeDef GPIO_InitStruct = {0};
80006e0: 940a str r4, [sp, #40] @ 0x28
HAL_GPIO_WritePin(GPIOB, LD1_Pin|LD3_Pin, GPIO_PIN_RESET);
80006e2: 4628 mov r0, r5
GPIO_InitTypeDef GPIO_InitStruct = {0};
80006e4: e9cd 4406 strd r4, r4, [sp, #24]
80006e8: e9cd 4408 strd r4, r4, [sp, #32]
__HAL_RCC_GPIOC_CLK_ENABLE();
80006ec: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
80006f0: f042 0204 orr.w r2, r2, #4
80006f4: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0
80006f8: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
80006fc: f002 0204 and.w r2, r2, #4
8000700: 9200 str r2, [sp, #0]
8000702: 9a00 ldr r2, [sp, #0]
__HAL_RCC_GPIOH_CLK_ENABLE();
8000704: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
8000708: f042 0280 orr.w r2, r2, #128 @ 0x80
800070c: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0
8000710: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
8000714: f002 0280 and.w r2, r2, #128 @ 0x80
8000718: 9201 str r2, [sp, #4]
800071a: 9a01 ldr r2, [sp, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
800071c: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
8000720: f042 0202 orr.w r2, r2, #2
8000724: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0
8000728: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
800072c: f002 0202 and.w r2, r2, #2
8000730: 9202 str r2, [sp, #8]
8000732: 9a02 ldr r2, [sp, #8]
__HAL_RCC_GPIOD_CLK_ENABLE();
8000734: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
8000738: f042 0208 orr.w r2, r2, #8
800073c: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0
8000740: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
8000744: f002 0208 and.w r2, r2, #8
8000748: 9203 str r2, [sp, #12]
800074a: 9a03 ldr r2, [sp, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
800074c: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
8000750: f042 0201 orr.w r2, r2, #1
8000754: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0
8000758: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
800075c: f002 0201 and.w r2, r2, #1
8000760: 9204 str r2, [sp, #16]
8000762: 9a04 ldr r2, [sp, #16]
__HAL_RCC_GPIOE_CLK_ENABLE();
8000764: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
8000768: f042 0210 orr.w r2, r2, #16
800076c: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0
HAL_GPIO_WritePin(GPIOB, LD1_Pin|LD3_Pin, GPIO_PIN_RESET);
8000770: 4622 mov r2, r4
__HAL_RCC_GPIOE_CLK_ENABLE();
8000772: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0
8000776: f003 0310 and.w r3, r3, #16
800077a: 9305 str r3, [sp, #20]
800077c: 9b05 ldr r3, [sp, #20]
HAL_GPIO_WritePin(GPIOB, LD1_Pin|LD3_Pin, GPIO_PIN_RESET);
800077e: f001 fda5 bl 80022cc <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
8000782: 4622 mov r2, r4
8000784: 4630 mov r0, r6
8000786: 2102 movs r1, #2
8000788: f001 fda0 bl 80022cc <HAL_GPIO_WritePin>
/*Configure GPIO pin : B1_Pin */
GPIO_InitStruct.Pin = B1_Pin;
800078c: f44f 5200 mov.w r2, #8192 @ 0x2000
8000790: 2300 movs r3, #0
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
8000792: a906 add r1, sp, #24
8000794: 4810 ldr r0, [pc, #64] @ (80007d8 <MX_GPIO_Init+0x108>)
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000796: 9408 str r4, [sp, #32]
GPIO_InitStruct.Pin = B1_Pin;
8000798: e9cd 2306 strd r2, r3, [sp, #24]
HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
800079c: f001 fb90 bl 8001ec0 <HAL_GPIO_Init>
/*Configure GPIO pins : LD1_Pin LD3_Pin */
GPIO_InitStruct.Pin = LD1_Pin|LD3_Pin;
80007a0: f244 0301 movw r3, #16385 @ 0x4001
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80007a4: 4628 mov r0, r5
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80007a6: 2501 movs r5, #1
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80007a8: a906 add r1, sp, #24
GPIO_InitStruct.Pin = LD1_Pin|LD3_Pin;
80007aa: 9306 str r3, [sp, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80007ac: 9408 str r4, [sp, #32]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80007ae: 9409 str r4, [sp, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80007b0: 9507 str r5, [sp, #28]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80007b2: f001 fb85 bl 8001ec0 <HAL_GPIO_Init>
/*Configure GPIO pin : LD2_Pin */
GPIO_InitStruct.Pin = LD2_Pin;
80007b6: 2302 movs r3, #2
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
80007b8: a906 add r1, sp, #24
80007ba: 4630 mov r0, r6
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80007bc: e9cd 3506 strd r3, r5, [sp, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80007c0: e9cd 4408 strd r4, r4, [sp, #32]
HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
80007c4: f001 fb7c bl 8001ec0 <HAL_GPIO_Init>
}
80007c8: b00c add sp, #48 @ 0x30
80007ca: bd70 pop {r4, r5, r6, pc}
80007cc: 58024400 .word 0x58024400
80007d0: 58020400 .word 0x58020400
80007d4: 58021000 .word 0x58021000
80007d8: 58020800 .word 0x58020800
080007dc <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void) {
80007dc: b510 push {r4, lr}
80007de: b09e sub sp, #120 @ 0x78
RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
80007e0: 224c movs r2, #76 @ 0x4c
80007e2: 2100 movs r1, #0
80007e4: a80a add r0, sp, #40 @ 0x28
80007e6: f004 fedf bl 80055a8 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
80007ea: 2220 movs r2, #32
80007ec: 2100 movs r1, #0
80007ee: a802 add r0, sp, #8
80007f0: f004 feda bl 80055a8 <memset>
/** Supply configuration update enable
*/
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
80007f4: 2002 movs r0, #2
80007f6: f001 fd6d bl 80022d4 <HAL_PWREx_ConfigSupply>
/** Configure the main internal regulator output voltage
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
80007fa: 4a24 ldr r2, [pc, #144] @ (800088c <SystemClock_Config+0xb0>)
80007fc: 2100 movs r1, #0
80007fe: 4b24 ldr r3, [pc, #144] @ (8000890 <SystemClock_Config+0xb4>)
8000800: 9101 str r1, [sp, #4]
8000802: 6991 ldr r1, [r2, #24]
8000804: f441 4140 orr.w r1, r1, #49152 @ 0xc000
8000808: 6191 str r1, [r2, #24]
800080a: 6991 ldr r1, [r2, #24]
800080c: f401 4140 and.w r1, r1, #49152 @ 0xc000
8000810: 9101 str r1, [sp, #4]
8000812: 6ad9 ldr r1, [r3, #44] @ 0x2c
8000814: f041 0101 orr.w r1, r1, #1
8000818: 62d9 str r1, [r3, #44] @ 0x2c
800081a: 6adb ldr r3, [r3, #44] @ 0x2c
800081c: f003 0301 and.w r3, r3, #1
8000820: 9301 str r3, [sp, #4]
8000822: 9b01 ldr r3, [sp, #4]
while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {
8000824: 6993 ldr r3, [r2, #24]
8000826: 049b lsls r3, r3, #18
8000828: d5fc bpl.n 8000824 <SystemClock_Config+0x48>
}
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
800082a: 2001 movs r0, #1
800082c: f44f 21a0 mov.w r1, #327680 @ 0x50000
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000830: 2302 movs r3, #2
RCC_OscInitStruct.PLL.PLLN = 192;
RCC_OscInitStruct.PLL.PLLP = 2;
RCC_OscInitStruct.PLL.PLLQ = 2;
RCC_OscInitStruct.PLL.PLLR = 2;
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
8000832: 2200 movs r2, #0
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
8000834: 2408 movs r4, #8
RCC_OscInitStruct.PLL.PLLR = 2;
8000836: 9319 str r3, [sp, #100] @ 0x64
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
8000838: 941a str r4, [sp, #104] @ 0x68
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
800083a: e9cd 010a strd r0, r1, [sp, #40] @ 0x28
RCC_OscInitStruct.PLL.PLLM = 5;
800083e: 2105 movs r1, #5
RCC_OscInitStruct.PLL.PLLFRACN = 0;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
8000840: a80a add r0, sp, #40 @ 0x28
RCC_OscInitStruct.PLL.PLLM = 5;
8000842: 9115 str r1, [sp, #84] @ 0x54
RCC_OscInitStruct.PLL.PLLN = 192;
8000844: 21c0 movs r1, #192 @ 0xc0
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
8000846: e9cd 3313 strd r3, r3, [sp, #76] @ 0x4c
RCC_OscInitStruct.PLL.PLLQ = 2;
800084a: e9cd 3317 strd r3, r3, [sp, #92] @ 0x5c
RCC_OscInitStruct.PLL.PLLN = 192;
800084e: 9116 str r1, [sp, #88] @ 0x58
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
8000850: e9cd 221b strd r2, r2, [sp, #108] @ 0x6c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
8000854: f001 fdd4 bl 8002400 <HAL_RCC_OscConfig>
8000858: 4603 mov r3, r0
800085a: b108 cbz r0, 8000860 <SystemClock_Config+0x84>
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
800085c: b672 cpsid i
*/
void Error_Handler(void) {
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1) {
800085e: e7fe b.n 800085e <SystemClock_Config+0x82>
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
8000860: 213f movs r1, #63 @ 0x3f
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
8000862: 2240 movs r2, #64 @ 0x40
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
8000864: 9304 str r3, [sp, #16]
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
8000866: f44f 6380 mov.w r3, #1024 @ 0x400
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
800086a: 9102 str r1, [sp, #8]
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
800086c: 2103 movs r1, #3
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
800086e: a802 add r0, sp, #8
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
8000870: 9207 str r2, [sp, #28]
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000872: 9103 str r1, [sp, #12]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
8000874: 2104 movs r1, #4
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
8000876: e9cd 4205 strd r4, r2, [sp, #20]
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
800087a: e9cd 3208 strd r3, r2, [sp, #32]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
800087e: f002 f93b bl 8002af8 <HAL_RCC_ClockConfig>
8000882: b108 cbz r0, 8000888 <SystemClock_Config+0xac>
8000884: b672 cpsid i
while (1) {
8000886: e7fe b.n 8000886 <SystemClock_Config+0xaa>
}
8000888: b01e add sp, #120 @ 0x78
800088a: bd10 pop {r4, pc}
800088c: 58024800 .word 0x58024800
8000890: 58000400 .word 0x58000400
8000894: 00000000 .word 0x00000000
08000898 <PeriphCommonClock_Config>:
void PeriphCommonClock_Config(void) {
8000898: b500 push {lr}
800089a: b0b1 sub sp, #196 @ 0xc4
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
800089c: 229c movs r2, #156 @ 0x9c
800089e: 2100 movs r1, #0
80008a0: a809 add r0, sp, #36 @ 0x24
80008a2: f004 fe81 bl 80055a8 <memset>
PeriphClkInitStruct.PLL2.PLL2M = 2;
80008a6: 2302 movs r3, #2
PeriphClkInitStruct.PLL2.PLL2N = 12;
80008a8: 210c movs r1, #12
PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOMEDIUM;
80008aa: 2220 movs r2, #32
PeriphClkInitStruct.PLL2.PLL2M = 2;
80008ac: 9302 str r3, [sp, #8]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
80008ae: 4668 mov r0, sp
PeriphClkInitStruct.PLL2.PLL2P = 2;
80008b0: 9304 str r3, [sp, #16]
PeriphClkInitStruct.PLL2.PLL2Q = 2;
80008b2: 9305 str r3, [sp, #20]
PeriphClkInitStruct.Usart234578ClockSelection =
80008b4: 2301 movs r3, #1
PeriphClkInitStruct.PLL2.PLL2N = 12;
80008b6: 9103 str r1, [sp, #12]
PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOMEDIUM;
80008b8: 9208 str r2, [sp, #32]
PeriphClkInitStruct.Usart234578ClockSelection =
80008ba: 931e str r3, [sp, #120] @ 0x78
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC
80008bc: ed9f 7b08 vldr d7, [pc, #32] @ 80008e0 <PeriphCommonClock_Config+0x48>
80008c0: ed8d 7b00 vstr d7, [sp]
PeriphClkInitStruct.PLL2.PLL2R = 2;
80008c4: ed9f 7b08 vldr d7, [pc, #32] @ 80008e8 <PeriphCommonClock_Config+0x50>
80008c8: ed8d 7b06 vstr d7, [sp, #24]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
80008cc: f002 fbee bl 80030ac <HAL_RCCEx_PeriphCLKConfig>
80008d0: b108 cbz r0, 80008d6 <PeriphCommonClock_Config+0x3e>
80008d2: b672 cpsid i
while (1) {
80008d4: e7fe b.n 80008d4 <PeriphCommonClock_Config+0x3c>
}
80008d6: b031 add sp, #196 @ 0xc4
80008d8: f85d fb04 ldr.w pc, [sp], #4
80008dc: f3af 8000 nop.w
80008e0: 00080002 .word 0x00080002
80008e4: 00000000 .word 0x00000000
80008e8: 00000002 .word 0x00000002
80008ec: 000000c0 .word 0x000000c0
080008f0 <main>:
int main(void) {
80008f0: b510 push {r4, lr}
MPU_Region_InitTypeDef MPU_InitStruct = { 0 };
80008f2: 2400 movs r4, #0
int main(void) {
80008f4: b084 sub sp, #16
MPU_Region_InitTypeDef MPU_InitStruct = { 0 };
80008f6: e9cd 4400 strd r4, r4, [sp]
80008fa: e9cd 4402 strd r4, r4, [sp, #8]
HAL_MPU_Disable();
80008fe: f001 f811 bl 8001924 <HAL_MPU_Disable>
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
8000902: 2101 movs r1, #1
MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
8000904: f248 721f movw r2, #34591 @ 0x871f
8000908: f240 1301 movw r3, #257 @ 0x101
HAL_MPU_ConfigRegion(&MPU_InitStruct);
800090c: 4668 mov r0, sp
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
800090e: f8ad 1000 strh.w r1, [sp]
MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
8000912: 9303 str r3, [sp, #12]
8000914: e9cd 4201 strd r4, r2, [sp, #4]
HAL_MPU_ConfigRegion(&MPU_InitStruct);
8000918: f001 f822 bl 8001960 <HAL_MPU_ConfigRegion>
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
800091c: 2004 movs r0, #4
800091e: f001 f80f bl 8001940 <HAL_MPU_Enable>
HAL_Init();
8000922: f000 fa1d bl 8000d60 <HAL_Init>
SystemClock_Config();
8000926: f7ff ff59 bl 80007dc <SystemClock_Config>
PeriphCommonClock_Config();
800092a: f7ff ffb5 bl 8000898 <PeriphCommonClock_Config>
MX_GPIO_Init();
800092e: f7ff fecf bl 80006d0 <MX_GPIO_Init>
MX_ADC3_Init();
8000932: f7ff fe67 bl 8000604 <MX_ADC3_Init>
MX_TIM6_Init();
8000936: f000 f8e7 bl 8000b08 <MX_TIM6_Init>
MX_USART3_UART_Init();
800093a: f000 f933 bl 8000ba4 <MX_USART3_UART_Init>
MOTD_init();
800093e: f000 f803 bl 8000948 <MOTD_init>
while (1) {
8000942: e7fc b.n 800093e <main+0x4e>
08000944 <Error_Handler>:
8000944: b672 cpsid i
while (1) {
8000946: e7fe b.n 8000946 <Error_Handler+0x2>
08000948 <MOTD_init>:
* @brief Funzione di Accensione onBoard
*
* Permette di far accendere e spegnere contemporaneamente tutti i leg
* presenti sulla board.
*/
void MOTD_init(void) {
8000948: b538 push {r3, r4, r5, lr}
HAL_Delay(1000);
GPIOB->BSRR |= GPIO_BSRR_BS0;
800094a: 4c11 ldr r4, [pc, #68] @ (8000990 <MOTD_init+0x48>)
HAL_Delay(1000);
800094c: f44f 707a mov.w r0, #1000 @ 0x3e8
8000950: f000 fa48 bl 8000de4 <HAL_Delay>
GPIOB->BSRR |= GPIO_BSRR_BS14;
GPIOE->BSRR |= GPIO_BSRR_BS1;
8000954: 4d0f ldr r5, [pc, #60] @ (8000994 <MOTD_init+0x4c>)
GPIOB->BSRR |= GPIO_BSRR_BS0;
8000956: 69a3 ldr r3, [r4, #24]
HAL_Delay(1000);
8000958: f44f 707a mov.w r0, #1000 @ 0x3e8
GPIOB->BSRR |= GPIO_BSRR_BS0;
800095c: f043 0301 orr.w r3, r3, #1
8000960: 61a3 str r3, [r4, #24]
GPIOB->BSRR |= GPIO_BSRR_BS14;
8000962: 69a3 ldr r3, [r4, #24]
8000964: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8000968: 61a3 str r3, [r4, #24]
GPIOE->BSRR |= GPIO_BSRR_BS1;
800096a: 69ab ldr r3, [r5, #24]
800096c: f043 0302 orr.w r3, r3, #2
8000970: 61ab str r3, [r5, #24]
HAL_Delay(1000);
8000972: f000 fa37 bl 8000de4 <HAL_Delay>
GPIOB->BSRR |= GPIO_BSRR_BR0;
8000976: 69a3 ldr r3, [r4, #24]
8000978: f443 3380 orr.w r3, r3, #65536 @ 0x10000
800097c: 61a3 str r3, [r4, #24]
GPIOB->BSRR |= GPIO_BSRR_BR14;
800097e: 69a3 ldr r3, [r4, #24]
8000980: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
8000984: 61a3 str r3, [r4, #24]
GPIOE->BSRR |= GPIO_BSRR_BR1;
8000986: 69ab ldr r3, [r5, #24]
8000988: f443 3300 orr.w r3, r3, #131072 @ 0x20000
800098c: 61ab str r3, [r5, #24]
}
800098e: bd38 pop {r3, r4, r5, pc}
8000990: 58020400 .word 0x58020400
8000994: 58021000 .word 0x58021000
08000998 <HAL_MspInit>:
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000998: 4b07 ldr r3, [pc, #28] @ (80009b8 <HAL_MspInit+0x20>)
{
800099a: b082 sub sp, #8
__HAL_RCC_SYSCFG_CLK_ENABLE();
800099c: f8d3 20f4 ldr.w r2, [r3, #244] @ 0xf4
80009a0: f042 0202 orr.w r2, r2, #2
80009a4: f8c3 20f4 str.w r2, [r3, #244] @ 0xf4
80009a8: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4
80009ac: f003 0302 and.w r3, r3, #2
80009b0: 9301 str r3, [sp, #4]
80009b2: 9b01 ldr r3, [sp, #4]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
80009b4: b002 add sp, #8
80009b6: 4770 bx lr
80009b8: 58024400 .word 0x58024400
080009bc <NMI_Handler>:
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
80009bc: e7fe b.n 80009bc <NMI_Handler>
80009be: bf00 nop
080009c0 <HardFault_Handler>:
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
80009c0: e7fe b.n 80009c0 <HardFault_Handler>
80009c2: bf00 nop
080009c4 <MemManage_Handler>:
void MemManage_Handler(void)
{
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
80009c4: e7fe b.n 80009c4 <MemManage_Handler>
80009c6: bf00 nop
080009c8 <BusFault_Handler>:
void BusFault_Handler(void)
{
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
80009c8: e7fe b.n 80009c8 <BusFault_Handler>
80009ca: bf00 nop
080009cc <UsageFault_Handler>:
void UsageFault_Handler(void)
{
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
80009cc: e7fe b.n 80009cc <UsageFault_Handler>
80009ce: bf00 nop
080009d0 <SVC_Handler>:
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
80009d0: 4770 bx lr
80009d2: bf00 nop
080009d4 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
80009d4: 4770 bx lr
80009d6: bf00 nop
080009d8 <PendSV_Handler>:
}
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
80009d8: 4770 bx lr
80009da: bf00 nop
080009dc <SysTick_Handler>:
void SysTick_Handler(void)
{
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
80009dc: f000 b9f0 b.w 8000dc0 <HAL_IncTick>
080009e0 <USART3_IRQHandler>:
void USART3_IRQHandler(void)
{
/* USER CODE BEGIN USART3_IRQn 0 */
/* USER CODE END USART3_IRQn 0 */
HAL_UART_IRQHandler(&huart3);
80009e0: 4801 ldr r0, [pc, #4] @ (80009e8 <USART3_IRQHandler+0x8>)
80009e2: f003 bfef b.w 80049c4 <HAL_UART_IRQHandler>
80009e6: bf00 nop
80009e8: 240000e0 .word 0x240000e0
080009ec <TIM6_DAC_IRQHandler>:
void TIM6_DAC_IRQHandler(void)
{
/* USER CODE BEGIN TIM6_DAC_IRQn 0 */
/* USER CODE END TIM6_DAC_IRQn 0 */
HAL_TIM_IRQHandler(&htim6);
80009ec: 4801 ldr r0, [pc, #4] @ (80009f4 <TIM6_DAC_IRQHandler+0x8>)
80009ee: f003 bed1 b.w 8004794 <HAL_TIM_IRQHandler>
80009f2: bf00 nop
80009f4: 24000090 .word 0x24000090
080009f8 <ADC3_IRQHandler>:
void ADC3_IRQHandler(void)
{
/* USER CODE BEGIN ADC3_IRQn 0 */
/* USER CODE END ADC3_IRQn 0 */
HAL_ADC_IRQHandler(&hadc3);
80009f8: 4801 ldr r0, [pc, #4] @ (8000a00 <ADC3_IRQHandler+0x8>)
80009fa: f000 ba11 b.w 8000e20 <HAL_ADC_IRQHandler>
80009fe: bf00 nop
8000a00: 2400002c .word 0x2400002c
08000a04 <SystemInit>:
__IO uint32_t tmpreg;
#endif /* DATA_IN_D2_SRAM */
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
8000a04: 4930 ldr r1, [pc, #192] @ (8000ac8 <SystemInit+0xc4>)
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Increasing the CPU frequency */
if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
8000a06: 4a31 ldr r2, [pc, #196] @ (8000acc <SystemInit+0xc8>)
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
8000a08: f8d1 3088 ldr.w r3, [r1, #136] @ 0x88
8000a0c: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
{
8000a10: b410 push {r4}
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
8000a12: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
8000a16: 6813 ldr r3, [r2, #0]
8000a18: f003 030f and.w r3, r3, #15
8000a1c: 2b06 cmp r3, #6
8000a1e: d805 bhi.n 8000a2c <SystemInit+0x28>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
8000a20: 6813 ldr r3, [r2, #0]
8000a22: f023 030f bic.w r3, r3, #15
8000a26: f043 0307 orr.w r3, r3, #7
8000a2a: 6013 str r3, [r2, #0]
}
/* Set HSION bit */
RCC->CR |= RCC_CR_HSION;
8000a2c: 4b28 ldr r3, [pc, #160] @ (8000ad0 <SystemInit+0xcc>)
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
8000a2e: 2400 movs r4, #0
/* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
RCC->CR &= 0xEAF6ED7FU;
8000a30: 4a28 ldr r2, [pc, #160] @ (8000ad4 <SystemInit+0xd0>)
RCC->CR |= RCC_CR_HSION;
8000a32: 6819 ldr r1, [r3, #0]
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
8000a34: 4825 ldr r0, [pc, #148] @ (8000acc <SystemInit+0xc8>)
RCC->CR |= RCC_CR_HSION;
8000a36: f041 0101 orr.w r1, r1, #1
8000a3a: 6019 str r1, [r3, #0]
RCC->CFGR = 0x00000000;
8000a3c: 611c str r4, [r3, #16]
RCC->CR &= 0xEAF6ED7FU;
8000a3e: 6819 ldr r1, [r3, #0]
8000a40: 400a ands r2, r1
8000a42: 601a str r2, [r3, #0]
if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
8000a44: 6803 ldr r3, [r0, #0]
8000a46: 0719 lsls r1, r3, #28
8000a48: d505 bpl.n 8000a56 <SystemInit+0x52>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
8000a4a: 6803 ldr r3, [r0, #0]
8000a4c: f023 030f bic.w r3, r3, #15
8000a50: f043 0307 orr.w r3, r3, #7
8000a54: 6003 str r3, [r0, #0]
}
#if defined(D3_SRAM_BASE)
/* Reset D1CFGR register */
RCC->D1CFGR = 0x00000000;
8000a56: 4b1e ldr r3, [pc, #120] @ (8000ad0 <SystemInit+0xcc>)
8000a58: 2200 movs r2, #0
RCC->PLLCKSELR = 0x02020200;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x01FF0000;
/* Reset PLL1DIVR register */
RCC->PLL1DIVR = 0x01010280;
8000a5a: 491f ldr r1, [pc, #124] @ (8000ad8 <SystemInit+0xd4>)
RCC->PLLCFGR = 0x01FF0000;
8000a5c: 481f ldr r0, [pc, #124] @ (8000adc <SystemInit+0xd8>)
RCC->PLLCKSELR = 0x02020200;
8000a5e: 4c20 ldr r4, [pc, #128] @ (8000ae0 <SystemInit+0xdc>)
RCC->D1CFGR = 0x00000000;
8000a60: 619a str r2, [r3, #24]
RCC->D2CFGR = 0x00000000;
8000a62: 61da str r2, [r3, #28]
RCC->D3CFGR = 0x00000000;
8000a64: 621a str r2, [r3, #32]
RCC->PLLCKSELR = 0x02020200;
8000a66: 629c str r4, [r3, #40] @ 0x28
RCC->PLLCFGR = 0x01FF0000;
8000a68: 62d8 str r0, [r3, #44] @ 0x2c
RCC->PLL1DIVR = 0x01010280;
8000a6a: 6319 str r1, [r3, #48] @ 0x30
/* Reset PLL1FRACR register */
RCC->PLL1FRACR = 0x00000000;
8000a6c: 635a str r2, [r3, #52] @ 0x34
/* Reset PLL2DIVR register */
RCC->PLL2DIVR = 0x01010280;
8000a6e: 6399 str r1, [r3, #56] @ 0x38
/* Reset PLL2FRACR register */
RCC->PLL2FRACR = 0x00000000;
8000a70: 63da str r2, [r3, #60] @ 0x3c
/* Reset PLL3DIVR register */
RCC->PLL3DIVR = 0x01010280;
8000a72: 6419 str r1, [r3, #64] @ 0x40
/* Reset PLL3FRACR register */
RCC->PLL3FRACR = 0x00000000;
8000a74: 645a str r2, [r3, #68] @ 0x44
/* Reset HSEBYP bit */
RCC->CR &= 0xFFFBFFFFU;
8000a76: 6819 ldr r1, [r3, #0]
/* Disable all interrupts */
RCC->CIER = 0x00000000;
#if (STM32H7_DEV_ID == 0x450UL)
/* dual core CM7 or single core line */
if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
8000a78: 481a ldr r0, [pc, #104] @ (8000ae4 <SystemInit+0xe0>)
RCC->CR &= 0xFFFBFFFFU;
8000a7a: f421 2180 bic.w r1, r1, #262144 @ 0x40000
8000a7e: 6019 str r1, [r3, #0]
RCC->CIER = 0x00000000;
8000a80: 661a str r2, [r3, #96] @ 0x60
if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
8000a82: 6803 ldr r3, [r0, #0]
8000a84: f36f 030f bfc r3, #0, #16
8000a88: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8000a8c: d203 bcs.n 8000a96 <SystemInit+0x92>
{
/* if stm32h7 revY*/
/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
*((__IO uint32_t*)0x51008108) = 0x000000001U;
8000a8e: 4b16 ldr r3, [pc, #88] @ (8000ae8 <SystemInit+0xe4>)
8000a90: 2201 movs r2, #1
8000a92: f8c3 2108 str.w r2, [r3, #264] @ 0x108
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */
#endif /* USER_VECT_TAB_ADDRESS */
#else
if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)
8000a96: 4b0e ldr r3, [pc, #56] @ (8000ad0 <SystemInit+0xcc>)
8000a98: f8d3 20d4 ldr.w r2, [r3, #212] @ 0xd4
8000a9c: 04d2 lsls r2, r2, #19
8000a9e: d40f bmi.n 8000ac0 <SystemInit+0xbc>
{
/* Enable the FMC interface clock */
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
8000aa0: f8d3 20d4 ldr.w r2, [r3, #212] @ 0xd4
/*
* Disable the FMC bank1 (enabled after reset).
* This, prevents CPU speculation access on this bank which blocks the use of FMC during
* 24us. During this time the others FMC master (such as LTDC) cannot use it!
*/
FMC_Bank1_R->BTCR[0] = 0x000030D2;
8000aa4: f243 00d2 movw r0, #12498 @ 0x30d2
8000aa8: 4910 ldr r1, [pc, #64] @ (8000aec <SystemInit+0xe8>)
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
8000aaa: f442 5280 orr.w r2, r2, #4096 @ 0x1000
8000aae: f8c3 20d4 str.w r2, [r3, #212] @ 0xd4
FMC_Bank1_R->BTCR[0] = 0x000030D2;
8000ab2: 6008 str r0, [r1, #0]
/* Disable the FMC interface clock */
CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
8000ab4: f8d3 20d4 ldr.w r2, [r3, #212] @ 0xd4
8000ab8: f422 5280 bic.w r2, r2, #4096 @ 0x1000
8000abc: f8c3 20d4 str.w r2, [r3, #212] @ 0xd4
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
#endif /* USER_VECT_TAB_ADDRESS */
#endif /*DUAL_CORE && CORE_CM4*/
}
8000ac0: f85d 4b04 ldr.w r4, [sp], #4
8000ac4: 4770 bx lr
8000ac6: bf00 nop
8000ac8: e000ed00 .word 0xe000ed00
8000acc: 52002000 .word 0x52002000
8000ad0: 58024400 .word 0x58024400
8000ad4: eaf6ed7f .word 0xeaf6ed7f
8000ad8: 01010280 .word 0x01010280
8000adc: 01ff0000 .word 0x01ff0000
8000ae0: 02020200 .word 0x02020200
8000ae4: 5c001000 .word 0x5c001000
8000ae8: 51008000 .word 0x51008000
8000aec: 52004000 .word 0x52004000
08000af0 <ExitRun0Mode>:
#if defined(SMPS)
/* Exit Run* mode by disabling SMPS and enabling LDO */
PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN;
#else
/* Enable LDO mode */
PWR->CR3 |= PWR_CR3_LDOEN;
8000af0: 4a04 ldr r2, [pc, #16] @ (8000b04 <ExitRun0Mode+0x14>)
8000af2: 68d3 ldr r3, [r2, #12]
8000af4: f043 0302 orr.w r3, r3, #2
8000af8: 60d3 str r3, [r2, #12]
#endif /* SMPS */
/* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
8000afa: 6853 ldr r3, [r2, #4]
8000afc: 049b lsls r3, r3, #18
8000afe: d5fc bpl.n 8000afa <ExitRun0Mode+0xa>
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{}
#else
/* No system power supply configuration is selected at exit Run* mode */
#endif /* USE_PWR_LDO_SUPPLY */
}
8000b00: 4770 bx lr
8000b02: bf00 nop
8000b04: 58024800 .word 0x58024800
08000b08 <MX_TIM6_Init>:
TIM_HandleTypeDef htim6;
/* TIM6 init function */
void MX_TIM6_Init(void)
{
8000b08: b500 push {lr}
TIM_MasterConfigTypeDef sMasterConfig = {0};
/* USER CODE BEGIN TIM6_Init 1 */
/* USER CODE END TIM6_Init 1 */
htim6.Instance = TIM6;
8000b0a: 4812 ldr r0, [pc, #72] @ (8000b54 <MX_TIM6_Init+0x4c>)
{
8000b0c: b085 sub sp, #20
TIM_MasterConfigTypeDef sMasterConfig = {0};
8000b0e: 2300 movs r3, #0
htim6.Instance = TIM6;
8000b10: 4911 ldr r1, [pc, #68] @ (8000b58 <MX_TIM6_Init+0x50>)
htim6.Init.Prescaler = 0;
htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
htim6.Init.Period = 65535;
8000b12: f64f 72ff movw r2, #65535 @ 0xffff
htim6.Instance = TIM6;
8000b16: 6001 str r1, [r0, #0]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8000b18: 9301 str r3, [sp, #4]
htim6.Init.Period = 65535;
8000b1a: 60c2 str r2, [r0, #12]
htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000b1c: 6183 str r3, [r0, #24]
htim6.Init.Prescaler = 0;
8000b1e: e9c0 3301 strd r3, r3, [r0, #4]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8000b22: e9cd 3302 strd r3, r3, [sp, #8]
if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
8000b26: f003 fd85 bl 8004634 <HAL_TIM_Base_Init>
8000b2a: b950 cbnz r0, 8000b42 <MX_TIM6_Init+0x3a>
{
Error_Handler();
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000b2c: 2300 movs r3, #0
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
8000b2e: a901 add r1, sp, #4
8000b30: 4808 ldr r0, [pc, #32] @ (8000b54 <MX_TIM6_Init+0x4c>)
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000b32: 9301 str r3, [sp, #4]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000b34: 9303 str r3, [sp, #12]
if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
8000b36: f003 fed7 bl 80048e8 <HAL_TIMEx_MasterConfigSynchronization>
8000b3a: b928 cbnz r0, 8000b48 <MX_TIM6_Init+0x40>
}
/* USER CODE BEGIN TIM6_Init 2 */
/* USER CODE END TIM6_Init 2 */
}
8000b3c: b005 add sp, #20
8000b3e: f85d fb04 ldr.w pc, [sp], #4
Error_Handler();
8000b42: f7ff feff bl 8000944 <Error_Handler>
8000b46: e7f1 b.n 8000b2c <MX_TIM6_Init+0x24>
Error_Handler();
8000b48: f7ff fefc bl 8000944 <Error_Handler>
}
8000b4c: b005 add sp, #20
8000b4e: f85d fb04 ldr.w pc, [sp], #4
8000b52: bf00 nop
8000b54: 24000090 .word 0x24000090
8000b58: 40001000 .word 0x40001000
08000b5c <HAL_TIM_Base_MspInit>:
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
{
if(tim_baseHandle->Instance==TIM6)
8000b5c: 4b0f ldr r3, [pc, #60] @ (8000b9c <HAL_TIM_Base_MspInit+0x40>)
8000b5e: 6802 ldr r2, [r0, #0]
8000b60: 429a cmp r2, r3
8000b62: d000 beq.n 8000b66 <HAL_TIM_Base_MspInit+0xa>
8000b64: 4770 bx lr
{
/* USER CODE BEGIN TIM6_MspInit 0 */
/* USER CODE END TIM6_MspInit 0 */
/* TIM6 clock enable */
__HAL_RCC_TIM6_CLK_ENABLE();
8000b66: 4b0e ldr r3, [pc, #56] @ (8000ba0 <HAL_TIM_Base_MspInit+0x44>)
/* TIM6 interrupt Init */
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0);
8000b68: 2200 movs r2, #0
8000b6a: 2036 movs r0, #54 @ 0x36
8000b6c: 4611 mov r1, r2
{
8000b6e: b510 push {r4, lr}
__HAL_RCC_TIM6_CLK_ENABLE();
8000b70: f8d3 40e8 ldr.w r4, [r3, #232] @ 0xe8
{
8000b74: b082 sub sp, #8
__HAL_RCC_TIM6_CLK_ENABLE();
8000b76: f044 0410 orr.w r4, r4, #16
8000b7a: f8c3 40e8 str.w r4, [r3, #232] @ 0xe8
8000b7e: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8
8000b82: f003 0310 and.w r3, r3, #16
8000b86: 9301 str r3, [sp, #4]
8000b88: 9b01 ldr r3, [sp, #4]
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0);
8000b8a: f000 fe6b bl 8001864 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
8000b8e: 2036 movs r0, #54 @ 0x36
/* USER CODE BEGIN TIM6_MspInit 1 */
/* USER CODE END TIM6_MspInit 1 */
}
}
8000b90: b002 add sp, #8
8000b92: e8bd 4010 ldmia.w sp!, {r4, lr}
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
8000b96: f000 bea1 b.w 80018dc <HAL_NVIC_EnableIRQ>
8000b9a: bf00 nop
8000b9c: 40001000 .word 0x40001000
8000ba0: 58024400 .word 0x58024400
08000ba4 <MX_USART3_UART_Init>:
UART_HandleTypeDef huart3;
/* USART3 init function */
void MX_USART3_UART_Init(void)
{
8000ba4: b510 push {r4, lr}
/* USER CODE END USART3_Init 0 */
/* USER CODE BEGIN USART3_Init 1 */
/* USER CODE END USART3_Init 1 */
huart3.Instance = USART3;
8000ba6: 481f ldr r0, [pc, #124] @ (8000c24 <MX_USART3_UART_Init+0x80>)
huart3.Init.BaudRate = 115200;
huart3.Init.WordLength = UART_WORDLENGTH_8B;
8000ba8: 2300 movs r3, #0
huart3.Instance = USART3;
8000baa: 4c1f ldr r4, [pc, #124] @ (8000c28 <MX_USART3_UART_Init+0x84>)
huart3.Init.BaudRate = 115200;
8000bac: f44f 31e1 mov.w r1, #115200 @ 0x1c200
huart3.Init.StopBits = UART_STOPBITS_1;
huart3.Init.Parity = UART_PARITY_NONE;
huart3.Init.Mode = UART_MODE_TX_RX;
8000bb0: 220c movs r2, #12
huart3.Init.WordLength = UART_WORDLENGTH_8B;
8000bb2: 6083 str r3, [r0, #8]
huart3.Init.BaudRate = 115200;
8000bb4: e9c0 4100 strd r4, r1, [r0]
huart3.Init.Parity = UART_PARITY_NONE;
8000bb8: e9c0 3303 strd r3, r3, [r0, #12]
huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8000bbc: e9c0 2305 strd r2, r3, [r0, #20]
huart3.Init.OverSampling = UART_OVERSAMPLING_16;
huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
8000bc0: e9c0 3307 strd r3, r3, [r0, #28]
huart3.Init.ClockPrescaler = UART_PRESCALER_DIV1;
8000bc4: e9c0 3309 strd r3, r3, [r0, #36] @ 0x24
huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
if (HAL_UART_Init(&huart3) != HAL_OK)
8000bc8: f004 fc12 bl 80053f0 <HAL_UART_Init>
8000bcc: b970 cbnz r0, 8000bec <MX_USART3_UART_Init+0x48>
{
Error_Handler();
}
if (HAL_UARTEx_SetTxFifoThreshold(&huart3, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
8000bce: 2100 movs r1, #0
8000bd0: 4814 ldr r0, [pc, #80] @ (8000c24 <MX_USART3_UART_Init+0x80>)
8000bd2: f004 fc65 bl 80054a0 <HAL_UARTEx_SetTxFifoThreshold>
8000bd6: b988 cbnz r0, 8000bfc <MX_USART3_UART_Init+0x58>
{
Error_Handler();
}
if (HAL_UARTEx_SetRxFifoThreshold(&huart3, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
8000bd8: 2100 movs r1, #0
8000bda: 4812 ldr r0, [pc, #72] @ (8000c24 <MX_USART3_UART_Init+0x80>)
8000bdc: f004 fca2 bl 8005524 <HAL_UARTEx_SetRxFifoThreshold>
8000be0: b9a0 cbnz r0, 8000c0c <MX_USART3_UART_Init+0x68>
{
Error_Handler();
}
if (HAL_UARTEx_DisableFifoMode(&huart3) != HAL_OK)
8000be2: 4810 ldr r0, [pc, #64] @ (8000c24 <MX_USART3_UART_Init+0x80>)
8000be4: f004 fc3e bl 8005464 <HAL_UARTEx_DisableFifoMode>
8000be8: b9b8 cbnz r0, 8000c1a <MX_USART3_UART_Init+0x76>
}
/* USER CODE BEGIN USART3_Init 2 */
/* USER CODE END USART3_Init 2 */
}
8000bea: bd10 pop {r4, pc}
Error_Handler();
8000bec: f7ff feaa bl 8000944 <Error_Handler>
if (HAL_UARTEx_SetTxFifoThreshold(&huart3, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
8000bf0: 2100 movs r1, #0
8000bf2: 480c ldr r0, [pc, #48] @ (8000c24 <MX_USART3_UART_Init+0x80>)
8000bf4: f004 fc54 bl 80054a0 <HAL_UARTEx_SetTxFifoThreshold>
8000bf8: 2800 cmp r0, #0
8000bfa: d0ed beq.n 8000bd8 <MX_USART3_UART_Init+0x34>
Error_Handler();
8000bfc: f7ff fea2 bl 8000944 <Error_Handler>
if (HAL_UARTEx_SetRxFifoThreshold(&huart3, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
8000c00: 2100 movs r1, #0
8000c02: 4808 ldr r0, [pc, #32] @ (8000c24 <MX_USART3_UART_Init+0x80>)
8000c04: f004 fc8e bl 8005524 <HAL_UARTEx_SetRxFifoThreshold>
8000c08: 2800 cmp r0, #0
8000c0a: d0ea beq.n 8000be2 <MX_USART3_UART_Init+0x3e>
Error_Handler();
8000c0c: f7ff fe9a bl 8000944 <Error_Handler>
if (HAL_UARTEx_DisableFifoMode(&huart3) != HAL_OK)
8000c10: 4804 ldr r0, [pc, #16] @ (8000c24 <MX_USART3_UART_Init+0x80>)
8000c12: f004 fc27 bl 8005464 <HAL_UARTEx_DisableFifoMode>
8000c16: 2800 cmp r0, #0
8000c18: d0e7 beq.n 8000bea <MX_USART3_UART_Init+0x46>
}
8000c1a: e8bd 4010 ldmia.w sp!, {r4, lr}
Error_Handler();
8000c1e: f7ff be91 b.w 8000944 <Error_Handler>
8000c22: bf00 nop
8000c24: 240000e0 .word 0x240000e0
8000c28: 40004800 .word 0x40004800
8000c2c: 00000000 .word 0x00000000
08000c30 <HAL_UART_MspInit>:
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(uartHandle->Instance==USART3)
8000c30: 4b1f ldr r3, [pc, #124] @ (8000cb0 <HAL_UART_MspInit+0x80>)
8000c32: 6802 ldr r2, [r0, #0]
{
8000c34: b510 push {r4, lr}
if(uartHandle->Instance==USART3)
8000c36: 429a cmp r2, r3
{
8000c38: b088 sub sp, #32
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000c3a: f04f 0400 mov.w r4, #0
8000c3e: e9cd 4402 strd r4, r4, [sp, #8]
8000c42: e9cd 4404 strd r4, r4, [sp, #16]
8000c46: 9406 str r4, [sp, #24]
if(uartHandle->Instance==USART3)
8000c48: d001 beq.n 8000c4e <HAL_UART_MspInit+0x1e>
HAL_NVIC_EnableIRQ(USART3_IRQn);
/* USER CODE BEGIN USART3_MspInit 1 */
/* USER CODE END USART3_MspInit 1 */
}
}
8000c4a: b008 add sp, #32
8000c4c: bd10 pop {r4, pc}
__HAL_RCC_USART3_CLK_ENABLE();
8000c4e: 4b19 ldr r3, [pc, #100] @ (8000cb4 <HAL_UART_MspInit+0x84>)
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8000c50: a902 add r1, sp, #8
8000c52: 4819 ldr r0, [pc, #100] @ (8000cb8 <HAL_UART_MspInit+0x88>)
__HAL_RCC_USART3_CLK_ENABLE();
8000c54: f8d3 20e8 ldr.w r2, [r3, #232] @ 0xe8
8000c58: f442 2280 orr.w r2, r2, #262144 @ 0x40000
8000c5c: f8c3 20e8 str.w r2, [r3, #232] @ 0xe8
8000c60: f8d3 20e8 ldr.w r2, [r3, #232] @ 0xe8
8000c64: f402 2280 and.w r2, r2, #262144 @ 0x40000
8000c68: 9200 str r2, [sp, #0]
8000c6a: 9a00 ldr r2, [sp, #0]
__HAL_RCC_GPIOD_CLK_ENABLE();
8000c6c: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
8000c70: f042 0208 orr.w r2, r2, #8
8000c74: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0
8000c78: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0
8000c7c: f003 0308 and.w r3, r3, #8
GPIO_InitStruct.Pin = STLINK_RX_Pin|STLINK_TX_Pin;
8000c80: ed9f 7b09 vldr d7, [pc, #36] @ 8000ca8 <HAL_UART_MspInit+0x78>
__HAL_RCC_GPIOD_CLK_ENABLE();
8000c84: 9301 str r3, [sp, #4]
GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
8000c86: 2307 movs r3, #7
__HAL_RCC_GPIOD_CLK_ENABLE();
8000c88: 9a01 ldr r2, [sp, #4]
GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
8000c8a: 9306 str r3, [sp, #24]
GPIO_InitStruct.Pin = STLINK_RX_Pin|STLINK_TX_Pin;
8000c8c: ed8d 7b02 vstr d7, [sp, #8]
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8000c90: f001 f916 bl 8001ec0 <HAL_GPIO_Init>
HAL_NVIC_SetPriority(USART3_IRQn, 0, 0);
8000c94: 4622 mov r2, r4
8000c96: 4621 mov r1, r4
8000c98: 2027 movs r0, #39 @ 0x27
8000c9a: f000 fde3 bl 8001864 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USART3_IRQn);
8000c9e: 2027 movs r0, #39 @ 0x27
8000ca0: f000 fe1c bl 80018dc <HAL_NVIC_EnableIRQ>
}
8000ca4: b008 add sp, #32
8000ca6: bd10 pop {r4, pc}
8000ca8: 00000300 .word 0x00000300
8000cac: 00000002 .word 0x00000002
8000cb0: 40004800 .word 0x40004800
8000cb4: 58024400 .word 0x58024400
8000cb8: 58020c00 .word 0x58020c00
08000cbc <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
8000cbc: f8df d038 ldr.w sp, [pc, #56] @ 8000cf8 <LoopFillZerobss+0xe>
/* Call the ExitRun0Mode function to configure the power supply */
bl ExitRun0Mode
8000cc0: f7ff ff16 bl 8000af0 <ExitRun0Mode>
/* Call the clock system initialization function.*/
bl SystemInit
8000cc4: f7ff fe9e bl 8000a04 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000cc8: 480c ldr r0, [pc, #48] @ (8000cfc <LoopFillZerobss+0x12>)
ldr r1, =_edata
8000cca: 490d ldr r1, [pc, #52] @ (8000d00 <LoopFillZerobss+0x16>)
ldr r2, =_sidata
8000ccc: 4a0d ldr r2, [pc, #52] @ (8000d04 <LoopFillZerobss+0x1a>)
movs r3, #0
8000cce: 2300 movs r3, #0
b LoopCopyDataInit
8000cd0: e002 b.n 8000cd8 <LoopCopyDataInit>
08000cd2 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000cd2: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000cd4: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8000cd6: 3304 adds r3, #4
08000cd8 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000cd8: 18c4 adds r4, r0, r3
cmp r4, r1
8000cda: 428c cmp r4, r1
bcc CopyDataInit
8000cdc: d3f9 bcc.n 8000cd2 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8000cde: 4a0a ldr r2, [pc, #40] @ (8000d08 <LoopFillZerobss+0x1e>)
ldr r4, =_ebss
8000ce0: 4c0a ldr r4, [pc, #40] @ (8000d0c <LoopFillZerobss+0x22>)
movs r3, #0
8000ce2: 2300 movs r3, #0
b LoopFillZerobss
8000ce4: e001 b.n 8000cea <LoopFillZerobss>
08000ce6 <FillZerobss>:
FillZerobss:
str r3, [r2]
8000ce6: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000ce8: 3204 adds r2, #4
08000cea <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8000cea: 42a2 cmp r2, r4
bcc FillZerobss
8000cec: d3fb bcc.n 8000ce6 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8000cee: f004 fc63 bl 80055b8 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8000cf2: f7ff fdfd bl 80008f0 <main>
bx lr
8000cf6: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
8000cf8: 24080000 .word 0x24080000
ldr r0, =_sdata
8000cfc: 24000000 .word 0x24000000
ldr r1, =_edata
8000d00: 24000010 .word 0x24000010
ldr r2, =_sidata
8000d04: 08005660 .word 0x08005660
ldr r2, =_sbss
8000d08: 24000010 .word 0x24000010
ldr r4, =_ebss
8000d0c: 24000178 .word 0x24000178
08000d10 <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000d10: e7fe b.n 8000d10 <ADC_IRQHandler>
...
08000d14 <HAL_InitTick>:
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/
if((uint32_t)uwTickFreq == 0UL)
8000d14: 4b0f ldr r3, [pc, #60] @ (8000d54 <HAL_InitTick+0x40>)
8000d16: 781b ldrb r3, [r3, #0]
8000d18: b90b cbnz r3, 8000d1e <HAL_InitTick+0xa>
{
return HAL_ERROR;
8000d1a: 2001 movs r0, #1
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
}
8000d1c: 4770 bx lr
{
8000d1e: b510 push {r4, lr}
8000d20: 4604 mov r4, r0
if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
8000d22: f44f 707a mov.w r0, #1000 @ 0x3e8
8000d26: 4a0c ldr r2, [pc, #48] @ (8000d58 <HAL_InitTick+0x44>)
8000d28: fbb0 f3f3 udiv r3, r0, r3
8000d2c: 6810 ldr r0, [r2, #0]
8000d2e: fbb0 f0f3 udiv r0, r0, r3
8000d32: f000 fde1 bl 80018f8 <HAL_SYSTICK_Config>
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000d36: 2c0f cmp r4, #15
8000d38: d800 bhi.n 8000d3c <HAL_InitTick+0x28>
8000d3a: b108 cbz r0, 8000d40 <HAL_InitTick+0x2c>
return HAL_ERROR;
8000d3c: 2001 movs r0, #1
}
8000d3e: bd10 pop {r4, pc}
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000d40: 2200 movs r2, #0
8000d42: 4621 mov r1, r4
8000d44: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8000d48: f000 fd8c bl 8001864 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000d4c: 4b03 ldr r3, [pc, #12] @ (8000d5c <HAL_InitTick+0x48>)
8000d4e: 2000 movs r0, #0
8000d50: 601c str r4, [r3, #0]
}
8000d52: bd10 pop {r4, pc}
8000d54: 24000008 .word 0x24000008
8000d58: 24000004 .word 0x24000004
8000d5c: 2400000c .word 0x2400000c
08000d60 <HAL_Init>:
{
8000d60: b510 push {r4, lr}
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000d62: 2003 movs r0, #3
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
8000d64: 4c12 ldr r4, [pc, #72] @ (8000db0 <HAL_Init+0x50>)
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000d66: f000 fd6b bl 8001840 <HAL_NVIC_SetPriorityGrouping>
common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
8000d6a: f001 fe37 bl 80029dc <HAL_RCC_GetSysClockFreq>
8000d6e: 4b11 ldr r3, [pc, #68] @ (8000db4 <HAL_Init+0x54>)
8000d70: 4911 ldr r1, [pc, #68] @ (8000db8 <HAL_Init+0x58>)
8000d72: 699a ldr r2, [r3, #24]
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
8000d74: 699b ldr r3, [r3, #24]
common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
8000d76: f3c2 2203 ubfx r2, r2, #8, #4
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
8000d7a: f003 030f and.w r3, r3, #15
common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
8000d7e: 5c8a ldrb r2, [r1, r2]
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
8000d80: 5ccb ldrb r3, [r1, r3]
common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
8000d82: f002 021f and.w r2, r2, #31
SystemCoreClock = common_system_clock;
8000d86: 490d ldr r1, [pc, #52] @ (8000dbc <HAL_Init+0x5c>)
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
8000d88: f003 031f and.w r3, r3, #31
common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
8000d8c: 40d0 lsrs r0, r2
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
8000d8e: fa20 f303 lsr.w r3, r0, r3
SystemCoreClock = common_system_clock;
8000d92: 6008 str r0, [r1, #0]
if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
8000d94: 2000 movs r0, #0
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
8000d96: 6023 str r3, [r4, #0]
if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
8000d98: f7ff ffbc bl 8000d14 <HAL_InitTick>
8000d9c: b110 cbz r0, 8000da4 <HAL_Init+0x44>
return HAL_ERROR;
8000d9e: 2401 movs r4, #1
}
8000da0: 4620 mov r0, r4
8000da2: bd10 pop {r4, pc}
8000da4: 4604 mov r4, r0
HAL_MspInit();
8000da6: f7ff fdf7 bl 8000998 <HAL_MspInit>
}
8000daa: 4620 mov r0, r4
8000dac: bd10 pop {r4, pc}
8000dae: bf00 nop
8000db0: 24000000 .word 0x24000000
8000db4: 58024400 .word 0x58024400
8000db8: 08005618 .word 0x08005618
8000dbc: 24000004 .word 0x24000004
08000dc0 <HAL_IncTick>:
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
uwTick += (uint32_t)uwTickFreq;
8000dc0: 4a03 ldr r2, [pc, #12] @ (8000dd0 <HAL_IncTick+0x10>)
8000dc2: 4b04 ldr r3, [pc, #16] @ (8000dd4 <HAL_IncTick+0x14>)
8000dc4: 6811 ldr r1, [r2, #0]
8000dc6: 781b ldrb r3, [r3, #0]
8000dc8: 440b add r3, r1
8000dca: 6013 str r3, [r2, #0]
}
8000dcc: 4770 bx lr
8000dce: bf00 nop
8000dd0: 24000174 .word 0x24000174
8000dd4: 24000008 .word 0x24000008
08000dd8 <HAL_GetTick>:
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
return uwTick;
8000dd8: 4b01 ldr r3, [pc, #4] @ (8000de0 <HAL_GetTick+0x8>)
8000dda: 6818 ldr r0, [r3, #0]
}
8000ddc: 4770 bx lr
8000dde: bf00 nop
8000de0: 24000174 .word 0x24000174
08000de4 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8000de4: b538 push {r3, r4, r5, lr}
8000de6: 4604 mov r4, r0
uint32_t tickstart = HAL_GetTick();
8000de8: f7ff fff6 bl 8000dd8 <HAL_GetTick>
8000dec: 4605 mov r5, r0
uint32_t wait = Delay;
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
8000dee: 1c63 adds r3, r4, #1
8000df0: d002 beq.n 8000df8 <HAL_Delay+0x14>
{
wait += (uint32_t)(uwTickFreq);
8000df2: 4b04 ldr r3, [pc, #16] @ (8000e04 <HAL_Delay+0x20>)
8000df4: 781b ldrb r3, [r3, #0]
8000df6: 441c add r4, r3
}
while ((HAL_GetTick() - tickstart) < wait)
8000df8: f7ff ffee bl 8000dd8 <HAL_GetTick>
8000dfc: 1b40 subs r0, r0, r5
8000dfe: 42a0 cmp r0, r4
8000e00: d3fa bcc.n 8000df8 <HAL_Delay+0x14>
{
}
}
8000e02: bd38 pop {r3, r4, r5, pc}
8000e04: 24000008 .word 0x24000008
08000e08 <HAL_GetREVID>:
* @brief Returns the device revision identifier.
* @retval Device revision identifier
*/
uint32_t HAL_GetREVID(void)
{
return((DBGMCU->IDCODE) >> 16);
8000e08: 4b01 ldr r3, [pc, #4] @ (8000e10 <HAL_GetREVID+0x8>)
8000e0a: 6818 ldr r0, [r3, #0]
}
8000e0c: 0c00 lsrs r0, r0, #16
8000e0e: 4770 bx lr
8000e10: 5c001000 .word 0x5c001000
08000e14 <HAL_ADC_ConvCpltCallback>:
/**
* @brief Conversion complete callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
8000e14: 4770 bx lr
8000e16: bf00 nop
08000e18 <HAL_ADC_LevelOutOfWindowCallback>:
/**
* @brief Analog watchdog 1 callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
8000e18: 4770 bx lr
8000e1a: bf00 nop
08000e1c <HAL_ADC_ErrorCallback>:
* "HAL_ADC_Start_DMA()"
* (this function is also clearing overrun flag)
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
8000e1c: 4770 bx lr
8000e1e: bf00 nop
08000e20 <HAL_ADC_IRQHandler>:
{
8000e20: b5f8 push {r3, r4, r5, r6, r7, lr}
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
8000e22: 4a8e ldr r2, [pc, #568] @ (800105c <HAL_ADC_IRQHandler+0x23c>)
{
8000e24: 4604 mov r4, r0
uint32_t tmp_isr = hadc->Instance->ISR;
8000e26: 6803 ldr r3, [r0, #0]
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
8000e28: 4293 cmp r3, r2
uint32_t tmp_isr = hadc->Instance->ISR;
8000e2a: 681d ldr r5, [r3, #0]
uint32_t tmp_ier = hadc->Instance->IER;
8000e2c: 685e ldr r6, [r3, #4]
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
8000e2e: f000 8095 beq.w 8000f5c <HAL_ADC_IRQHandler+0x13c>
8000e32: f502 7280 add.w r2, r2, #256 @ 0x100
8000e36: 4293 cmp r3, r2
8000e38: f000 8090 beq.w 8000f5c <HAL_ADC_IRQHandler+0x13c>
8000e3c: 4a88 ldr r2, [pc, #544] @ (8001060 <HAL_ADC_IRQHandler+0x240>)
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
* @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
*/
__STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON)
{
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
8000e3e: 6897 ldr r7, [r2, #8]
if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
8000e40: 07a9 lsls r1, r5, #30
8000e42: f007 071f and.w r7, r7, #31
8000e46: d502 bpl.n 8000e4e <HAL_ADC_IRQHandler+0x2e>
8000e48: 07b2 lsls r2, r6, #30
8000e4a: f100 80aa bmi.w 8000fa2 <HAL_ADC_IRQHandler+0x182>
if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
8000e4e: 0769 lsls r1, r5, #29
8000e50: d579 bpl.n 8000f46 <HAL_ADC_IRQHandler+0x126>
8000e52: 0772 lsls r2, r6, #29
8000e54: d577 bpl.n 8000f46 <HAL_ADC_IRQHandler+0x126>
if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
8000e56: 6d62 ldr r2, [r4, #84] @ 0x54
8000e58: 06d2 lsls r2, r2, #27
8000e5a: d403 bmi.n 8000e64 <HAL_ADC_IRQHandler+0x44>
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
8000e5c: 6d62 ldr r2, [r4, #84] @ 0x54
8000e5e: f442 7200 orr.w r2, r2, #512 @ 0x200
8000e62: 6562 str r2, [r4, #84] @ 0x54
return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
8000e64: 68da ldr r2, [r3, #12]
8000e66: f412 6f40 tst.w r2, #3072 @ 0xc00
8000e6a: d11c bne.n 8000ea6 <HAL_ADC_IRQHandler+0x86>
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
8000e6c: 4a7d ldr r2, [pc, #500] @ (8001064 <HAL_ADC_IRQHandler+0x244>)
8000e6e: 4293 cmp r3, r2
8000e70: f000 80e7 beq.w 8001042 <HAL_ADC_IRQHandler+0x222>
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
8000e74: 68da ldr r2, [r3, #12]
if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
8000e76: 0491 lsls r1, r2, #18
8000e78: d415 bmi.n 8000ea6 <HAL_ADC_IRQHandler+0x86>
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
8000e7a: 681a ldr r2, [r3, #0]
8000e7c: 0712 lsls r2, r2, #28
8000e7e: d512 bpl.n 8000ea6 <HAL_ADC_IRQHandler+0x86>
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group regular.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
8000e80: 689a ldr r2, [r3, #8]
8000e82: 0750 lsls r0, r2, #29
8000e84: f100 80f2 bmi.w 800106c <HAL_ADC_IRQHandler+0x24c>
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
8000e88: 685a ldr r2, [r3, #4]
8000e8a: f022 020c bic.w r2, r2, #12
8000e8e: 605a str r2, [r3, #4]
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
8000e90: 6d63 ldr r3, [r4, #84] @ 0x54
8000e92: f423 7380 bic.w r3, r3, #256 @ 0x100
8000e96: 6563 str r3, [r4, #84] @ 0x54
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
8000e98: 6d63 ldr r3, [r4, #84] @ 0x54
8000e9a: 04d9 lsls r1, r3, #19
8000e9c: d403 bmi.n 8000ea6 <HAL_ADC_IRQHandler+0x86>
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
8000e9e: 6d63 ldr r3, [r4, #84] @ 0x54
8000ea0: f043 0301 orr.w r3, r3, #1
8000ea4: 6563 str r3, [r4, #84] @ 0x54
HAL_ADC_ConvCpltCallback(hadc);
8000ea6: 4620 mov r0, r4
8000ea8: f7ff ffb4 bl 8000e14 <HAL_ADC_ConvCpltCallback>
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
8000eac: 6823 ldr r3, [r4, #0]
8000eae: 220c movs r2, #12
8000eb0: 601a str r2, [r3, #0]
if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
8000eb2: 06aa lsls r2, r5, #26
8000eb4: d54d bpl.n 8000f52 <HAL_ADC_IRQHandler+0x132>
8000eb6: 06b0 lsls r0, r6, #26
8000eb8: d54b bpl.n 8000f52 <HAL_ADC_IRQHandler+0x132>
if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
8000eba: 6d62 ldr r2, [r4, #84] @ 0x54
8000ebc: 06d0 lsls r0, r2, #27
8000ebe: d403 bmi.n 8000ec8 <HAL_ADC_IRQHandler+0xa8>
SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
8000ec0: 6d62 ldr r2, [r4, #84] @ 0x54
8000ec2: f442 5200 orr.w r2, r2, #8192 @ 0x2000
8000ec6: 6562 str r2, [r4, #84] @ 0x54
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
8000ec8: 4966 ldr r1, [pc, #408] @ (8001064 <HAL_ADC_IRQHandler+0x244>)
return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
8000eca: 6cda ldr r2, [r3, #76] @ 0x4c
8000ecc: 428b cmp r3, r1
return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
8000ece: 68d8 ldr r0, [r3, #12]
return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
8000ed0: f402 72c0 and.w r2, r2, #384 @ 0x180
8000ed4: d073 beq.n 8000fbe <HAL_ADC_IRQHandler+0x19e>
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
8000ed6: 68d9 ldr r1, [r3, #12]
if (tmp_adc_inj_is_trigger_source_sw_start != 0UL)
8000ed8: b9d2 cbnz r2, 8000f10 <HAL_ADC_IRQHandler+0xf0>
if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) ||
8000eda: 018a lsls r2, r1, #6
8000edc: f100 80a9 bmi.w 8001032 <HAL_ADC_IRQHandler+0x212>
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
8000ee0: 681a ldr r2, [r3, #0]
8000ee2: 0650 lsls r0, r2, #25
8000ee4: d514 bpl.n 8000f10 <HAL_ADC_IRQHandler+0xf0>
if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
8000ee6: 0289 lsls r1, r1, #10
8000ee8: d412 bmi.n 8000f10 <HAL_ADC_IRQHandler+0xf0>
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group injected.
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
8000eea: 689a ldr r2, [r3, #8]
8000eec: 0712 lsls r2, r2, #28
8000eee: f100 80c8 bmi.w 8001082 <HAL_ADC_IRQHandler+0x262>
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
8000ef2: 685a ldr r2, [r3, #4]
8000ef4: f022 0260 bic.w r2, r2, #96 @ 0x60
8000ef8: 605a str r2, [r3, #4]
CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
8000efa: 6d63 ldr r3, [r4, #84] @ 0x54
8000efc: f423 5380 bic.w r3, r3, #4096 @ 0x1000
8000f00: 6563 str r3, [r4, #84] @ 0x54
if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
8000f02: 6d63 ldr r3, [r4, #84] @ 0x54
8000f04: 05d8 lsls r0, r3, #23
8000f06: d403 bmi.n 8000f10 <HAL_ADC_IRQHandler+0xf0>
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
8000f08: 6d63 ldr r3, [r4, #84] @ 0x54
8000f0a: f043 0301 orr.w r3, r3, #1
8000f0e: 6563 str r3, [r4, #84] @ 0x54
HAL_ADCEx_InjectedConvCpltCallback(hadc);
8000f10: 4620 mov r0, r4
8000f12: f000 fc8b bl 800182c <HAL_ADCEx_InjectedConvCpltCallback>
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
8000f16: 6823 ldr r3, [r4, #0]
8000f18: 2260 movs r2, #96 @ 0x60
8000f1a: 601a str r2, [r3, #0]
if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
8000f1c: 0629 lsls r1, r5, #24
8000f1e: d501 bpl.n 8000f24 <HAL_ADC_IRQHandler+0x104>
8000f20: 0632 lsls r2, r6, #24
8000f22: d45f bmi.n 8000fe4 <HAL_ADC_IRQHandler+0x1c4>
if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
8000f24: 05e8 lsls r0, r5, #23
8000f26: d501 bpl.n 8000f2c <HAL_ADC_IRQHandler+0x10c>
8000f28: 05f1 lsls r1, r6, #23
8000f2a: d466 bmi.n 8000ffa <HAL_ADC_IRQHandler+0x1da>
if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
8000f2c: 05aa lsls r2, r5, #22
8000f2e: d501 bpl.n 8000f34 <HAL_ADC_IRQHandler+0x114>
8000f30: 05b0 lsls r0, r6, #22
8000f32: d44b bmi.n 8000fcc <HAL_ADC_IRQHandler+0x1ac>
if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
8000f34: 06e9 lsls r1, r5, #27
8000f36: d501 bpl.n 8000f3c <HAL_ADC_IRQHandler+0x11c>
8000f38: 06f2 lsls r2, r6, #27
8000f3a: d411 bmi.n 8000f60 <HAL_ADC_IRQHandler+0x140>
if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
8000f3c: 0569 lsls r1, r5, #21
8000f3e: d501 bpl.n 8000f44 <HAL_ADC_IRQHandler+0x124>
8000f40: 0572 lsls r2, r6, #21
8000f42: d466 bmi.n 8001012 <HAL_ADC_IRQHandler+0x1f2>
}
8000f44: bdf8 pop {r3, r4, r5, r6, r7, pc}
if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
8000f46: 0728 lsls r0, r5, #28
8000f48: d5b3 bpl.n 8000eb2 <HAL_ADC_IRQHandler+0x92>
(((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
8000f4a: 0731 lsls r1, r6, #28
8000f4c: d483 bmi.n 8000e56 <HAL_ADC_IRQHandler+0x36>
if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
8000f4e: 06aa lsls r2, r5, #26
8000f50: d4b1 bmi.n 8000eb6 <HAL_ADC_IRQHandler+0x96>
8000f52: 0669 lsls r1, r5, #25
8000f54: d5e2 bpl.n 8000f1c <HAL_ADC_IRQHandler+0xfc>
(((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
8000f56: 0672 lsls r2, r6, #25
8000f58: d5e0 bpl.n 8000f1c <HAL_ADC_IRQHandler+0xfc>
8000f5a: e7ae b.n 8000eba <HAL_ADC_IRQHandler+0x9a>
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
8000f5c: 4a42 ldr r2, [pc, #264] @ (8001068 <HAL_ADC_IRQHandler+0x248>)
8000f5e: e76e b.n 8000e3e <HAL_ADC_IRQHandler+0x1e>
if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
8000f60: 6b22 ldr r2, [r4, #48] @ 0x30
8000f62: b17a cbz r2, 8000f84 <HAL_ADC_IRQHandler+0x164>
if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT)
8000f64: 2f00 cmp r7, #0
8000f66: d075 beq.n 8001054 <HAL_ADC_IRQHandler+0x234>
if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
8000f68: 4a3c ldr r2, [pc, #240] @ (800105c <HAL_ADC_IRQHandler+0x23c>)
8000f6a: 4293 cmp r3, r2
8000f6c: f000 8087 beq.w 800107e <HAL_ADC_IRQHandler+0x25e>
8000f70: f502 7280 add.w r2, r2, #256 @ 0x100
8000f74: 4293 cmp r3, r2
8000f76: f000 8082 beq.w 800107e <HAL_ADC_IRQHandler+0x25e>
8000f7a: 4a39 ldr r2, [pc, #228] @ (8001060 <HAL_ADC_IRQHandler+0x240>)
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DAMDF));
8000f7c: 6892 ldr r2, [r2, #8]
8000f7e: f412 4f40 tst.w r2, #49152 @ 0xc000
8000f82: d00b beq.n 8000f9c <HAL_ADC_IRQHandler+0x17c>
SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
8000f84: 6d63 ldr r3, [r4, #84] @ 0x54
HAL_ADC_ErrorCallback(hadc);
8000f86: 4620 mov r0, r4
SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
8000f88: f443 6380 orr.w r3, r3, #1024 @ 0x400
8000f8c: 6563 str r3, [r4, #84] @ 0x54
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
8000f8e: 6da3 ldr r3, [r4, #88] @ 0x58
8000f90: f043 0302 orr.w r3, r3, #2
8000f94: 65a3 str r3, [r4, #88] @ 0x58
HAL_ADC_ErrorCallback(hadc);
8000f96: f7ff ff41 bl 8000e1c <HAL_ADC_ErrorCallback>
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
8000f9a: 6823 ldr r3, [r4, #0]
8000f9c: 2210 movs r2, #16
8000f9e: 601a str r2, [r3, #0]
8000fa0: e7cc b.n 8000f3c <HAL_ADC_IRQHandler+0x11c>
if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
8000fa2: 6d63 ldr r3, [r4, #84] @ 0x54
8000fa4: 06d8 lsls r0, r3, #27
8000fa6: d403 bmi.n 8000fb0 <HAL_ADC_IRQHandler+0x190>
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
8000fa8: 6d63 ldr r3, [r4, #84] @ 0x54
8000faa: f443 6300 orr.w r3, r3, #2048 @ 0x800
8000fae: 6563 str r3, [r4, #84] @ 0x54
HAL_ADCEx_EndOfSamplingCallback(hadc);
8000fb0: 4620 mov r0, r4
8000fb2: f000 fc43 bl 800183c <HAL_ADCEx_EndOfSamplingCallback>
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
8000fb6: 6823 ldr r3, [r4, #0]
8000fb8: 2202 movs r2, #2
8000fba: 601a str r2, [r3, #0]
8000fbc: e747 b.n 8000e4e <HAL_ADC_IRQHandler+0x2e>
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
8000fbe: 21c1 movs r1, #193 @ 0xc1
8000fc0: 40f9 lsrs r1, r7
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
8000fc2: 07c9 lsls r1, r1, #31
8000fc4: d487 bmi.n 8000ed6 <HAL_ADC_IRQHandler+0xb6>
tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
8000fc6: 4925 ldr r1, [pc, #148] @ (800105c <HAL_ADC_IRQHandler+0x23c>)
8000fc8: 68c9 ldr r1, [r1, #12]
8000fca: e785 b.n 8000ed8 <HAL_ADC_IRQHandler+0xb8>
SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
8000fcc: 6d63 ldr r3, [r4, #84] @ 0x54
HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
8000fce: 4620 mov r0, r4
SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
8000fd0: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8000fd4: 6563 str r3, [r4, #84] @ 0x54
HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
8000fd6: f000 fc2f bl 8001838 <HAL_ADCEx_LevelOutOfWindow3Callback>
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
8000fda: 6823 ldr r3, [r4, #0]
8000fdc: f44f 7200 mov.w r2, #512 @ 0x200
8000fe0: 601a str r2, [r3, #0]
8000fe2: e7a7 b.n 8000f34 <HAL_ADC_IRQHandler+0x114>
SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
8000fe4: 6d63 ldr r3, [r4, #84] @ 0x54
HAL_ADC_LevelOutOfWindowCallback(hadc);
8000fe6: 4620 mov r0, r4
SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
8000fe8: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8000fec: 6563 str r3, [r4, #84] @ 0x54
HAL_ADC_LevelOutOfWindowCallback(hadc);
8000fee: f7ff ff13 bl 8000e18 <HAL_ADC_LevelOutOfWindowCallback>
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
8000ff2: 6823 ldr r3, [r4, #0]
8000ff4: 2280 movs r2, #128 @ 0x80
8000ff6: 601a str r2, [r3, #0]
8000ff8: e794 b.n 8000f24 <HAL_ADC_IRQHandler+0x104>
SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
8000ffa: 6d63 ldr r3, [r4, #84] @ 0x54
HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
8000ffc: 4620 mov r0, r4
SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
8000ffe: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8001002: 6563 str r3, [r4, #84] @ 0x54
HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
8001004: f000 fc16 bl 8001834 <HAL_ADCEx_LevelOutOfWindow2Callback>
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
8001008: 6823 ldr r3, [r4, #0]
800100a: f44f 7280 mov.w r2, #256 @ 0x100
800100e: 601a str r2, [r3, #0]
8001010: e78c b.n 8000f2c <HAL_ADC_IRQHandler+0x10c>
SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
8001012: 6d62 ldr r2, [r4, #84] @ 0x54
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
8001014: f44f 6180 mov.w r1, #1024 @ 0x400
HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
8001018: 4620 mov r0, r4
SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
800101a: f442 4280 orr.w r2, r2, #16384 @ 0x4000
800101e: 6562 str r2, [r4, #84] @ 0x54
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
8001020: 6da2 ldr r2, [r4, #88] @ 0x58
8001022: f042 0208 orr.w r2, r2, #8
8001026: 65a2 str r2, [r4, #88] @ 0x58
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
8001028: 6019 str r1, [r3, #0]
}
800102a: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr}
HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
800102e: f000 bbff b.w 8001830 <HAL_ADCEx_InjectedQueueOverflowCallback>
return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
8001032: f400 6040 and.w r0, r0, #3072 @ 0xc00
(READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))
8001036: f401 5200 and.w r2, r1, #8192 @ 0x2000
((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
800103a: 4302 orrs r2, r0
800103c: f47f af68 bne.w 8000f10 <HAL_ADC_IRQHandler+0xf0>
8001040: e74e b.n 8000ee0 <HAL_ADC_IRQHandler+0xc0>
8001042: f240 2221 movw r2, #545 @ 0x221
8001046: 40fa lsrs r2, r7
8001048: 07d0 lsls r0, r2, #31
800104a: f53f af13 bmi.w 8000e74 <HAL_ADC_IRQHandler+0x54>
tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
800104e: 4a03 ldr r2, [pc, #12] @ (800105c <HAL_ADC_IRQHandler+0x23c>)
8001050: 68d2 ldr r2, [r2, #12]
8001052: e710 b.n 8000e76 <HAL_ADC_IRQHandler+0x56>
if ((hadc->Instance->CFGR & ADC_CFGR_DMNGT) != 0UL)
8001054: 68da ldr r2, [r3, #12]
8001056: 0790 lsls r0, r2, #30
8001058: d0a0 beq.n 8000f9c <HAL_ADC_IRQHandler+0x17c>
800105a: e793 b.n 8000f84 <HAL_ADC_IRQHandler+0x164>
800105c: 40022000 .word 0x40022000
8001060: 58026300 .word 0x58026300
8001064: 40022100 .word 0x40022100
8001068: 40022300 .word 0x40022300
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800106c: 6d63 ldr r3, [r4, #84] @ 0x54
800106e: f043 0310 orr.w r3, r3, #16
8001072: 6563 str r3, [r4, #84] @ 0x54
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8001074: 6da3 ldr r3, [r4, #88] @ 0x58
8001076: f043 0301 orr.w r3, r3, #1
800107a: 65a3 str r3, [r4, #88] @ 0x58
800107c: e713 b.n 8000ea6 <HAL_ADC_IRQHandler+0x86>
if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
800107e: 4a05 ldr r2, [pc, #20] @ (8001094 <HAL_ADC_IRQHandler+0x274>)
8001080: e77c b.n 8000f7c <HAL_ADC_IRQHandler+0x15c>
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8001082: 6d63 ldr r3, [r4, #84] @ 0x54
8001084: f043 0310 orr.w r3, r3, #16
8001088: 6563 str r3, [r4, #84] @ 0x54
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
800108a: 6da3 ldr r3, [r4, #88] @ 0x58
800108c: f043 0301 orr.w r3, r3, #1
8001090: 65a3 str r3, [r4, #88] @ 0x58
8001092: e73d b.n 8000f10 <HAL_ADC_IRQHandler+0xf0>
8001094: 40022300 .word 0x40022300
08001098 <HAL_ADC_ConfigChannel>:
* @param hadc ADC handle
* @param sConfig Structure of ADC channel assigned to ADC group regular.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
{
8001098: b570 push {r4, r5, r6, lr}
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmpOffsetShifted;
uint32_t tmp_config_internal_channel;
__IO uint32_t wait_loop_index = 0;
800109a: 2200 movs r2, #0
{
800109c: b082 sub sp, #8
__IO uint32_t wait_loop_index = 0;
800109e: 9201 str r2, [sp, #4]
}
#endif
}
/* Process locked */
__HAL_LOCK(hadc);
80010a0: f890 2050 ldrb.w r2, [r0, #80] @ 0x50
80010a4: 2a01 cmp r2, #1
80010a6: f000 80ef beq.w 8001288 <HAL_ADC_ConfigChannel+0x1f0>
80010aa: 2401 movs r4, #1
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel number */
/* - Channel rank */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
80010ac: 6802 ldr r2, [r0, #0]
80010ae: 4603 mov r3, r0
__HAL_LOCK(hadc);
80010b0: f880 4050 strb.w r4, [r0, #80] @ 0x50
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
80010b4: 6890 ldr r0, [r2, #8]
80010b6: 0745 lsls r5, r0, #29
80010b8: d509 bpl.n 80010ce <HAL_ADC_ConfigChannel+0x36>
/* enabled and other ADC of the common group are enabled, internal */
/* measurement paths cannot be enabled. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
80010ba: 6d5a ldr r2, [r3, #84] @ 0x54
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
tmp_hal_status = HAL_ERROR;
80010bc: 2001 movs r0, #1
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
80010be: f042 0220 orr.w r2, r2, #32
80010c2: 655a str r2, [r3, #84] @ 0x54
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
80010c4: 2200 movs r2, #0
80010c6: f883 2050 strb.w r2, [r3, #80] @ 0x50
/* Return function status */
return tmp_hal_status;
}
80010ca: b002 add sp, #8
80010cc: bd70 pop {r4, r5, r6, pc}
if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)))
80010ce: 680d ldr r5, [r1, #0]
80010d0: 2d00 cmp r5, #0
hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
80010d2: ea4f 6095 mov.w r0, r5, lsr #26
if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)))
80010d6: db0d blt.n 80010f4 <HAL_ADC_ConfigChannel+0x5c>
hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
80010d8: f3c5 0613 ubfx r6, r5, #0, #20
80010dc: 2e00 cmp r6, #0
80010de: f000 80c1 beq.w 8001264 <HAL_ADC_ConfigChannel+0x1cc>
uint32_t result;
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80010e2: fa95 f5a5 rbit r5, r5
optimisations using the logic "value was passed to __builtin_clz, so it
is non-zero".
ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
single CLZ instruction.
*/
if (value == 0U)
80010e6: b115 cbz r5, 80010ee <HAL_ADC_ConfigChannel+0x56>
{
return 32U;
}
return __builtin_clz(value);
80010e8: fab5 f585 clz r5, r5
80010ec: 40ac lsls r4, r5
80010ee: 69d5 ldr r5, [r2, #28]
80010f0: 432c orrs r4, r5
80010f2: 61d4 str r4, [r2, #28]
LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
80010f4: 684c ldr r4, [r1, #4]
MODIFY_REG(*preg,
80010f6: f04f 0c1f mov.w ip, #31
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
80010fa: f102 0e30 add.w lr, r2, #48 @ 0x30
MODIFY_REG(*preg,
80010fe: f000 001f and.w r0, r0, #31
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
8001102: 09a5 lsrs r5, r4, #6
MODIFY_REG(*preg,
8001104: ea04 040c and.w r4, r4, ip
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
8001108: f005 050c and.w r5, r5, #12
MODIFY_REG(*preg,
800110c: fa0c fc04 lsl.w ip, ip, r4
8001110: 40a0 lsls r0, r4
8001112: f85e 4005 ldr.w r4, [lr, r5]
8001116: ea24 0c0c bic.w ip, r4, ip
800111a: ea4c 0000 orr.w r0, ip, r0
800111e: f84e 0005 str.w r0, [lr, r5]
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
8001122: 6890 ldr r0, [r2, #8]
8001124: f010 0f04 tst.w r0, #4
return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
8001128: 6890 ldr r0, [r2, #8]
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
800112a: d101 bne.n 8001130 <HAL_ADC_ConfigChannel+0x98>
return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
800112c: 0700 lsls r0, r0, #28
800112e: d542 bpl.n 80011b6 <HAL_ADC_ConfigChannel+0x11e>
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
8001130: 6890 ldr r0, [r2, #8]
8001132: 07c6 lsls r6, r0, #31
8001134: d43d bmi.n 80011b2 <HAL_ADC_ConfigChannel+0x11a>
LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff);
8001136: 68cd ldr r5, [r1, #12]
8001138: 680c ldr r4, [r1, #0]
MODIFY_REG(ADCx->DIFSEL,
800113a: f005 0618 and.w r6, r5, #24
800113e: 48a9 ldr r0, [pc, #676] @ (80013e4 <HAL_ADC_ConfigChannel+0x34c>)
8001140: f8d2 10c0 ldr.w r1, [r2, #192] @ 0xc0
8001144: 40f0 lsrs r0, r6
8001146: f3c4 0613 ubfx r6, r4, #0, #20
800114a: 4020 ands r0, r4
800114c: ea21 0106 bic.w r1, r1, r6
8001150: 4301 orrs r1, r0
8001152: f8c2 10c0 str.w r1, [r2, #192] @ 0xc0
if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
8001156: 49a4 ldr r1, [pc, #656] @ (80013e8 <HAL_ADC_ConfigChannel+0x350>)
8001158: 428d cmp r5, r1
800115a: f000 808a beq.w 8001272 <HAL_ADC_ConfigChannel+0x1da>
if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
800115e: 2c00 cmp r4, #0
8001160: da27 bge.n 80011b2 <HAL_ADC_ConfigChannel+0x11a>
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
8001162: 49a2 ldr r1, [pc, #648] @ (80013ec <HAL_ADC_ConfigChannel+0x354>)
8001164: 428a cmp r2, r1
8001166: f000 80bd beq.w 80012e4 <HAL_ADC_ConfigChannel+0x24c>
800116a: f501 7180 add.w r1, r1, #256 @ 0x100
800116e: 428a cmp r2, r1
8001170: f000 80b8 beq.w 80012e4 <HAL_ADC_ConfigChannel+0x24c>
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
8001174: 489e ldr r0, [pc, #632] @ (80013f0 <HAL_ADC_ConfigChannel+0x358>)
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
8001176: 499f ldr r1, [pc, #636] @ (80013f4 <HAL_ADC_ConfigChannel+0x35c>)
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
8001178: 6886 ldr r6, [r0, #8]
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
800117a: 688d ldr r5, [r1, #8]
800117c: 07ed lsls r5, r5, #31
800117e: d49c bmi.n 80010ba <HAL_ADC_ConfigChannel+0x22>
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
8001180: 4d9d ldr r5, [pc, #628] @ (80013f8 <HAL_ADC_ConfigChannel+0x360>)
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
8001182: f006 7ce0 and.w ip, r6, #29360128 @ 0x1c00000
8001186: 42ac cmp r4, r5
8001188: f000 8156 beq.w 8001438 <HAL_ADC_ConfigChannel+0x3a0>
else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
800118c: 4d9b ldr r5, [pc, #620] @ (80013fc <HAL_ADC_ConfigChannel+0x364>)
800118e: 42ac cmp r4, r5
8001190: f000 8118 beq.w 80013c4 <HAL_ADC_ConfigChannel+0x32c>
else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
8001194: 4d9a ldr r5, [pc, #616] @ (8001400 <HAL_ADC_ConfigChannel+0x368>)
8001196: 42ac cmp r4, r5
8001198: d10b bne.n 80011b2 <HAL_ADC_ConfigChannel+0x11a>
if (ADC_VREFINT_INSTANCE(hadc))
800119a: 0274 lsls r4, r6, #9
800119c: d409 bmi.n 80011b2 <HAL_ADC_ConfigChannel+0x11a>
800119e: 428a cmp r2, r1
80011a0: d107 bne.n 80011b2 <HAL_ADC_ConfigChannel+0x11a>
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
80011a2: 6882 ldr r2, [r0, #8]
80011a4: f022 72e0 bic.w r2, r2, #29360128 @ 0x1c00000
80011a8: ea42 020c orr.w r2, r2, ip
80011ac: f442 0280 orr.w r2, r2, #4194304 @ 0x400000
80011b0: 6082 str r2, [r0, #8]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
80011b2: 2000 movs r0, #0
80011b4: e786 b.n 80010c4 <HAL_ADC_ConfigChannel+0x2c>
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
80011b6: 680c ldr r4, [r1, #0]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
80011b8: f102 0c14 add.w ip, r2, #20
MODIFY_REG(*preg,
80011bc: f04f 0e07 mov.w lr, #7
80011c0: 688e ldr r6, [r1, #8]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
80011c2: 0de5 lsrs r5, r4, #23
MODIFY_REG(*preg,
80011c4: f3c4 5404 ubfx r4, r4, #20, #5
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
80011c8: f005 0504 and.w r5, r5, #4
MODIFY_REG(*preg,
80011cc: fa0e fe04 lsl.w lr, lr, r4
80011d0: fa06 f404 lsl.w r4, r6, r4
80011d4: f85c 0005 ldr.w r0, [ip, r5]
80011d8: ea20 000e bic.w r0, r0, lr
80011dc: 4320 orrs r0, r4
80011de: f84c 0005 str.w r0, [ip, r5]
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
80011e2: 4888 ldr r0, [pc, #544] @ (8001404 <HAL_ADC_ConfigChannel+0x36c>)
80011e4: 694d ldr r5, [r1, #20]
80011e6: 6800 ldr r0, [r0, #0]
80011e8: f000 4070 and.w r0, r0, #4026531840 @ 0xf0000000
80011ec: f1b0 5f80 cmp.w r0, #268435456 @ 0x10000000
80011f0: 68d0 ldr r0, [r2, #12]
80011f2: d039 beq.n 8001268 <HAL_ADC_ConfigChannel+0x1d0>
80011f4: f010 0f10 tst.w r0, #16
80011f8: 68d0 ldr r0, [r2, #12]
80011fa: d035 beq.n 8001268 <HAL_ADC_ConfigChannel+0x1d0>
80011fc: 0840 lsrs r0, r0, #1
80011fe: f000 0008 and.w r0, r0, #8
8001202: 4085 lsls r5, r0
if (sConfig->OffsetNumber != ADC_OFFSET_NONE)
8001204: 690e ldr r6, [r1, #16]
LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted);
8001206: 6808 ldr r0, [r1, #0]
if (sConfig->OffsetNumber != ADC_OFFSET_NONE)
8001208: 2e04 cmp r6, #4
800120a: d040 beq.n 800128e <HAL_ADC_ConfigChannel+0x1f6>
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
800120c: f102 0c60 add.w ip, r2, #96 @ 0x60
MODIFY_REG(*preg,
8001210: f000 44f8 and.w r4, r0, #2080374784 @ 0x7c000000
8001214: f85c 0026 ldr.w r0, [ip, r6, lsl #2]
8001218: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000
800121c: 4320 orrs r0, r4
800121e: 4328 orrs r0, r5
8001220: f84c 0026 str.w r0, [ip, r6, lsl #2]
LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
8001224: 7e4c ldrb r4, [r1, #25]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8001226: 690d ldr r5, [r1, #16]
8001228: f1a4 0401 sub.w r4, r4, #1
MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation);
800122c: f85c 0025 ldr.w r0, [ip, r5, lsl #2]
8001230: fab4 f484 clz r4, r4
8001234: f020 4000 bic.w r0, r0, #2147483648 @ 0x80000000
8001238: 0964 lsrs r4, r4, #5
800123a: ea40 70c4 orr.w r0, r0, r4, lsl #31
800123e: f84c 0025 str.w r0, [ip, r5, lsl #2]
LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE);
8001242: 7e08 ldrb r0, [r1, #24]
MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL));
8001244: 690d ldr r5, [r1, #16]
8001246: f1a0 0001 sub.w r0, r0, #1
800124a: 6914 ldr r4, [r2, #16]
800124c: f005 051f and.w r5, r5, #31
8001250: fab0 f080 clz r0, r0
8001254: f424 44f0 bic.w r4, r4, #30720 @ 0x7800
8001258: 0940 lsrs r0, r0, #5
800125a: 02c0 lsls r0, r0, #11
800125c: 40a8 lsls r0, r5
800125e: 4320 orrs r0, r4
8001260: 6110 str r0, [r2, #16]
}
8001262: e765 b.n 8001130 <HAL_ADC_ConfigChannel+0x98>
hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
8001264: 4084 lsls r4, r0
8001266: e742 b.n 80010ee <HAL_ADC_ConfigChannel+0x56>
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
8001268: f3c0 0082 ubfx r0, r0, #2, #3
800126c: 0040 lsls r0, r0, #1
800126e: 4085 lsls r5, r0
8001270: e7c8 b.n 8001204 <HAL_ADC_ConfigChannel+0x16c>
LL_ADC_SetChannelPreselection(hadc->Instance, ADC_CHANNEL_DIFF_NEG_INPUT(hadc, sConfig->Channel));
8001272: 495e ldr r1, [pc, #376] @ (80013ec <HAL_ADC_ConfigChannel+0x354>)
8001274: 428a cmp r2, r1
8001276: d07a beq.n 800136e <HAL_ADC_ConfigChannel+0x2d6>
8001278: 4963 ldr r1, [pc, #396] @ (8001408 <HAL_ADC_ConfigChannel+0x370>)
800127a: 428a cmp r2, r1
800127c: d040 beq.n 8001300 <HAL_ADC_ConfigChannel+0x268>
ADCx->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL));
800127e: 69d1 ldr r1, [r2, #28]
8001280: f041 0101 orr.w r1, r1, #1
8001284: 61d1 str r1, [r2, #28]
}
8001286: e76a b.n 800115e <HAL_ADC_ConfigChannel+0xc6>
__HAL_LOCK(hadc);
8001288: 2002 movs r0, #2
}
800128a: b002 add sp, #8
800128c: bd70 pop {r4, r5, r6, pc}
if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
800128e: 6e15 ldr r5, [r2, #96] @ 0x60
8001290: 0684 lsls r4, r0, #26
8001292: f005 45f8 and.w r5, r5, #2080374784 @ 0x7c000000
8001296: ebb5 6f80 cmp.w r5, r0, lsl #26
800129a: d014 beq.n 80012c6 <HAL_ADC_ConfigChannel+0x22e>
if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
800129c: 6e50 ldr r0, [r2, #100] @ 0x64
800129e: f000 40f8 and.w r0, r0, #2080374784 @ 0x7c000000
80012a2: 4284 cmp r4, r0
80012a4: d019 beq.n 80012da <HAL_ADC_ConfigChannel+0x242>
if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
80012a6: 6e90 ldr r0, [r2, #104] @ 0x68
80012a8: f000 40f8 and.w r0, r0, #2080374784 @ 0x7c000000
80012ac: 4284 cmp r4, r0
80012ae: d00f beq.n 80012d0 <HAL_ADC_ConfigChannel+0x238>
if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
80012b0: 6ed0 ldr r0, [r2, #108] @ 0x6c
80012b2: f000 40f8 and.w r0, r0, #2080374784 @ 0x7c000000
80012b6: 4284 cmp r4, r0
80012b8: f47f af3a bne.w 8001130 <HAL_ADC_ConfigChannel+0x98>
CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE);
80012bc: 6ed0 ldr r0, [r2, #108] @ 0x6c
80012be: f020 4000 bic.w r0, r0, #2147483648 @ 0x80000000
80012c2: 66d0 str r0, [r2, #108] @ 0x6c
80012c4: e734 b.n 8001130 <HAL_ADC_ConfigChannel+0x98>
CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE);
80012c6: 6e10 ldr r0, [r2, #96] @ 0x60
80012c8: f020 4000 bic.w r0, r0, #2147483648 @ 0x80000000
80012cc: 6610 str r0, [r2, #96] @ 0x60
80012ce: e7e5 b.n 800129c <HAL_ADC_ConfigChannel+0x204>
CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE);
80012d0: 6e90 ldr r0, [r2, #104] @ 0x68
80012d2: f020 4000 bic.w r0, r0, #2147483648 @ 0x80000000
80012d6: 6690 str r0, [r2, #104] @ 0x68
80012d8: e7ea b.n 80012b0 <HAL_ADC_ConfigChannel+0x218>
CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE);
80012da: 6e50 ldr r0, [r2, #100] @ 0x64
80012dc: f020 4000 bic.w r0, r0, #2147483648 @ 0x80000000
80012e0: 6650 str r0, [r2, #100] @ 0x64
80012e2: e7e0 b.n 80012a6 <HAL_ADC_ConfigChannel+0x20e>
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
80012e4: 4949 ldr r1, [pc, #292] @ (800140c <HAL_ADC_ConfigChannel+0x374>)
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
80012e6: 4a41 ldr r2, [pc, #260] @ (80013ec <HAL_ADC_ConfigChannel+0x354>)
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
80012e8: 6889 ldr r1, [r1, #8]
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
80012ea: 6892 ldr r2, [r2, #8]
80012ec: f012 0f01 tst.w r2, #1
80012f0: 4a45 ldr r2, [pc, #276] @ (8001408 <HAL_ADC_ConfigChannel+0x370>)
80012f2: 6892 ldr r2, [r2, #8]
80012f4: f47f aee1 bne.w 80010ba <HAL_ADC_ConfigChannel+0x22>
80012f8: 07d2 lsls r2, r2, #31
80012fa: f53f aede bmi.w 80010ba <HAL_ADC_ConfigChannel+0x22>
80012fe: e758 b.n 80011b2 <HAL_ADC_ConfigChannel+0x11a>
LL_ADC_SetChannelPreselection(hadc->Instance, ADC_CHANNEL_DIFF_NEG_INPUT(hadc, sConfig->Channel));
8001300: 4943 ldr r1, [pc, #268] @ (8001410 <HAL_ADC_ConfigChannel+0x378>)
8001302: 428c cmp r4, r1
8001304: d058 beq.n 80013b8 <HAL_ADC_ConfigChannel+0x320>
8001306: 4943 ldr r1, [pc, #268] @ (8001414 <HAL_ADC_ConfigChannel+0x37c>)
8001308: 428c cmp r4, r1
800130a: d057 beq.n 80013bc <HAL_ADC_ConfigChannel+0x324>
800130c: 4942 ldr r1, [pc, #264] @ (8001418 <HAL_ADC_ConfigChannel+0x380>)
800130e: 428c cmp r4, r1
8001310: f000 80b5 beq.w 800147e <HAL_ADC_ConfigChannel+0x3e6>
8001314: 4941 ldr r1, [pc, #260] @ (800141c <HAL_ADC_ConfigChannel+0x384>)
8001316: 428c cmp r4, r1
8001318: f000 80b3 beq.w 8001482 <HAL_ADC_ConfigChannel+0x3ea>
800131c: f101 6186 add.w r1, r1, #70254592 @ 0x4300000
8001320: 3110 adds r1, #16
8001322: 428c cmp r4, r1
8001324: f000 80af beq.w 8001486 <HAL_ADC_ConfigChannel+0x3ee>
8001328: 493d ldr r1, [pc, #244] @ (8001420 <HAL_ADC_ConfigChannel+0x388>)
800132a: 428c cmp r4, r1
800132c: f000 80ad beq.w 800148a <HAL_ADC_ConfigChannel+0x3f2>
8001330: f101 2104 add.w r1, r1, #67109888 @ 0x4000400
8001334: f501 1140 add.w r1, r1, #3145728 @ 0x300000
8001338: 428c cmp r4, r1
800133a: f000 80a8 beq.w 800148e <HAL_ADC_ConfigChannel+0x3f6>
800133e: f101 6186 add.w r1, r1, #70254592 @ 0x4300000
8001342: f501 6100 add.w r1, r1, #2048 @ 0x800
8001346: 428c cmp r4, r1
8001348: f000 80a3 beq.w 8001492 <HAL_ADC_ConfigChannel+0x3fa>
800134c: 4935 ldr r1, [pc, #212] @ (8001424 <HAL_ADC_ConfigChannel+0x38c>)
800134e: 428c cmp r4, r1
8001350: d195 bne.n 800127e <HAL_ADC_ConfigChannel+0x1e6>
8001352: 4935 ldr r1, [pc, #212] @ (8001428 <HAL_ADC_ConfigChannel+0x390>)
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001354: fa91 f1a1 rbit r1, r1
if (value == 0U)
8001358: 2900 cmp r1, #0
800135a: d031 beq.n 80013c0 <HAL_ADC_ConfigChannel+0x328>
return __builtin_clz(value);
800135c: fab1 f181 clz r1, r1
ADCx->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL));
8001360: 2001 movs r0, #1
8001362: fa00 f101 lsl.w r1, r0, r1
8001366: 69d0 ldr r0, [r2, #28]
8001368: 4301 orrs r1, r0
800136a: 61d1 str r1, [r2, #28]
if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
800136c: e721 b.n 80011b2 <HAL_ADC_ConfigChannel+0x11a>
LL_ADC_SetChannelPreselection(hadc->Instance, ADC_CHANNEL_DIFF_NEG_INPUT(hadc, sConfig->Channel));
800136e: 4928 ldr r1, [pc, #160] @ (8001410 <HAL_ADC_ConfigChannel+0x378>)
8001370: 428c cmp r4, r1
8001372: d021 beq.n 80013b8 <HAL_ADC_ConfigChannel+0x320>
8001374: 4927 ldr r1, [pc, #156] @ (8001414 <HAL_ADC_ConfigChannel+0x37c>)
8001376: 428c cmp r4, r1
8001378: d020 beq.n 80013bc <HAL_ADC_ConfigChannel+0x324>
800137a: 4927 ldr r1, [pc, #156] @ (8001418 <HAL_ADC_ConfigChannel+0x380>)
800137c: 428c cmp r4, r1
800137e: d07e beq.n 800147e <HAL_ADC_ConfigChannel+0x3e6>
8001380: 4926 ldr r1, [pc, #152] @ (800141c <HAL_ADC_ConfigChannel+0x384>)
8001382: 428c cmp r4, r1
8001384: d07d beq.n 8001482 <HAL_ADC_ConfigChannel+0x3ea>
8001386: f101 6186 add.w r1, r1, #70254592 @ 0x4300000
800138a: 3110 adds r1, #16
800138c: 428c cmp r4, r1
800138e: d07a beq.n 8001486 <HAL_ADC_ConfigChannel+0x3ee>
8001390: 4923 ldr r1, [pc, #140] @ (8001420 <HAL_ADC_ConfigChannel+0x388>)
8001392: 428c cmp r4, r1
8001394: d079 beq.n 800148a <HAL_ADC_ConfigChannel+0x3f2>
8001396: f101 2104 add.w r1, r1, #67109888 @ 0x4000400
800139a: f501 1140 add.w r1, r1, #3145728 @ 0x300000
800139e: 428c cmp r4, r1
80013a0: d075 beq.n 800148e <HAL_ADC_ConfigChannel+0x3f6>
80013a2: f101 6186 add.w r1, r1, #70254592 @ 0x4300000
80013a6: f501 6100 add.w r1, r1, #2048 @ 0x800
80013aa: 428c cmp r4, r1
80013ac: d071 beq.n 8001492 <HAL_ADC_ConfigChannel+0x3fa>
80013ae: 491f ldr r1, [pc, #124] @ (800142c <HAL_ADC_ConfigChannel+0x394>)
80013b0: 428c cmp r4, r1
80013b2: d1cb bne.n 800134c <HAL_ADC_ConfigChannel+0x2b4>
80013b4: 491e ldr r1, [pc, #120] @ (8001430 <HAL_ADC_ConfigChannel+0x398>)
80013b6: e7cd b.n 8001354 <HAL_ADC_ConfigChannel+0x2bc>
80013b8: 2101 movs r1, #1
80013ba: e7cb b.n 8001354 <HAL_ADC_ConfigChannel+0x2bc>
80013bc: 491d ldr r1, [pc, #116] @ (8001434 <HAL_ADC_ConfigChannel+0x39c>)
80013be: e7c9 b.n 8001354 <HAL_ADC_ConfigChannel+0x2bc>
80013c0: 2101 movs r1, #1
80013c2: e7d0 b.n 8001366 <HAL_ADC_ConfigChannel+0x2ce>
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
80013c4: 01f5 lsls r5, r6, #7
80013c6: f53f aef4 bmi.w 80011b2 <HAL_ADC_ConfigChannel+0x11a>
80013ca: 428a cmp r2, r1
80013cc: f47f aef1 bne.w 80011b2 <HAL_ADC_ConfigChannel+0x11a>
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
80013d0: 6882 ldr r2, [r0, #8]
80013d2: f022 72e0 bic.w r2, r2, #29360128 @ 0x1c00000
80013d6: ea42 020c orr.w r2, r2, ip
80013da: f042 7280 orr.w r2, r2, #16777216 @ 0x1000000
80013de: 6082 str r2, [r0, #8]
}
80013e0: e6e7 b.n 80011b2 <HAL_ADC_ConfigChannel+0x11a>
80013e2: bf00 nop
80013e4: 000fffff .word 0x000fffff
80013e8: 47ff0000 .word 0x47ff0000
80013ec: 40022000 .word 0x40022000
80013f0: 58026300 .word 0x58026300
80013f4: 58026000 .word 0x58026000
80013f8: cb840000 .word 0xcb840000
80013fc: c7520000 .word 0xc7520000
8001400: cfb80000 .word 0xcfb80000
8001404: 5c001000 .word 0x5c001000
8001408: 40022100 .word 0x40022100
800140c: 40022300 .word 0x40022300
8001410: 04300002 .word 0x04300002
8001414: 08600004 .word 0x08600004
8001418: 0c900008 .word 0x0c900008
800141c: 10c00010 .word 0x10c00010
8001420: 2a000400 .word 0x2a000400
8001424: 4b840000 .word 0x4b840000
8001428: 4fb80000 .word 0x4fb80000
800142c: 43210000 .word 0x43210000
8001430: 47520000 .word 0x47520000
8001434: 19200040 .word 0x19200040
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
8001438: 0236 lsls r6, r6, #8
800143a: f53f aeba bmi.w 80011b2 <HAL_ADC_ConfigChannel+0x11a>
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
800143e: 428a cmp r2, r1
8001440: f47f aeb7 bne.w 80011b2 <HAL_ADC_ConfigChannel+0x11a>
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
8001444: 6882 ldr r2, [r0, #8]
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
8001446: 4914 ldr r1, [pc, #80] @ (8001498 <HAL_ADC_ConfigChannel+0x400>)
8001448: f022 72e0 bic.w r2, r2, #29360128 @ 0x1c00000
800144c: ea42 020c orr.w r2, r2, ip
8001450: f442 0200 orr.w r2, r2, #8388608 @ 0x800000
8001454: 6082 str r2, [r0, #8]
8001456: 680a ldr r2, [r1, #0]
8001458: 4910 ldr r1, [pc, #64] @ (800149c <HAL_ADC_ConfigChannel+0x404>)
800145a: 0992 lsrs r2, r2, #6
800145c: fba1 1202 umull r1, r2, r1, r2
8001460: 0992 lsrs r2, r2, #6
8001462: 3201 adds r2, #1
8001464: 0052 lsls r2, r2, #1
8001466: 9201 str r2, [sp, #4]
while (wait_loop_index != 0UL)
8001468: 9a01 ldr r2, [sp, #4]
800146a: 2a00 cmp r2, #0
800146c: f43f aea1 beq.w 80011b2 <HAL_ADC_ConfigChannel+0x11a>
wait_loop_index--;
8001470: 9a01 ldr r2, [sp, #4]
8001472: 3a01 subs r2, #1
8001474: 9201 str r2, [sp, #4]
while (wait_loop_index != 0UL)
8001476: 9a01 ldr r2, [sp, #4]
8001478: 2a00 cmp r2, #0
800147a: d1f9 bne.n 8001470 <HAL_ADC_ConfigChannel+0x3d8>
800147c: e699 b.n 80011b2 <HAL_ADC_ConfigChannel+0x11a>
LL_ADC_SetChannelPreselection(hadc->Instance, ADC_CHANNEL_DIFF_NEG_INPUT(hadc, sConfig->Channel));
800147e: 4908 ldr r1, [pc, #32] @ (80014a0 <HAL_ADC_ConfigChannel+0x408>)
8001480: e768 b.n 8001354 <HAL_ADC_ConfigChannel+0x2bc>
8001482: 4908 ldr r1, [pc, #32] @ (80014a4 <HAL_ADC_ConfigChannel+0x40c>)
8001484: e766 b.n 8001354 <HAL_ADC_ConfigChannel+0x2bc>
8001486: 4908 ldr r1, [pc, #32] @ (80014a8 <HAL_ADC_ConfigChannel+0x410>)
8001488: e764 b.n 8001354 <HAL_ADC_ConfigChannel+0x2bc>
800148a: 4908 ldr r1, [pc, #32] @ (80014ac <HAL_ADC_ConfigChannel+0x414>)
800148c: e762 b.n 8001354 <HAL_ADC_ConfigChannel+0x2bc>
800148e: 4908 ldr r1, [pc, #32] @ (80014b0 <HAL_ADC_ConfigChannel+0x418>)
8001490: e760 b.n 8001354 <HAL_ADC_ConfigChannel+0x2bc>
8001492: 4908 ldr r1, [pc, #32] @ (80014b4 <HAL_ADC_ConfigChannel+0x41c>)
8001494: e75e b.n 8001354 <HAL_ADC_ConfigChannel+0x2bc>
8001496: bf00 nop
8001498: 24000004 .word 0x24000004
800149c: 053e2d63 .word 0x053e2d63
80014a0: 1d500080 .word 0x1d500080
80014a4: 21800100 .word 0x21800100
80014a8: 25b00200 .word 0x25b00200
80014ac: 2e300800 .word 0x2e300800
80014b0: 32601000 .word 0x32601000
80014b4: 36902000 .word 0x36902000
080014b8 <ADC_ConfigureBoostMode>:
* stopped.
* @param hadc ADC handle
* @retval None.
*/
void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc)
{
80014b8: b538 push {r3, r4, r5, lr}
uint32_t freq;
if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc))
80014ba: 4a4f ldr r2, [pc, #316] @ (80015f8 <ADC_ConfigureBoostMode+0x140>)
{
80014bc: 4604 mov r4, r0
if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc))
80014be: 6803 ldr r3, [r0, #0]
80014c0: 4293 cmp r3, r2
80014c2: d024 beq.n 800150e <ADC_ConfigureBoostMode+0x56>
80014c4: f502 7280 add.w r2, r2, #256 @ 0x100
80014c8: 4293 cmp r3, r2
80014ca: d020 beq.n 800150e <ADC_ConfigureBoostMode+0x56>
80014cc: 4b4b ldr r3, [pc, #300] @ (80015fc <ADC_ConfigureBoostMode+0x144>)
80014ce: 689b ldr r3, [r3, #8]
80014d0: f413 3f40 tst.w r3, #196608 @ 0x30000
80014d4: d020 beq.n 8001518 <ADC_ConfigureBoostMode+0x60>
{
freq = HAL_RCC_GetHCLKFreq();
80014d6: f001 fc39 bl 8002d4c <HAL_RCC_GetHCLKFreq>
switch (hadc->Init.ClockPrescaler)
80014da: 6863 ldr r3, [r4, #4]
freq = HAL_RCC_GetHCLKFreq();
80014dc: 4605 mov r5, r0
switch (hadc->Init.ClockPrescaler)
80014de: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
80014e2: d06d beq.n 80015c0 <ADC_ConfigureBoostMode+0x108>
80014e4: f5b3 3f40 cmp.w r3, #196608 @ 0x30000
80014e8: d072 beq.n 80015d0 <ADC_ConfigureBoostMode+0x118>
80014ea: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
80014ee: d067 beq.n 80015c0 <ADC_ConfigureBoostMode+0x108>
else /* if(freq > 25000000UL) */
{
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
}
#else
if (HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */
80014f0: f7ff fc8a bl 8000e08 <HAL_GetREVID>
80014f4: f241 0303 movw r3, #4099 @ 0x1003
80014f8: 4298 cmp r0, r3
80014fa: d82d bhi.n 8001558 <ADC_ConfigureBoostMode+0xa0>
{
if (freq > 20000000UL)
80014fc: 4a40 ldr r2, [pc, #256] @ (8001600 <ADC_ConfigureBoostMode+0x148>)
{
SET_BIT(hadc->Instance->CR, ADC_CR_BOOST_0);
80014fe: 6823 ldr r3, [r4, #0]
if (freq > 20000000UL)
8001500: 4295 cmp r5, r2
8001502: d947 bls.n 8001594 <ADC_ConfigureBoostMode+0xdc>
SET_BIT(hadc->Instance->CR, ADC_CR_BOOST_0);
8001504: 689a ldr r2, [r3, #8]
8001506: f442 7280 orr.w r2, r2, #256 @ 0x100
800150a: 609a str r2, [r3, #8]
{
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
}
}
#endif /* ADC_VER_V5_3 */
}
800150c: bd38 pop {r3, r4, r5, pc}
if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc))
800150e: 4b3d ldr r3, [pc, #244] @ (8001604 <ADC_ConfigureBoostMode+0x14c>)
8001510: 689b ldr r3, [r3, #8]
8001512: f413 3f40 tst.w r3, #196608 @ 0x30000
8001516: d1de bne.n 80014d6 <ADC_ConfigureBoostMode+0x1e>
freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC);
8001518: f44f 2000 mov.w r0, #524288 @ 0x80000
800151c: 2100 movs r1, #0
800151e: f002 fee9 bl 80042f4 <HAL_RCCEx_GetPeriphCLKFreq>
switch (hadc->Init.ClockPrescaler)
8001522: 6863 ldr r3, [r4, #4]
freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC);
8001524: 4605 mov r5, r0
switch (hadc->Init.ClockPrescaler)
8001526: f5b3 1f10 cmp.w r3, #2359296 @ 0x240000
800152a: d04d beq.n 80015c8 <ADC_ConfigureBoostMode+0x110>
800152c: d825 bhi.n 800157a <ADC_ConfigureBoostMode+0xc2>
800152e: f5b3 1fe0 cmp.w r3, #1835008 @ 0x1c0000
8001532: d04b beq.n 80015cc <ADC_ConfigureBoostMode+0x114>
8001534: d84e bhi.n 80015d4 <ADC_ConfigureBoostMode+0x11c>
8001536: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
800153a: d008 beq.n 800154e <ADC_ConfigureBoostMode+0x96>
800153c: d855 bhi.n 80015ea <ADC_ConfigureBoostMode+0x132>
800153e: f5b3 2f00 cmp.w r3, #524288 @ 0x80000
8001542: d004 beq.n 800154e <ADC_ConfigureBoostMode+0x96>
8001544: f423 2200 bic.w r2, r3, #524288 @ 0x80000
8001548: f5b2 2f80 cmp.w r2, #262144 @ 0x40000
800154c: d1d0 bne.n 80014f0 <ADC_ConfigureBoostMode+0x38>
freq /= ((hadc->Init.ClockPrescaler >> ADC_CCR_PRESC_Pos) << 1UL);
800154e: 0c9b lsrs r3, r3, #18
8001550: 005b lsls r3, r3, #1
8001552: fbb5 f5f3 udiv r5, r5, r3
break;
8001556: e7cb b.n 80014f0 <ADC_ConfigureBoostMode+0x38>
if (freq <= 6250000UL)
8001558: 4a2b ldr r2, [pc, #172] @ (8001608 <ADC_ConfigureBoostMode+0x150>)
SET_BIT(hadc->Instance->CR, ADC_CR_BOOST_0);
800155a: 6823 ldr r3, [r4, #0]
if (freq <= 6250000UL)
800155c: 4295 cmp r5, r2
800155e: d923 bls.n 80015a8 <ADC_ConfigureBoostMode+0xf0>
else if (freq <= 12500000UL)
8001560: 4a2a ldr r2, [pc, #168] @ (800160c <ADC_ConfigureBoostMode+0x154>)
8001562: 4295 cmp r5, r2
8001564: d925 bls.n 80015b2 <ADC_ConfigureBoostMode+0xfa>
else if (freq <= 25000000UL)
8001566: 4a2a ldr r2, [pc, #168] @ (8001610 <ADC_ConfigureBoostMode+0x158>)
8001568: 4295 cmp r5, r2
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1);
800156a: 689a ldr r2, [r3, #8]
else if (freq <= 25000000UL)
800156c: d839 bhi.n 80015e2 <ADC_ConfigureBoostMode+0x12a>
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1);
800156e: f422 7240 bic.w r2, r2, #768 @ 0x300
8001572: f442 7200 orr.w r2, r2, #512 @ 0x200
8001576: 609a str r2, [r3, #8]
}
8001578: bd38 pop {r3, r4, r5, pc}
switch (hadc->Init.ClockPrescaler)
800157a: f5b3 1f20 cmp.w r3, #2621440 @ 0x280000
800157e: d02e beq.n 80015de <ADC_ConfigureBoostMode+0x126>
8001580: f5b3 1f30 cmp.w r3, #2883584 @ 0x2c0000
8001584: d1b4 bne.n 80014f0 <ADC_ConfigureBoostMode+0x38>
if (HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */
8001586: f7ff fc3f bl 8000e08 <HAL_GetREVID>
800158a: f241 0303 movw r3, #4099 @ 0x1003
800158e: 4298 cmp r0, r3
8001590: d805 bhi.n 800159e <ADC_ConfigureBoostMode+0xe6>
8001592: 6823 ldr r3, [r4, #0]
CLEAR_BIT(hadc->Instance->CR, ADC_CR_BOOST_0);
8001594: 689a ldr r2, [r3, #8]
8001596: f422 7280 bic.w r2, r2, #256 @ 0x100
800159a: 609a str r2, [r3, #8]
}
800159c: bd38 pop {r3, r4, r5, pc}
if (freq <= 6250000UL)
800159e: 4b1a ldr r3, [pc, #104] @ (8001608 <ADC_ConfigureBoostMode+0x150>)
80015a0: ebb3 2f15 cmp.w r3, r5, lsr #8
80015a4: 6823 ldr r3, [r4, #0]
80015a6: d304 bcc.n 80015b2 <ADC_ConfigureBoostMode+0xfa>
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL);
80015a8: 689a ldr r2, [r3, #8]
80015aa: f422 7240 bic.w r2, r2, #768 @ 0x300
80015ae: 609a str r2, [r3, #8]
}
80015b0: bd38 pop {r3, r4, r5, pc}
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0);
80015b2: 689a ldr r2, [r3, #8]
80015b4: f422 7240 bic.w r2, r2, #768 @ 0x300
80015b8: f442 7280 orr.w r2, r2, #256 @ 0x100
80015bc: 609a str r2, [r3, #8]
}
80015be: bd38 pop {r3, r4, r5, pc}
freq /= (hadc->Init.ClockPrescaler >> ADC_CCR_CKMODE_Pos);
80015c0: 0c1b lsrs r3, r3, #16
80015c2: fbb5 f5f3 udiv r5, r5, r3
break;
80015c6: e793 b.n 80014f0 <ADC_ConfigureBoostMode+0x38>
freq /= 64UL;
80015c8: 0985 lsrs r5, r0, #6
break;
80015ca: e791 b.n 80014f0 <ADC_ConfigureBoostMode+0x38>
freq /= 16UL;
80015cc: 0905 lsrs r5, r0, #4
break;
80015ce: e78f b.n 80014f0 <ADC_ConfigureBoostMode+0x38>
freq /= 4UL;
80015d0: 0885 lsrs r5, r0, #2
break;
80015d2: e78d b.n 80014f0 <ADC_ConfigureBoostMode+0x38>
switch (hadc->Init.ClockPrescaler)
80015d4: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000
80015d8: d18a bne.n 80014f0 <ADC_ConfigureBoostMode+0x38>
freq /= 32UL;
80015da: 0945 lsrs r5, r0, #5
break;
80015dc: e788 b.n 80014f0 <ADC_ConfigureBoostMode+0x38>
freq /= 128UL;
80015de: 09c5 lsrs r5, r0, #7
break;
80015e0: e786 b.n 80014f0 <ADC_ConfigureBoostMode+0x38>
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
80015e2: f442 7240 orr.w r2, r2, #768 @ 0x300
80015e6: 609a str r2, [r3, #8]
}
80015e8: bd38 pop {r3, r4, r5, pc}
switch (hadc->Init.ClockPrescaler)
80015ea: f5b3 1fa0 cmp.w r3, #1310720 @ 0x140000
80015ee: d0ae beq.n 800154e <ADC_ConfigureBoostMode+0x96>
80015f0: f5b3 1fc0 cmp.w r3, #1572864 @ 0x180000
80015f4: d0ab beq.n 800154e <ADC_ConfigureBoostMode+0x96>
80015f6: e77b b.n 80014f0 <ADC_ConfigureBoostMode+0x38>
80015f8: 40022000 .word 0x40022000
80015fc: 58026300 .word 0x58026300
8001600: 01312d00 .word 0x01312d00
8001604: 40022300 .word 0x40022300
8001608: 00bebc21 .word 0x00bebc21
800160c: 017d7841 .word 0x017d7841
8001610: 02faf081 .word 0x02faf081
08001614 <HAL_ADC_Init>:
{
8001614: b570 push {r4, r5, r6, lr}
__IO uint32_t wait_loop_index = 0UL;
8001616: 2300 movs r3, #0
{
8001618: b082 sub sp, #8
__IO uint32_t wait_loop_index = 0UL;
800161a: 9301 str r3, [sp, #4]
if (hadc == NULL)
800161c: 2800 cmp r0, #0
800161e: f000 80a9 beq.w 8001774 <HAL_ADC_Init+0x160>
if (hadc->State == HAL_ADC_STATE_RESET)
8001622: 6d45 ldr r5, [r0, #84] @ 0x54
8001624: 4604 mov r4, r0
8001626: 2d00 cmp r5, #0
8001628: f000 80aa beq.w 8001780 <HAL_ADC_Init+0x16c>
if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
800162c: 6822 ldr r2, [r4, #0]
return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
800162e: 6893 ldr r3, [r2, #8]
8001630: 009d lsls r5, r3, #2
8001632: d503 bpl.n 800163c <HAL_ADC_Init+0x28>
CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
8001634: 6891 ldr r1, [r2, #8]
8001636: 4b71 ldr r3, [pc, #452] @ (80017fc <HAL_ADC_Init+0x1e8>)
8001638: 400b ands r3, r1
800163a: 6093 str r3, [r2, #8]
return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
800163c: 6893 ldr r3, [r2, #8]
800163e: 00d8 lsls r0, r3, #3
8001640: d416 bmi.n 8001670 <HAL_ADC_Init+0x5c>
wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
8001642: 4b6f ldr r3, [pc, #444] @ (8001800 <HAL_ADC_Init+0x1ec>)
8001644: 496f ldr r1, [pc, #444] @ (8001804 <HAL_ADC_Init+0x1f0>)
8001646: 681b ldr r3, [r3, #0]
MODIFY_REG(ADCx->CR,
8001648: 6890 ldr r0, [r2, #8]
800164a: 099b lsrs r3, r3, #6
800164c: fba1 1303 umull r1, r3, r1, r3
8001650: 496d ldr r1, [pc, #436] @ (8001808 <HAL_ADC_Init+0x1f4>)
8001652: 099b lsrs r3, r3, #6
8001654: 4001 ands r1, r0
8001656: 3301 adds r3, #1
8001658: f041 5180 orr.w r1, r1, #268435456 @ 0x10000000
800165c: 6091 str r1, [r2, #8]
800165e: 9301 str r3, [sp, #4]
while (wait_loop_index != 0UL)
8001660: 9b01 ldr r3, [sp, #4]
8001662: b12b cbz r3, 8001670 <HAL_ADC_Init+0x5c>
wait_loop_index--;
8001664: 9b01 ldr r3, [sp, #4]
8001666: 3b01 subs r3, #1
8001668: 9301 str r3, [sp, #4]
while (wait_loop_index != 0UL)
800166a: 9b01 ldr r3, [sp, #4]
800166c: 2b00 cmp r3, #0
800166e: d1f9 bne.n 8001664 <HAL_ADC_Init+0x50>
return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
8001670: 6893 ldr r3, [r2, #8]
8001672: 00d9 lsls r1, r3, #3
8001674: f100 8082 bmi.w 800177c <HAL_ADC_Init+0x168>
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8001678: 6d63 ldr r3, [r4, #84] @ 0x54
tmp_hal_status = HAL_ERROR;
800167a: 2501 movs r5, #1
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800167c: f043 0310 orr.w r3, r3, #16
8001680: 6563 str r3, [r4, #84] @ 0x54
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8001682: 6da3 ldr r3, [r4, #88] @ 0x58
8001684: 432b orrs r3, r5
8001686: 65a3 str r3, [r4, #88] @ 0x58
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
8001688: 6893 ldr r3, [r2, #8]
800168a: f013 0f04 tst.w r3, #4
if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
800168e: 6d63 ldr r3, [r4, #84] @ 0x54
8001690: d16c bne.n 800176c <HAL_ADC_Init+0x158>
8001692: 06db lsls r3, r3, #27
8001694: d46a bmi.n 800176c <HAL_ADC_Init+0x158>
ADC_STATE_CLR_SET(hadc->State,
8001696: 6d63 ldr r3, [r4, #84] @ 0x54
8001698: f423 7381 bic.w r3, r3, #258 @ 0x102
800169c: f043 0302 orr.w r3, r3, #2
80016a0: 6563 str r3, [r4, #84] @ 0x54
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
80016a2: 6893 ldr r3, [r2, #8]
80016a4: 07de lsls r6, r3, #31
80016a6: d40c bmi.n 80016c2 <HAL_ADC_Init+0xae>
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
80016a8: 4b58 ldr r3, [pc, #352] @ (800180c <HAL_ADC_Init+0x1f8>)
80016aa: 429a cmp r2, r3
80016ac: f000 8081 beq.w 80017b2 <HAL_ADC_Init+0x19e>
80016b0: f503 7380 add.w r3, r3, #256 @ 0x100
80016b4: 429a cmp r2, r3
80016b6: d07c beq.n 80017b2 <HAL_ADC_Init+0x19e>
80016b8: 4b55 ldr r3, [pc, #340] @ (8001810 <HAL_ADC_Init+0x1fc>)
80016ba: 689b ldr r3, [r3, #8]
80016bc: 07d9 lsls r1, r3, #31
80016be: f140 808a bpl.w 80017d6 <HAL_ADC_Init+0x1c2>
if ((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution))
80016c2: f7ff fba1 bl 8000e08 <HAL_GetREVID>
80016c6: f241 0303 movw r3, #4099 @ 0x1003
80016ca: 68a1 ldr r1, [r4, #8]
80016cc: 4298 cmp r0, r3
ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
80016ce: 7f23 ldrb r3, [r4, #28]
if ((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution))
80016d0: d85c bhi.n 800178c <HAL_ADC_Init+0x178>
tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
80016d2: f894 c015 ldrb.w ip, [r4, #21]
ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
80016d6: 041a lsls r2, r3, #16
tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
80016d8: 6b20 ldr r0, [r4, #48] @ 0x30
80016da: ea42 324c orr.w r2, r2, ip, lsl #13
80016de: 4302 orrs r2, r0
80016e0: 430a orrs r2, r1
if (hadc->Init.DiscontinuousConvMode == ENABLE)
80016e2: 2b01 cmp r3, #1
80016e4: d103 bne.n 80016ee <HAL_ADC_Init+0xda>
tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
80016e6: 6a23 ldr r3, [r4, #32]
80016e8: 3b01 subs r3, #1
80016ea: ea42 4243 orr.w r2, r2, r3, lsl #17
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
80016ee: 6a63 ldr r3, [r4, #36] @ 0x24
80016f0: b123 cbz r3, 80016fc <HAL_ADC_Init+0xe8>
tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
80016f2: f403 7378 and.w r3, r3, #992 @ 0x3e0
| hadc->Init.ExternalTrigConvEdge
80016f6: 6aa1 ldr r1, [r4, #40] @ 0x28
80016f8: 430b orrs r3, r1
tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
80016fa: 431a orrs r2, r3
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
80016fc: 6823 ldr r3, [r4, #0]
80016fe: 4945 ldr r1, [pc, #276] @ (8001814 <HAL_ADC_Init+0x200>)
8001700: 68d8 ldr r0, [r3, #12]
8001702: 4001 ands r1, r0
8001704: 4311 orrs r1, r2
8001706: 60d9 str r1, [r3, #12]
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
8001708: 689a ldr r2, [r3, #8]
800170a: f012 0f04 tst.w r2, #4
return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
800170e: 689a ldr r2, [r3, #8]
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
8001710: d11c bne.n 800174c <HAL_ADC_Init+0x138>
return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
8001712: 0712 lsls r2, r2, #28
8001714: d41a bmi.n 800174c <HAL_ADC_Init+0x138>
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
8001716: 68d8 ldr r0, [r3, #12]
8001718: 4a3f ldr r2, [pc, #252] @ (8001818 <HAL_ADC_Init+0x204>)
ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
800171a: 7d21 ldrb r1, [r4, #20]
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
800171c: 4002 ands r2, r0
800171e: ea42 3281 orr.w r2, r2, r1, lsl #14
8001722: 6ae1 ldr r1, [r4, #44] @ 0x2c
8001724: 430a orrs r2, r1
8001726: 60da str r2, [r3, #12]
if (hadc->Init.OversamplingMode == ENABLE)
8001728: f894 2038 ldrb.w r2, [r4, #56] @ 0x38
800172c: 2a01 cmp r2, #1
800172e: d054 beq.n 80017da <HAL_ADC_Init+0x1c6>
CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
8001730: 691a ldr r2, [r3, #16]
8001732: f022 0201 bic.w r2, r2, #1
8001736: 611a str r2, [r3, #16]
MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift);
8001738: 691a ldr r2, [r3, #16]
ADC_ConfigureBoostMode(hadc);
800173a: 4620 mov r0, r4
MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift);
800173c: 6b61 ldr r1, [r4, #52] @ 0x34
800173e: f022 4270 bic.w r2, r2, #4026531840 @ 0xf0000000
8001742: 430a orrs r2, r1
8001744: 611a str r2, [r3, #16]
ADC_ConfigureBoostMode(hadc);
8001746: f7ff feb7 bl 80014b8 <ADC_ConfigureBoostMode>
MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
800174a: 6823 ldr r3, [r4, #0]
if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
800174c: 68e2 ldr r2, [r4, #12]
800174e: 2a01 cmp r2, #1
8001750: d027 beq.n 80017a2 <HAL_ADC_Init+0x18e>
CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
8001752: 6b1a ldr r2, [r3, #48] @ 0x30
8001754: f022 020f bic.w r2, r2, #15
8001758: 631a str r2, [r3, #48] @ 0x30
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
800175a: 6d63 ldr r3, [r4, #84] @ 0x54
}
800175c: 4628 mov r0, r5
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
800175e: f023 0303 bic.w r3, r3, #3
8001762: f043 0301 orr.w r3, r3, #1
8001766: 6563 str r3, [r4, #84] @ 0x54
}
8001768: b002 add sp, #8
800176a: bd70 pop {r4, r5, r6, pc}
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800176c: 6d63 ldr r3, [r4, #84] @ 0x54
800176e: f043 0310 orr.w r3, r3, #16
8001772: 6563 str r3, [r4, #84] @ 0x54
return HAL_ERROR;
8001774: 2501 movs r5, #1
}
8001776: 4628 mov r0, r5
8001778: b002 add sp, #8
800177a: bd70 pop {r4, r5, r6, pc}
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
800177c: 2500 movs r5, #0
800177e: e783 b.n 8001688 <HAL_ADC_Init+0x74>
HAL_ADC_MspInit(hadc);
8001780: f7fe ff84 bl 800068c <HAL_ADC_MspInit>
ADC_CLEAR_ERRORCODE(hadc);
8001784: 65a5 str r5, [r4, #88] @ 0x58
hadc->Lock = HAL_UNLOCKED;
8001786: f884 5050 strb.w r5, [r4, #80] @ 0x50
800178a: e74f b.n 800162c <HAL_ADC_Init+0x18>
if ((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution))
800178c: 2910 cmp r1, #16
800178e: d1a0 bne.n 80016d2 <HAL_ADC_Init+0xbe>
tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
8001790: 7d61 ldrb r1, [r4, #21]
ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
8001792: 041a lsls r2, r3, #16
tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
8001794: ea42 3241 orr.w r2, r2, r1, lsl #13
8001798: 6b21 ldr r1, [r4, #48] @ 0x30
800179a: 430a orrs r2, r1
800179c: f042 021c orr.w r2, r2, #28
80017a0: e79f b.n 80016e2 <HAL_ADC_Init+0xce>
MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
80017a2: 6b19 ldr r1, [r3, #48] @ 0x30
80017a4: 69a2 ldr r2, [r4, #24]
80017a6: f021 010f bic.w r1, r1, #15
80017aa: 3a01 subs r2, #1
80017ac: 430a orrs r2, r1
80017ae: 631a str r2, [r3, #48] @ 0x30
80017b0: e7d3 b.n 800175a <HAL_ADC_Init+0x146>
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
80017b2: 4b16 ldr r3, [pc, #88] @ (800180c <HAL_ADC_Init+0x1f8>)
80017b4: 689b ldr r3, [r3, #8]
80017b6: f013 0f01 tst.w r3, #1
80017ba: 4b18 ldr r3, [pc, #96] @ (800181c <HAL_ADC_Init+0x208>)
80017bc: 689b ldr r3, [r3, #8]
80017be: d180 bne.n 80016c2 <HAL_ADC_Init+0xae>
80017c0: 07d8 lsls r0, r3, #31
80017c2: f53f af7e bmi.w 80016c2 <HAL_ADC_Init+0xae>
LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
80017c6: 4a16 ldr r2, [pc, #88] @ (8001820 <HAL_ADC_Init+0x20c>)
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
80017c8: 6893 ldr r3, [r2, #8]
80017ca: 6861 ldr r1, [r4, #4]
80017cc: f423 137c bic.w r3, r3, #4128768 @ 0x3f0000
80017d0: 430b orrs r3, r1
80017d2: 6093 str r3, [r2, #8]
}
80017d4: e775 b.n 80016c2 <HAL_ADC_Init+0xae>
80017d6: 4a13 ldr r2, [pc, #76] @ (8001824 <HAL_ADC_Init+0x210>)
80017d8: e7f6 b.n 80017c8 <HAL_ADC_Init+0x1b4>
MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
80017da: e9d4 120f ldrd r1, r2, [r4, #60] @ 0x3c
80017de: 6c66 ldr r6, [r4, #68] @ 0x44
80017e0: 3901 subs r1, #1
80017e2: 6918 ldr r0, [r3, #16]
80017e4: 4332 orrs r2, r6
80017e6: ea42 4201 orr.w r2, r2, r1, lsl #16
80017ea: 6ca1 ldr r1, [r4, #72] @ 0x48
80017ec: 430a orrs r2, r1
80017ee: 490e ldr r1, [pc, #56] @ (8001828 <HAL_ADC_Init+0x214>)
80017f0: 4001 ands r1, r0
80017f2: 430a orrs r2, r1
80017f4: f042 0201 orr.w r2, r2, #1
80017f8: 611a str r2, [r3, #16]
80017fa: e79d b.n 8001738 <HAL_ADC_Init+0x124>
80017fc: 5fffffc0 .word 0x5fffffc0
8001800: 24000004 .word 0x24000004
8001804: 053e2d63 .word 0x053e2d63
8001808: 6fffffc0 .word 0x6fffffc0
800180c: 40022000 .word 0x40022000
8001810: 58026000 .word 0x58026000
8001814: fff0c003 .word 0xfff0c003
8001818: ffffbffc .word 0xffffbffc
800181c: 40022100 .word 0x40022100
8001820: 40022300 .word 0x40022300
8001824: 58026300 .word 0x58026300
8001828: fc00f81e .word 0xfc00f81e
0800182c <HAL_ADCEx_InjectedConvCpltCallback>:
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
*/
}
800182c: 4770 bx lr
800182e: bf00 nop
08001830 <HAL_ADCEx_InjectedQueueOverflowCallback>:
and if a new injected context is set when queue is full (maximum 2
contexts).
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc)
8001830: 4770 bx lr
8001832: bf00 nop
08001834 <HAL_ADCEx_LevelOutOfWindow2Callback>:
/**
* @brief Analog watchdog 2 callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
8001834: 4770 bx lr
8001836: bf00 nop
08001838 <HAL_ADCEx_LevelOutOfWindow3Callback>:
/**
* @brief Analog watchdog 3 callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
8001838: 4770 bx lr
800183a: bf00 nop
0800183c <HAL_ADCEx_EndOfSamplingCallback>:
/**
* @brief End Of Sampling callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
800183c: 4770 bx lr
800183e: bf00 nop
08001840 <HAL_NVIC_SetPriorityGrouping>:
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */
8001840: 4906 ldr r1, [pc, #24] @ (800185c <HAL_NVIC_SetPriorityGrouping+0x1c>)
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8001842: f64f 0cff movw ip, #63743 @ 0xf8ff
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8001846: 0200 lsls r0, r0, #8
reg_value = (reg_value |
8001848: 4b05 ldr r3, [pc, #20] @ (8001860 <HAL_NVIC_SetPriorityGrouping+0x20>)
reg_value = SCB->AIRCR; /* read old register configuration */
800184a: 68ca ldr r2, [r1, #12]
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
800184c: f400 60e0 and.w r0, r0, #1792 @ 0x700
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8001850: ea02 020c and.w r2, r2, ip
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8001854: 4310 orrs r0, r2
reg_value = (reg_value |
8001856: 4303 orrs r3, r0
SCB->AIRCR = reg_value;
8001858: 60cb str r3, [r1, #12]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
}
800185a: 4770 bx lr
800185c: e000ed00 .word 0xe000ed00
8001860: 05fa0000 .word 0x05fa0000
08001864 <HAL_NVIC_SetPriority>:
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8001864: 4b1a ldr r3, [pc, #104] @ (80018d0 <HAL_NVIC_SetPriority+0x6c>)
8001866: 68db ldr r3, [r3, #12]
8001868: f3c3 2302 ubfx r3, r3, #8, #3
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
800186c: b500 push {lr}
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
800186e: f1c3 0e07 rsb lr, r3, #7
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8001872: f103 0c04 add.w ip, r3, #4
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8001876: f1be 0f04 cmp.w lr, #4
800187a: bf28 it cs
800187c: f04f 0e04 movcs.w lr, #4
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8001880: f1bc 0f06 cmp.w ip, #6
8001884: d91a bls.n 80018bc <HAL_NVIC_SetPriority+0x58>
8001886: f1a3 0c03 sub.w ip, r3, #3
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
800188a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
800188e: fa03 f30c lsl.w r3, r3, ip
8001892: ea22 0203 bic.w r2, r2, r3
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8001896: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
if ((int32_t)(IRQn) >= 0)
800189a: 2800 cmp r0, #0
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
800189c: fa03 f30e lsl.w r3, r3, lr
80018a0: ea21 0303 bic.w r3, r1, r3
80018a4: fa03 f30c lsl.w r3, r3, ip
80018a8: ea43 0302 orr.w r3, r3, r2
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80018ac: ea4f 1303 mov.w r3, r3, lsl #4
80018b0: b2db uxtb r3, r3
if ((int32_t)(IRQn) >= 0)
80018b2: db06 blt.n 80018c2 <HAL_NVIC_SetPriority+0x5e>
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80018b4: 4a07 ldr r2, [pc, #28] @ (80018d4 <HAL_NVIC_SetPriority+0x70>)
80018b6: 5413 strb r3, [r2, r0]
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
}
80018b8: f85d fb04 ldr.w pc, [sp], #4
80018bc: 2200 movs r2, #0
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80018be: 4694 mov ip, r2
80018c0: e7e9 b.n 8001896 <HAL_NVIC_SetPriority+0x32>
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80018c2: f000 000f and.w r0, r0, #15
80018c6: 4a04 ldr r2, [pc, #16] @ (80018d8 <HAL_NVIC_SetPriority+0x74>)
80018c8: 5413 strb r3, [r2, r0]
80018ca: f85d fb04 ldr.w pc, [sp], #4
80018ce: bf00 nop
80018d0: e000ed00 .word 0xe000ed00
80018d4: e000e400 .word 0xe000e400
80018d8: e000ed14 .word 0xe000ed14
080018dc <HAL_NVIC_EnableIRQ>:
if ((int32_t)(IRQn) >= 0)
80018dc: 2800 cmp r0, #0
80018de: db07 blt.n 80018f0 <HAL_NVIC_EnableIRQ+0x14>
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
80018e0: 2301 movs r3, #1
80018e2: f000 011f and.w r1, r0, #31
80018e6: 4a03 ldr r2, [pc, #12] @ (80018f4 <HAL_NVIC_EnableIRQ+0x18>)
80018e8: 0940 lsrs r0, r0, #5
80018ea: 408b lsls r3, r1
80018ec: f842 3020 str.w r3, [r2, r0, lsl #2]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
}
80018f0: 4770 bx lr
80018f2: bf00 nop
80018f4: e000e100 .word 0xe000e100
080018f8 <HAL_SYSTICK_Config>:
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
80018f8: 1e43 subs r3, r0, #1
80018fa: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
80018fe: d301 bcc.n 8001904 <HAL_SYSTICK_Config+0xc>
{
return (1UL); /* Reload value impossible */
8001900: 2001 movs r0, #1
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
return SysTick_Config(TicksNumb);
}
8001902: 4770 bx lr
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8001904: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8001908: 2000 movs r0, #0
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800190a: 4905 ldr r1, [pc, #20] @ (8001920 <HAL_SYSTICK_Config+0x28>)
800190c: f04f 0cf0 mov.w ip, #240 @ 0xf0
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8001910: 6153 str r3, [r2, #20]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8001912: 2307 movs r3, #7
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8001914: f881 c023 strb.w ip, [r1, #35] @ 0x23
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8001918: 6190 str r0, [r2, #24]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
800191a: 6113 str r3, [r2, #16]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
800191c: 4770 bx lr
800191e: bf00 nop
8001920: e000ed00 .word 0xe000ed00
08001924 <HAL_MPU_Disable>:
__ASM volatile ("dmb 0xF":::"memory");
8001924: f3bf 8f5f dmb sy
{
/* Make sure outstanding transfers are done */
__DMB();
/* Disable fault exceptions */
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
8001928: 4b04 ldr r3, [pc, #16] @ (800193c <HAL_MPU_Disable+0x18>)
/* Disable the MPU and clear the control register*/
MPU->CTRL = 0;
800192a: 2100 movs r1, #0
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
800192c: 6a5a ldr r2, [r3, #36] @ 0x24
800192e: f422 3280 bic.w r2, r2, #65536 @ 0x10000
8001932: 625a str r2, [r3, #36] @ 0x24
MPU->CTRL = 0;
8001934: f8c3 1094 str.w r1, [r3, #148] @ 0x94
}
8001938: 4770 bx lr
800193a: bf00 nop
800193c: e000ed00 .word 0xe000ed00
08001940 <HAL_MPU_Enable>:
* @retval None
*/
void HAL_MPU_Enable(uint32_t MPU_Control)
{
/* Enable the MPU */
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
8001940: 4b06 ldr r3, [pc, #24] @ (800195c <HAL_MPU_Enable+0x1c>)
8001942: f040 0001 orr.w r0, r0, #1
8001946: f8c3 0094 str.w r0, [r3, #148] @ 0x94
/* Enable fault exceptions */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
800194a: 6a5a ldr r2, [r3, #36] @ 0x24
800194c: f442 3280 orr.w r2, r2, #65536 @ 0x10000
8001950: 625a str r2, [r3, #36] @ 0x24
__ASM volatile ("dsb 0xF":::"memory");
8001952: f3bf 8f4f dsb sy
__ASM volatile ("isb 0xF":::"memory");
8001956: f3bf 8f6f isb sy
/* Ensure MPU setting take effects */
__DSB();
__ISB();
}
800195a: 4770 bx lr
800195c: e000ed00 .word 0xe000ed00
08001960 <HAL_MPU_ConfigRegion>:
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
/* Set the Region number */
MPU->RNR = MPU_Init->Number;
8001960: 4a16 ldr r2, [pc, #88] @ (80019bc <HAL_MPU_ConfigRegion+0x5c>)
8001962: 7843 ldrb r3, [r0, #1]
8001964: f8c2 3098 str.w r3, [r2, #152] @ 0x98
/* Disable the Region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
8001968: f8d2 30a0 ldr.w r3, [r2, #160] @ 0xa0
800196c: f023 0301 bic.w r3, r3, #1
8001970: f8c2 30a0 str.w r3, [r2, #160] @ 0xa0
/* Apply configuration */
MPU->RBAR = MPU_Init->BaseAddress;
8001974: 6843 ldr r3, [r0, #4]
8001976: f8c2 309c str.w r3, [r2, #156] @ 0x9c
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
800197a: 7ac3 ldrb r3, [r0, #11]
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
800197c: f890 c00c ldrb.w ip, [r0, #12]
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
8001980: 061b lsls r3, r3, #24
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
8001982: 7801 ldrb r1, [r0, #0]
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
8001984: ea43 730c orr.w r3, r3, ip, lsl #28
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
8001988: f890 c00a ldrb.w ip, [r0, #10]
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
800198c: 430b orrs r3, r1
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
800198e: 7b41 ldrb r1, [r0, #13]
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
8001990: ea43 43cc orr.w r3, r3, ip, lsl #19
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
8001994: f890 c00e ldrb.w ip, [r0, #14]
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
8001998: ea43 4381 orr.w r3, r3, r1, lsl #18
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
800199c: 7bc1 ldrb r1, [r0, #15]
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
800199e: ea43 434c orr.w r3, r3, ip, lsl #17
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
80019a2: f890 c009 ldrb.w ip, [r0, #9]
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
80019a6: ea43 4301 orr.w r3, r3, r1, lsl #16
80019aa: 7a01 ldrb r1, [r0, #8]
80019ac: ea43 230c orr.w r3, r3, ip, lsl #8
80019b0: ea43 0341 orr.w r3, r3, r1, lsl #1
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
80019b4: f8c2 30a0 str.w r3, [r2, #160] @ 0xa0
}
80019b8: 4770 bx lr
80019ba: bf00 nop
80019bc: e000ed00 .word 0xe000ed00
080019c0 <HAL_DMA_Abort>:
* and the Stream will be effectively disabled only after the transfer of
* this single data is finished.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
80019c0: b570 push {r4, r5, r6, lr}
80019c2: 4604 mov r4, r0
/* calculate DMA base and stream number */
DMA_Base_Registers *regs_dma;
BDMA_Base_Registers *regs_bdma;
const __IO uint32_t *enableRegister;
uint32_t tickstart = HAL_GetTick();
80019c4: f7ff fa08 bl 8000dd8 <HAL_GetTick>
/* Check the DMA peripheral handle */
if(hdma == NULL)
80019c8: 2c00 cmp r4, #0
80019ca: d06d beq.n 8001aa8 <HAL_DMA_Abort+0xe8>
{
return HAL_ERROR;
}
/* Check the DMA peripheral state */
if(hdma->State != HAL_DMA_STATE_BUSY)
80019cc: f894 3035 ldrb.w r3, [r4, #53] @ 0x35
80019d0: 2b02 cmp r3, #2
80019d2: d164 bne.n 8001a9e <HAL_DMA_Abort+0xde>
return HAL_ERROR;
}
else
{
/* Disable all the transfer interrupts */
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
80019d4: 6825 ldr r5, [r4, #0]
80019d6: 4606 mov r6, r0
80019d8: 4bad ldr r3, [pc, #692] @ (8001c90 <HAL_DMA_Abort+0x2d0>)
80019da: 429d cmp r5, r3
80019dc: d066 beq.n 8001aac <HAL_DMA_Abort+0xec>
80019de: 3318 adds r3, #24
80019e0: 429d cmp r5, r3
80019e2: d063 beq.n 8001aac <HAL_DMA_Abort+0xec>
80019e4: 3318 adds r3, #24
80019e6: 429d cmp r5, r3
80019e8: f000 80f3 beq.w 8001bd2 <HAL_DMA_Abort+0x212>
80019ec: 3318 adds r3, #24
80019ee: 429d cmp r5, r3
80019f0: f000 811a beq.w 8001c28 <HAL_DMA_Abort+0x268>
80019f4: 3318 adds r3, #24
80019f6: 429d cmp r5, r3
80019f8: f000 8125 beq.w 8001c46 <HAL_DMA_Abort+0x286>
80019fc: 3318 adds r3, #24
80019fe: 429d cmp r5, r3
8001a00: f000 80ff beq.w 8001c02 <HAL_DMA_Abort+0x242>
8001a04: 3318 adds r3, #24
8001a06: 429d cmp r5, r3
8001a08: f000 812e beq.w 8001c68 <HAL_DMA_Abort+0x2a8>
8001a0c: 3318 adds r3, #24
8001a0e: 429d cmp r5, r3
8001a10: f000 814a beq.w 8001ca8 <HAL_DMA_Abort+0x2e8>
8001a14: f503 7356 add.w r3, r3, #856 @ 0x358
8001a18: 429d cmp r5, r3
8001a1a: f000 8158 beq.w 8001cce <HAL_DMA_Abort+0x30e>
8001a1e: 3318 adds r3, #24
8001a20: 429d cmp r5, r3
8001a22: f000 8163 beq.w 8001cec <HAL_DMA_Abort+0x32c>
8001a26: 3318 adds r3, #24
8001a28: 429d cmp r5, r3
8001a2a: f000 816e beq.w 8001d0a <HAL_DMA_Abort+0x34a>
8001a2e: 3318 adds r3, #24
8001a30: 429d cmp r5, r3
8001a32: f000 816c beq.w 8001d0e <HAL_DMA_Abort+0x34e>
8001a36: 3318 adds r3, #24
8001a38: 429d cmp r5, r3
8001a3a: f000 816a beq.w 8001d12 <HAL_DMA_Abort+0x352>
8001a3e: 3318 adds r3, #24
8001a40: 429d cmp r5, r3
8001a42: f000 8168 beq.w 8001d16 <HAL_DMA_Abort+0x356>
8001a46: 3318 adds r3, #24
8001a48: 429d cmp r5, r3
8001a4a: f000 8168 beq.w 8001d1e <HAL_DMA_Abort+0x35e>
8001a4e: 3318 adds r3, #24
8001a50: 429d cmp r5, r3
8001a52: f000 8162 beq.w 8001d1a <HAL_DMA_Abort+0x35a>
enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef *)hdma->Instance)->CR));
}
else /* BDMA channel */
{
/* Disable DMA All Interrupts */
((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
8001a56: 682b ldr r3, [r5, #0]
enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR));
}
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
8001a58: 4a8e ldr r2, [pc, #568] @ (8001c94 <HAL_DMA_Abort+0x2d4>)
((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
8001a5a: f023 030e bic.w r3, r3, #14
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
8001a5e: 4295 cmp r5, r2
((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
8001a60: 602b str r3, [r5, #0]
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
8001a62: f000 80bf beq.w 8001be4 <HAL_DMA_Abort+0x224>
8001a66: 4b8c ldr r3, [pc, #560] @ (8001c98 <HAL_DMA_Abort+0x2d8>)
8001a68: 429d cmp r5, r3
8001a6a: f000 80bb beq.w 8001be4 <HAL_DMA_Abort+0x224>
8001a6e: 3314 adds r3, #20
8001a70: 429d cmp r5, r3
8001a72: f000 80b7 beq.w 8001be4 <HAL_DMA_Abort+0x224>
8001a76: 3314 adds r3, #20
8001a78: 429d cmp r5, r3
8001a7a: f000 80b3 beq.w 8001be4 <HAL_DMA_Abort+0x224>
8001a7e: 3314 adds r3, #20
8001a80: 429d cmp r5, r3
8001a82: f000 80af beq.w 8001be4 <HAL_DMA_Abort+0x224>
8001a86: 3314 adds r3, #20
8001a88: 429d cmp r5, r3
8001a8a: f000 80ab beq.w 8001be4 <HAL_DMA_Abort+0x224>
8001a8e: 3314 adds r3, #20
8001a90: 429d cmp r5, r3
8001a92: f000 80a7 beq.w 8001be4 <HAL_DMA_Abort+0x224>
8001a96: 3314 adds r3, #20
8001a98: 429d cmp r5, r3
8001a9a: d114 bne.n 8001ac6 <HAL_DMA_Abort+0x106>
8001a9c: e0a2 b.n 8001be4 <HAL_DMA_Abort+0x224>
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
8001a9e: 2280 movs r2, #128 @ 0x80
__HAL_UNLOCK(hdma);
8001aa0: 2300 movs r3, #0
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
8001aa2: 6562 str r2, [r4, #84] @ 0x54
__HAL_UNLOCK(hdma);
8001aa4: f884 3034 strb.w r3, [r4, #52] @ 0x34
return HAL_ERROR;
8001aa8: 2001 movs r0, #1
/* Process Unlocked */
__HAL_UNLOCK(hdma);
}
return HAL_OK;
}
8001aaa: bd70 pop {r4, r5, r6, pc}
((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
8001aac: 682b ldr r3, [r5, #0]
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
8001aae: 6e22 ldr r2, [r4, #96] @ 0x60
((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
8001ab0: f023 031e bic.w r3, r3, #30
8001ab4: 602b str r3, [r5, #0]
((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
8001ab6: 696b ldr r3, [r5, #20]
8001ab8: f023 0380 bic.w r3, r3, #128 @ 0x80
8001abc: 616b str r3, [r5, #20]
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
8001abe: 6813 ldr r3, [r2, #0]
8001ac0: f423 7380 bic.w r3, r3, #256 @ 0x100
8001ac4: 6013 str r3, [r2, #0]
__HAL_DMA_DISABLE(hdma);
8001ac6: 682b ldr r3, [r5, #0]
8001ac8: f023 0301 bic.w r3, r3, #1
8001acc: 602b str r3, [r5, #0]
8001ace: e005 b.n 8001adc <HAL_DMA_Abort+0x11c>
if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
8001ad0: f7ff f982 bl 8000dd8 <HAL_GetTick>
8001ad4: 1b83 subs r3, r0, r6
8001ad6: 2b05 cmp r3, #5
8001ad8: f200 808a bhi.w 8001bf0 <HAL_DMA_Abort+0x230>
while(((*enableRegister) & DMA_SxCR_EN) != 0U)
8001adc: 682b ldr r3, [r5, #0]
8001ade: 07db lsls r3, r3, #31
8001ae0: d4f6 bmi.n 8001ad0 <HAL_DMA_Abort+0x110>
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
8001ae2: 6823 ldr r3, [r4, #0]
8001ae4: 496a ldr r1, [pc, #424] @ (8001c90 <HAL_DMA_Abort+0x2d0>)
regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
8001ae6: 6de2 ldr r2, [r4, #92] @ 0x5c
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
8001ae8: 428b cmp r3, r1
regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
8001aea: 6da0 ldr r0, [r4, #88] @ 0x58
regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
8001aec: f002 021f and.w r2, r2, #31
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
8001af0: d05e beq.n 8001bb0 <HAL_DMA_Abort+0x1f0>
8001af2: 3118 adds r1, #24
8001af4: 428b cmp r3, r1
8001af6: d05b beq.n 8001bb0 <HAL_DMA_Abort+0x1f0>
8001af8: 3118 adds r1, #24
8001afa: 428b cmp r3, r1
8001afc: d058 beq.n 8001bb0 <HAL_DMA_Abort+0x1f0>
8001afe: 3118 adds r1, #24
8001b00: 428b cmp r3, r1
8001b02: d055 beq.n 8001bb0 <HAL_DMA_Abort+0x1f0>
8001b04: 3118 adds r1, #24
8001b06: 428b cmp r3, r1
8001b08: d052 beq.n 8001bb0 <HAL_DMA_Abort+0x1f0>
8001b0a: 3118 adds r1, #24
8001b0c: 428b cmp r3, r1
8001b0e: d04f beq.n 8001bb0 <HAL_DMA_Abort+0x1f0>
8001b10: 3118 adds r1, #24
8001b12: 428b cmp r3, r1
8001b14: d04c beq.n 8001bb0 <HAL_DMA_Abort+0x1f0>
8001b16: 3118 adds r1, #24
8001b18: 428b cmp r3, r1
8001b1a: d049 beq.n 8001bb0 <HAL_DMA_Abort+0x1f0>
8001b1c: f501 7156 add.w r1, r1, #856 @ 0x358
8001b20: 428b cmp r3, r1
8001b22: d045 beq.n 8001bb0 <HAL_DMA_Abort+0x1f0>
8001b24: 3118 adds r1, #24
8001b26: 428b cmp r3, r1
8001b28: d042 beq.n 8001bb0 <HAL_DMA_Abort+0x1f0>
8001b2a: 3118 adds r1, #24
8001b2c: 428b cmp r3, r1
8001b2e: d03f beq.n 8001bb0 <HAL_DMA_Abort+0x1f0>
8001b30: 3118 adds r1, #24
8001b32: 428b cmp r3, r1
8001b34: d03c beq.n 8001bb0 <HAL_DMA_Abort+0x1f0>
8001b36: 3118 adds r1, #24
8001b38: 428b cmp r3, r1
8001b3a: d039 beq.n 8001bb0 <HAL_DMA_Abort+0x1f0>
8001b3c: 3118 adds r1, #24
8001b3e: 428b cmp r3, r1
8001b40: d036 beq.n 8001bb0 <HAL_DMA_Abort+0x1f0>
8001b42: 3118 adds r1, #24
8001b44: 428b cmp r3, r1
8001b46: d033 beq.n 8001bb0 <HAL_DMA_Abort+0x1f0>
8001b48: 3118 adds r1, #24
8001b4a: 428b cmp r3, r1
8001b4c: d030 beq.n 8001bb0 <HAL_DMA_Abort+0x1f0>
regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
8001b4e: 2101 movs r1, #1
8001b50: 4091 lsls r1, r2
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
8001b52: 4a51 ldr r2, [pc, #324] @ (8001c98 <HAL_DMA_Abort+0x2d8>)
regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
8001b54: 6041 str r1, [r0, #4]
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
8001b56: 484f ldr r0, [pc, #316] @ (8001c94 <HAL_DMA_Abort+0x2d4>)
8001b58: 4950 ldr r1, [pc, #320] @ (8001c9c <HAL_DMA_Abort+0x2dc>)
8001b5a: 4283 cmp r3, r0
8001b5c: bf18 it ne
8001b5e: 4293 cmpne r3, r2
8001b60: f100 003c add.w r0, r0, #60 @ 0x3c
8001b64: bf0c ite eq
8001b66: 2201 moveq r2, #1
8001b68: 2200 movne r2, #0
8001b6a: 428b cmp r3, r1
8001b6c: bf08 it eq
8001b6e: f042 0201 orreq.w r2, r2, #1
8001b72: 3128 adds r1, #40 @ 0x28
8001b74: 4283 cmp r3, r0
8001b76: bf08 it eq
8001b78: f042 0201 orreq.w r2, r2, #1
8001b7c: 3028 adds r0, #40 @ 0x28
8001b7e: 428b cmp r3, r1
8001b80: bf08 it eq
8001b82: f042 0201 orreq.w r2, r2, #1
8001b86: 3128 adds r1, #40 @ 0x28
8001b88: 4283 cmp r3, r0
8001b8a: bf08 it eq
8001b8c: f042 0201 orreq.w r2, r2, #1
8001b90: 428b cmp r3, r1
8001b92: bf08 it eq
8001b94: f042 0201 orreq.w r2, r2, #1
8001b98: b96a cbnz r2, 8001bb6 <HAL_DMA_Abort+0x1f6>
8001b9a: 4a41 ldr r2, [pc, #260] @ (8001ca0 <HAL_DMA_Abort+0x2e0>)
8001b9c: 4293 cmp r3, r2
8001b9e: d00a beq.n 8001bb6 <HAL_DMA_Abort+0x1f6>
__HAL_UNLOCK(hdma);
8001ba0: 2300 movs r3, #0
hdma->State = HAL_DMA_STATE_READY;
8001ba2: 2201 movs r2, #1
return HAL_OK;
8001ba4: 4618 mov r0, r3
hdma->State = HAL_DMA_STATE_READY;
8001ba6: f884 2035 strb.w r2, [r4, #53] @ 0x35
__HAL_UNLOCK(hdma);
8001baa: f884 3034 strb.w r3, [r4, #52] @ 0x34
}
8001bae: bd70 pop {r4, r5, r6, pc}
regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
8001bb0: 233f movs r3, #63 @ 0x3f
8001bb2: 4093 lsls r3, r2
8001bb4: 6083 str r3, [r0, #8]
if(hdma->DMAmuxRequestGen != 0U)
8001bb6: 6ee3 ldr r3, [r4, #108] @ 0x6c
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
8001bb8: e9d4 2119 ldrd r2, r1, [r4, #100] @ 0x64
8001bbc: 6051 str r1, [r2, #4]
if(hdma->DMAmuxRequestGen != 0U)
8001bbe: 2b00 cmp r3, #0
8001bc0: d0ee beq.n 8001ba0 <HAL_DMA_Abort+0x1e0>
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
8001bc2: 681a ldr r2, [r3, #0]
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
8001bc4: e9d4 101c ldrd r1, r0, [r4, #112] @ 0x70
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
8001bc8: f422 7280 bic.w r2, r2, #256 @ 0x100
8001bcc: 601a str r2, [r3, #0]
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
8001bce: 6048 str r0, [r1, #4]
8001bd0: e7e6 b.n 8001ba0 <HAL_DMA_Abort+0x1e0>
((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
8001bd2: 4b34 ldr r3, [pc, #208] @ (8001ca4 <HAL_DMA_Abort+0x2e4>)
8001bd4: 6c1a ldr r2, [r3, #64] @ 0x40
8001bd6: f022 021e bic.w r2, r2, #30
8001bda: 641a str r2, [r3, #64] @ 0x40
((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
8001bdc: 6d5a ldr r2, [r3, #84] @ 0x54
8001bde: f022 0280 bic.w r2, r2, #128 @ 0x80
8001be2: 655a str r2, [r3, #84] @ 0x54
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
8001be4: 6e22 ldr r2, [r4, #96] @ 0x60
8001be6: 6813 ldr r3, [r2, #0]
8001be8: f423 7380 bic.w r3, r3, #256 @ 0x100
8001bec: 6013 str r3, [r2, #0]
__HAL_DMA_DISABLE(hdma);
8001bee: e76a b.n 8001ac6 <HAL_DMA_Abort+0x106>
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
8001bf0: 2120 movs r1, #32
hdma->State = HAL_DMA_STATE_ERROR;
8001bf2: 2203 movs r2, #3
__HAL_UNLOCK(hdma);
8001bf4: 2300 movs r3, #0
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
8001bf6: 6561 str r1, [r4, #84] @ 0x54
__HAL_UNLOCK(hdma);
8001bf8: f884 3034 strb.w r3, [r4, #52] @ 0x34
hdma->State = HAL_DMA_STATE_ERROR;
8001bfc: f884 2035 strb.w r2, [r4, #53] @ 0x35
return HAL_ERROR;
8001c00: e752 b.n 8001aa8 <HAL_DMA_Abort+0xe8>
((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
8001c02: 4b28 ldr r3, [pc, #160] @ (8001ca4 <HAL_DMA_Abort+0x2e4>)
8001c04: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88
8001c08: f022 021e bic.w r2, r2, #30
8001c0c: f8c3 2088 str.w r2, [r3, #136] @ 0x88
((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
8001c10: f8d3 209c ldr.w r2, [r3, #156] @ 0x9c
8001c14: f022 0280 bic.w r2, r2, #128 @ 0x80
8001c18: f8c3 209c str.w r2, [r3, #156] @ 0x9c
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
8001c1c: 6e22 ldr r2, [r4, #96] @ 0x60
8001c1e: 6813 ldr r3, [r2, #0]
8001c20: f423 7380 bic.w r3, r3, #256 @ 0x100
8001c24: 6013 str r3, [r2, #0]
__HAL_DMA_DISABLE(hdma);
8001c26: e74e b.n 8001ac6 <HAL_DMA_Abort+0x106>
((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
8001c28: 4b1e ldr r3, [pc, #120] @ (8001ca4 <HAL_DMA_Abort+0x2e4>)
8001c2a: 6d9a ldr r2, [r3, #88] @ 0x58
8001c2c: f022 021e bic.w r2, r2, #30
8001c30: 659a str r2, [r3, #88] @ 0x58
((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
8001c32: 6eda ldr r2, [r3, #108] @ 0x6c
8001c34: f022 0280 bic.w r2, r2, #128 @ 0x80
8001c38: 66da str r2, [r3, #108] @ 0x6c
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
8001c3a: 6e22 ldr r2, [r4, #96] @ 0x60
8001c3c: 6813 ldr r3, [r2, #0]
8001c3e: f423 7380 bic.w r3, r3, #256 @ 0x100
8001c42: 6013 str r3, [r2, #0]
__HAL_DMA_DISABLE(hdma);
8001c44: e73f b.n 8001ac6 <HAL_DMA_Abort+0x106>
((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
8001c46: 4b17 ldr r3, [pc, #92] @ (8001ca4 <HAL_DMA_Abort+0x2e4>)
8001c48: 6f1a ldr r2, [r3, #112] @ 0x70
8001c4a: f022 021e bic.w r2, r2, #30
8001c4e: 671a str r2, [r3, #112] @ 0x70
((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
8001c50: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84
8001c54: f022 0280 bic.w r2, r2, #128 @ 0x80
8001c58: f8c3 2084 str.w r2, [r3, #132] @ 0x84
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
8001c5c: 6e22 ldr r2, [r4, #96] @ 0x60
8001c5e: 6813 ldr r3, [r2, #0]
8001c60: f423 7380 bic.w r3, r3, #256 @ 0x100
8001c64: 6013 str r3, [r2, #0]
__HAL_DMA_DISABLE(hdma);
8001c66: e72e b.n 8001ac6 <HAL_DMA_Abort+0x106>
((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
8001c68: 4b0e ldr r3, [pc, #56] @ (8001ca4 <HAL_DMA_Abort+0x2e4>)
8001c6a: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0
8001c6e: f022 021e bic.w r2, r2, #30
8001c72: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0
((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
8001c76: f8d3 20b4 ldr.w r2, [r3, #180] @ 0xb4
8001c7a: f022 0280 bic.w r2, r2, #128 @ 0x80
8001c7e: f8c3 20b4 str.w r2, [r3, #180] @ 0xb4
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
8001c82: 6e22 ldr r2, [r4, #96] @ 0x60
8001c84: 6813 ldr r3, [r2, #0]
8001c86: f423 7380 bic.w r3, r3, #256 @ 0x100
8001c8a: 6013 str r3, [r2, #0]
__HAL_DMA_DISABLE(hdma);
8001c8c: e71b b.n 8001ac6 <HAL_DMA_Abort+0x106>
8001c8e: bf00 nop
8001c90: 40020010 .word 0x40020010
8001c94: 58025408 .word 0x58025408
8001c98: 5802541c .word 0x5802541c
8001c9c: 58025430 .word 0x58025430
8001ca0: 58025494 .word 0x58025494
8001ca4: 40020000 .word 0x40020000
((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
8001ca8: 4b1e ldr r3, [pc, #120] @ (8001d24 <HAL_DMA_Abort+0x364>)
8001caa: f8d3 20b8 ldr.w r2, [r3, #184] @ 0xb8
8001cae: f022 021e bic.w r2, r2, #30
8001cb2: f8c3 20b8 str.w r2, [r3, #184] @ 0xb8
((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
8001cb6: f8d3 20cc ldr.w r2, [r3, #204] @ 0xcc
8001cba: f022 0280 bic.w r2, r2, #128 @ 0x80
8001cbe: f8c3 20cc str.w r2, [r3, #204] @ 0xcc
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
8001cc2: 6e22 ldr r2, [r4, #96] @ 0x60
8001cc4: 6813 ldr r3, [r2, #0]
8001cc6: f423 7380 bic.w r3, r3, #256 @ 0x100
8001cca: 6013 str r3, [r2, #0]
__HAL_DMA_DISABLE(hdma);
8001ccc: e6fb b.n 8001ac6 <HAL_DMA_Abort+0x106>
((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
8001cce: 4b16 ldr r3, [pc, #88] @ (8001d28 <HAL_DMA_Abort+0x368>)
8001cd0: 691a ldr r2, [r3, #16]
8001cd2: f022 021e bic.w r2, r2, #30
8001cd6: 611a str r2, [r3, #16]
((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
8001cd8: 6a5a ldr r2, [r3, #36] @ 0x24
8001cda: f022 0280 bic.w r2, r2, #128 @ 0x80
8001cde: 625a str r2, [r3, #36] @ 0x24
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
8001ce0: 6e22 ldr r2, [r4, #96] @ 0x60
8001ce2: 6813 ldr r3, [r2, #0]
8001ce4: f423 7380 bic.w r3, r3, #256 @ 0x100
8001ce8: 6013 str r3, [r2, #0]
__HAL_DMA_DISABLE(hdma);
8001cea: e6ec b.n 8001ac6 <HAL_DMA_Abort+0x106>
((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
8001cec: 4b0e ldr r3, [pc, #56] @ (8001d28 <HAL_DMA_Abort+0x368>)
8001cee: 6a9a ldr r2, [r3, #40] @ 0x28
8001cf0: f022 021e bic.w r2, r2, #30
8001cf4: 629a str r2, [r3, #40] @ 0x28
((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
8001cf6: 6bda ldr r2, [r3, #60] @ 0x3c
8001cf8: f022 0280 bic.w r2, r2, #128 @ 0x80
8001cfc: 63da str r2, [r3, #60] @ 0x3c
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
8001cfe: 6e22 ldr r2, [r4, #96] @ 0x60
8001d00: 6813 ldr r3, [r2, #0]
8001d02: f423 7380 bic.w r3, r3, #256 @ 0x100
8001d06: 6013 str r3, [r2, #0]
__HAL_DMA_DISABLE(hdma);
8001d08: e6dd b.n 8001ac6 <HAL_DMA_Abort+0x106>
((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
8001d0a: 4b07 ldr r3, [pc, #28] @ (8001d28 <HAL_DMA_Abort+0x368>)
8001d0c: e762 b.n 8001bd4 <HAL_DMA_Abort+0x214>
8001d0e: 4b06 ldr r3, [pc, #24] @ (8001d28 <HAL_DMA_Abort+0x368>)
8001d10: e78b b.n 8001c2a <HAL_DMA_Abort+0x26a>
8001d12: 4b05 ldr r3, [pc, #20] @ (8001d28 <HAL_DMA_Abort+0x368>)
8001d14: e798 b.n 8001c48 <HAL_DMA_Abort+0x288>
8001d16: 4b04 ldr r3, [pc, #16] @ (8001d28 <HAL_DMA_Abort+0x368>)
8001d18: e774 b.n 8001c04 <HAL_DMA_Abort+0x244>
8001d1a: 4b03 ldr r3, [pc, #12] @ (8001d28 <HAL_DMA_Abort+0x368>)
8001d1c: e7c5 b.n 8001caa <HAL_DMA_Abort+0x2ea>
8001d1e: 4b02 ldr r3, [pc, #8] @ (8001d28 <HAL_DMA_Abort+0x368>)
8001d20: e7a3 b.n 8001c6a <HAL_DMA_Abort+0x2aa>
8001d22: bf00 nop
8001d24: 40020000 .word 0x40020000
8001d28: 40020400 .word 0x40020400
08001d2c <HAL_DMA_Abort_IT>:
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
BDMA_Base_Registers *regs_bdma;
/* Check the DMA peripheral handle */
if(hdma == NULL)
8001d2c: 2800 cmp r0, #0
8001d2e: d062 beq.n 8001df6 <HAL_DMA_Abort_IT+0xca>
{
8001d30: b538 push {r3, r4, r5, lr}
{
return HAL_ERROR;
}
if(hdma->State != HAL_DMA_STATE_BUSY)
8001d32: f890 3035 ldrb.w r3, [r0, #53] @ 0x35
8001d36: 2b02 cmp r3, #2
8001d38: d159 bne.n 8001dee <HAL_DMA_Abort_IT+0xc2>
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
return HAL_ERROR;
}
else
{
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
8001d3a: 6802 ldr r2, [r0, #0]
8001d3c: 4b57 ldr r3, [pc, #348] @ (8001e9c <HAL_DMA_Abort_IT+0x170>)
8001d3e: 4c58 ldr r4, [pc, #352] @ (8001ea0 <HAL_DMA_Abort_IT+0x174>)
8001d40: 4958 ldr r1, [pc, #352] @ (8001ea4 <HAL_DMA_Abort_IT+0x178>)
8001d42: 42a2 cmp r2, r4
8001d44: bf18 it ne
8001d46: 429a cmpne r2, r3
8001d48: f104 0430 add.w r4, r4, #48 @ 0x30
8001d4c: bf0c ite eq
8001d4e: 2301 moveq r3, #1
8001d50: 2300 movne r3, #0
8001d52: 428a cmp r2, r1
8001d54: bf08 it eq
8001d56: f043 0301 orreq.w r3, r3, #1
8001d5a: 3130 adds r1, #48 @ 0x30
8001d5c: 42a2 cmp r2, r4
8001d5e: bf08 it eq
8001d60: f043 0301 orreq.w r3, r3, #1
8001d64: 3430 adds r4, #48 @ 0x30
8001d66: 428a cmp r2, r1
8001d68: bf08 it eq
8001d6a: f043 0301 orreq.w r3, r3, #1
8001d6e: 3130 adds r1, #48 @ 0x30
8001d70: 42a2 cmp r2, r4
8001d72: bf08 it eq
8001d74: f043 0301 orreq.w r3, r3, #1
8001d78: 3430 adds r4, #48 @ 0x30
8001d7a: 428a cmp r2, r1
8001d7c: bf08 it eq
8001d7e: f043 0301 orreq.w r3, r3, #1
8001d82: f501 715c add.w r1, r1, #880 @ 0x370
8001d86: 42a2 cmp r2, r4
8001d88: bf08 it eq
8001d8a: f043 0301 orreq.w r3, r3, #1
8001d8e: f504 745c add.w r4, r4, #880 @ 0x370
8001d92: 428a cmp r2, r1
8001d94: bf08 it eq
8001d96: f043 0301 orreq.w r3, r3, #1
8001d9a: 3130 adds r1, #48 @ 0x30
8001d9c: 42a2 cmp r2, r4
8001d9e: bf08 it eq
8001da0: f043 0301 orreq.w r3, r3, #1
8001da4: 3430 adds r4, #48 @ 0x30
8001da6: 428a cmp r2, r1
8001da8: bf08 it eq
8001daa: f043 0301 orreq.w r3, r3, #1
8001dae: 3130 adds r1, #48 @ 0x30
8001db0: 42a2 cmp r2, r4
8001db2: bf08 it eq
8001db4: f043 0301 orreq.w r3, r3, #1
8001db8: 3430 adds r4, #48 @ 0x30
8001dba: 428a cmp r2, r1
8001dbc: bf08 it eq
8001dbe: f043 0301 orreq.w r3, r3, #1
8001dc2: 3130 adds r1, #48 @ 0x30
8001dc4: 42a2 cmp r2, r4
8001dc6: bf08 it eq
8001dc8: f043 0301 orreq.w r3, r3, #1
8001dcc: 428a cmp r2, r1
8001dce: bf08 it eq
8001dd0: f043 0301 orreq.w r3, r3, #1
8001dd4: b913 cbnz r3, 8001ddc <HAL_DMA_Abort_IT+0xb0>
8001dd6: 4b34 ldr r3, [pc, #208] @ (8001ea8 <HAL_DMA_Abort_IT+0x17c>)
8001dd8: 429a cmp r2, r3
8001dda: d10e bne.n 8001dfa <HAL_DMA_Abort_IT+0xce>
{
/* Set Abort State */
hdma->State = HAL_DMA_STATE_ABORT;
8001ddc: 2304 movs r3, #4
8001dde: f880 3035 strb.w r3, [r0, #53] @ 0x35
/* Disable the stream */
__HAL_DMA_DISABLE(hdma);
8001de2: 6813 ldr r3, [r2, #0]
8001de4: f023 0301 bic.w r3, r3, #1
8001de8: 6013 str r3, [r2, #0]
hdma->XferAbortCallback(hdma);
}
}
}
return HAL_OK;
8001dea: 2000 movs r0, #0
}
8001dec: bd38 pop {r3, r4, r5, pc}
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
8001dee: 2380 movs r3, #128 @ 0x80
8001df0: 6543 str r3, [r0, #84] @ 0x54
return HAL_ERROR;
8001df2: 2001 movs r0, #1
}
8001df4: bd38 pop {r3, r4, r5, pc}
return HAL_ERROR;
8001df6: 2001 movs r0, #1
}
8001df8: 4770 bx lr
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
8001dfa: 4b2c ldr r3, [pc, #176] @ (8001eac <HAL_DMA_Abort_IT+0x180>)
8001dfc: 4d2c ldr r5, [pc, #176] @ (8001eb0 <HAL_DMA_Abort_IT+0x184>)
((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
8001dfe: 6811 ldr r1, [r2, #0]
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
8001e00: 42aa cmp r2, r5
8001e02: bf18 it ne
8001e04: 429a cmpne r2, r3
8001e06: 4c2b ldr r4, [pc, #172] @ (8001eb4 <HAL_DMA_Abort_IT+0x188>)
((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
8001e08: f021 010e bic.w r1, r1, #14
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
8001e0c: f105 053c add.w r5, r5, #60 @ 0x3c
8001e10: bf0c ite eq
8001e12: 2301 moveq r3, #1
8001e14: 2300 movne r3, #0
((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
8001e16: 6011 str r1, [r2, #0]
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
8001e18: 42a2 cmp r2, r4
8001e1a: bf08 it eq
8001e1c: f043 0301 orreq.w r3, r3, #1
__HAL_DMA_DISABLE(hdma);
8001e20: 6811 ldr r1, [r2, #0]
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
8001e22: 3428 adds r4, #40 @ 0x28
8001e24: 42aa cmp r2, r5
8001e26: bf08 it eq
8001e28: f043 0301 orreq.w r3, r3, #1
__HAL_DMA_DISABLE(hdma);
8001e2c: f021 0101 bic.w r1, r1, #1
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
8001e30: 42a2 cmp r2, r4
8001e32: bf08 it eq
8001e34: f043 0301 orreq.w r3, r3, #1
8001e38: 3414 adds r4, #20
__HAL_DMA_DISABLE(hdma);
8001e3a: 6011 str r1, [r2, #0]
if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
8001e3c: 42a2 cmp r2, r4
8001e3e: bf08 it eq
8001e40: f043 0301 orreq.w r3, r3, #1
8001e44: 491c ldr r1, [pc, #112] @ (8001eb8 <HAL_DMA_Abort_IT+0x18c>)
8001e46: 428a cmp r2, r1
8001e48: bf08 it eq
8001e4a: f043 0301 orreq.w r3, r3, #1
8001e4e: b913 cbnz r3, 8001e56 <HAL_DMA_Abort_IT+0x12a>
8001e50: 4b1a ldr r3, [pc, #104] @ (8001ebc <HAL_DMA_Abort_IT+0x190>)
8001e52: 429a cmp r2, r3
8001e54: d117 bne.n 8001e86 <HAL_DMA_Abort_IT+0x15a>
regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
8001e56: 2301 movs r3, #1
regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
8001e58: 6d85 ldr r5, [r0, #88] @ 0x58
regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
8001e5a: e9d0 1417 ldrd r1, r4, [r0, #92] @ 0x5c
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
8001e5e: 6822 ldr r2, [r4, #0]
regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
8001e60: f001 011f and.w r1, r1, #31
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
8001e64: f422 7280 bic.w r2, r2, #256 @ 0x100
regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
8001e68: 408b lsls r3, r1
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
8001e6a: 6022 str r2, [r4, #0]
regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
8001e6c: 606b str r3, [r5, #4]
if(hdma->DMAmuxRequestGen != 0U)
8001e6e: 6ec3 ldr r3, [r0, #108] @ 0x6c
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
8001e70: e9d0 2119 ldrd r2, r1, [r0, #100] @ 0x64
8001e74: 6051 str r1, [r2, #4]
if(hdma->DMAmuxRequestGen != 0U)
8001e76: b133 cbz r3, 8001e86 <HAL_DMA_Abort_IT+0x15a>
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
8001e78: 681a ldr r2, [r3, #0]
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
8001e7a: e9d0 141c ldrd r1, r4, [r0, #112] @ 0x70
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
8001e7e: f422 7280 bic.w r2, r2, #256 @ 0x100
8001e82: 601a str r2, [r3, #0]
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
8001e84: 604c str r4, [r1, #4]
hdma->State = HAL_DMA_STATE_READY;
8001e86: 2101 movs r1, #1
__HAL_UNLOCK(hdma);
8001e88: 2200 movs r2, #0
if(hdma->XferAbortCallback != NULL)
8001e8a: 6d03 ldr r3, [r0, #80] @ 0x50
hdma->State = HAL_DMA_STATE_READY;
8001e8c: f880 1035 strb.w r1, [r0, #53] @ 0x35
__HAL_UNLOCK(hdma);
8001e90: f880 2034 strb.w r2, [r0, #52] @ 0x34
if(hdma->XferAbortCallback != NULL)
8001e94: 2b00 cmp r3, #0
8001e96: d0a8 beq.n 8001dea <HAL_DMA_Abort_IT+0xbe>
hdma->XferAbortCallback(hdma);
8001e98: 4798 blx r3
8001e9a: e7a6 b.n 8001dea <HAL_DMA_Abort_IT+0xbe>
8001e9c: 40020010 .word 0x40020010
8001ea0: 40020028 .word 0x40020028
8001ea4: 40020040 .word 0x40020040
8001ea8: 400204b8 .word 0x400204b8
8001eac: 5802541c .word 0x5802541c
8001eb0: 58025408 .word 0x58025408
8001eb4: 58025430 .word 0x58025430
8001eb8: 58025480 .word 0x58025480
8001ebc: 58025494 .word 0x58025494
08001ec0 <HAL_GPIO_Init>:
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00U)
8001ec0: 680b ldr r3, [r1, #0]
8001ec2: 2b00 cmp r3, #0
8001ec4: f000 81dc beq.w 8002280 <HAL_GPIO_Init+0x3c0>
8001ec8: 4ab4 ldr r2, [pc, #720] @ (800219c <HAL_GPIO_Init+0x2dc>)
8001eca: 4290 cmp r0, r2
uint32_t position = 0x00U;
8001ecc: f04f 0200 mov.w r2, #0
{
8001ed0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1UL << position);
8001ed4: f04f 0b01 mov.w fp, #1
{
8001ed8: b085 sub sp, #20
8001eda: f000 8105 beq.w 80020e8 <HAL_GPIO_Init+0x228>
temp &= ~(0x0FUL << (4U * (position & 0x03U)));
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
SYSCFG->EXTICR[position >> 2U] = temp;
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
8001ede: f04f 4eb0 mov.w lr, #1476395008 @ 0x58000000
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
8001ee2: 9300 str r3, [sp, #0]
iocurrent = (GPIO_Init->Pin) & (1UL << position);
8001ee4: fa0b fc02 lsl.w ip, fp, r2
if (iocurrent != 0x00U)
8001ee8: 9b00 ldr r3, [sp, #0]
8001eea: ea1c 0a03 ands.w sl, ip, r3
8001eee: f000 814b beq.w 8002188 <HAL_GPIO_Init+0x2c8>
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8001ef2: 684d ldr r5, [r1, #4]
8001ef4: 0054 lsls r4, r2, #1
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
8001ef6: 2303 movs r3, #3
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8001ef8: f005 0703 and.w r7, r5, #3
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
8001efc: fa03 f604 lsl.w r6, r3, r4
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8001f00: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
8001f04: 43f6 mvns r6, r6
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8001f06: f1b8 0f01 cmp.w r8, #1
8001f0a: f240 815d bls.w 80021c8 <HAL_GPIO_Init+0x308>
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8001f0e: 2f03 cmp r7, #3
8001f10: f040 81cf bne.w 80022b2 <HAL_GPIO_Init+0x3f2>
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
8001f14: fa07 f404 lsl.w r4, r7, r4
temp = GPIOx->MODER;
8001f18: 6807 ldr r7, [r0, #0]
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
8001f1a: f415 3f40 tst.w r5, #196608 @ 0x30000
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
8001f1e: ea06 0607 and.w r6, r6, r7
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
8001f22: ea44 0406 orr.w r4, r4, r6
GPIOx->MODER = temp;
8001f26: 6004 str r4, [r0, #0]
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
8001f28: f000 812e beq.w 8002188 <HAL_GPIO_Init+0x2c8>
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001f2c: 4e9c ldr r6, [pc, #624] @ (80021a0 <HAL_GPIO_Init+0x2e0>)
temp &= ~(0x0FUL << (4U * (position & 0x03U)));
8001f2e: f002 0703 and.w r7, r2, #3
8001f32: 230f movs r3, #15
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001f34: f8d6 40f4 ldr.w r4, [r6, #244] @ 0xf4
temp &= ~(0x0FUL << (4U * (position & 0x03U)));
8001f38: 00bf lsls r7, r7, #2
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001f3a: f044 0402 orr.w r4, r4, #2
temp &= ~(0x0FUL << (4U * (position & 0x03U)));
8001f3e: fa03 fc07 lsl.w ip, r3, r7
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
8001f42: 4b98 ldr r3, [pc, #608] @ (80021a4 <HAL_GPIO_Init+0x2e4>)
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001f44: f8c6 40f4 str.w r4, [r6, #244] @ 0xf4
8001f48: f8d6 40f4 ldr.w r4, [r6, #244] @ 0xf4
8001f4c: f022 0603 bic.w r6, r2, #3
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
8001f50: 4298 cmp r0, r3
8001f52: f106 46b0 add.w r6, r6, #1476395008 @ 0x58000000
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001f56: f004 0402 and.w r4, r4, #2
8001f5a: f506 6680 add.w r6, r6, #1024 @ 0x400
8001f5e: 9403 str r4, [sp, #12]
8001f60: 9c03 ldr r4, [sp, #12]
temp = SYSCFG->EXTICR[position >> 2U];
8001f62: 68b4 ldr r4, [r6, #8]
temp &= ~(0x0FUL << (4U * (position & 0x03U)));
8001f64: ea24 040c bic.w r4, r4, ip
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
8001f68: f000 8178 beq.w 800225c <HAL_GPIO_Init+0x39c>
8001f6c: 4b8e ldr r3, [pc, #568] @ (80021a8 <HAL_GPIO_Init+0x2e8>)
8001f6e: 4298 cmp r0, r3
8001f70: f000 80de beq.w 8002130 <HAL_GPIO_Init+0x270>
8001f74: f8df c234 ldr.w ip, [pc, #564] @ 80021ac <HAL_GPIO_Init+0x2ec>
8001f78: 4560 cmp r0, ip
8001f7a: f000 817b beq.w 8002274 <HAL_GPIO_Init+0x3b4>
8001f7e: f8df c230 ldr.w ip, [pc, #560] @ 80021b0 <HAL_GPIO_Init+0x2f0>
8001f82: 4560 cmp r0, ip
8001f84: f000 817d beq.w 8002282 <HAL_GPIO_Init+0x3c2>
8001f88: f8df c228 ldr.w ip, [pc, #552] @ 80021b4 <HAL_GPIO_Init+0x2f4>
8001f8c: 4560 cmp r0, ip
8001f8e: f000 816b beq.w 8002268 <HAL_GPIO_Init+0x3a8>
8001f92: f8df c224 ldr.w ip, [pc, #548] @ 80021b8 <HAL_GPIO_Init+0x2f8>
8001f96: 4560 cmp r0, ip
8001f98: f000 8179 beq.w 800228e <HAL_GPIO_Init+0x3ce>
8001f9c: f8df c21c ldr.w ip, [pc, #540] @ 80021bc <HAL_GPIO_Init+0x2fc>
8001fa0: 4560 cmp r0, ip
8001fa2: f000 817a beq.w 800229a <HAL_GPIO_Init+0x3da>
8001fa6: f8df c218 ldr.w ip, [pc, #536] @ 80021c0 <HAL_GPIO_Init+0x300>
8001faa: 4560 cmp r0, ip
8001fac: f000 817b beq.w 80022a6 <HAL_GPIO_Init+0x3e6>
8001fb0: f8df c210 ldr.w ip, [pc, #528] @ 80021c4 <HAL_GPIO_Init+0x304>
8001fb4: 4560 cmp r0, ip
8001fb6: bf0c ite eq
8001fb8: f04f 0c09 moveq.w ip, #9
8001fbc: f04f 0c0a movne.w ip, #10
8001fc0: fa0c f707 lsl.w r7, ip, r7
8001fc4: 433c orrs r4, r7
8001fc6: e0b8 b.n 800213a <HAL_GPIO_Init+0x27a>
temp = GPIOx->OSPEEDR;
8001fc8: f8d0 9008 ldr.w r9, [r0, #8]
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8001fcc: 2c02 cmp r4, #2
temp |= (GPIO_Init->Speed << (position * 2U));
8001fce: 68ce ldr r6, [r1, #12]
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
8001fd0: ea0a 0909 and.w r9, sl, r9
temp |= (GPIO_Init->Speed << (position * 2U));
8001fd4: fa06 f807 lsl.w r8, r6, r7
8001fd8: ea48 0809 orr.w r8, r8, r9
GPIOx->OSPEEDR = temp;
8001fdc: f8c0 8008 str.w r8, [r0, #8]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8001fe0: f3c5 1800 ubfx r8, r5, #4, #1
temp = GPIOx->OTYPER;
8001fe4: f8d0 9004 ldr.w r9, [r0, #4]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8001fe8: fa08 f802 lsl.w r8, r8, r2
temp &= ~(GPIO_OTYPER_OT0 << position) ;
8001fec: ea29 0e0e bic.w lr, r9, lr
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8001ff0: ea48 0e0e orr.w lr, r8, lr
GPIOx->OTYPER = temp;
8001ff4: f8c0 e004 str.w lr, [r0, #4]
temp = GPIOx->PUPDR;
8001ff8: f8d0 800c ldr.w r8, [r0, #12]
temp |= ((GPIO_Init->Pull) << (position * 2U));
8001ffc: 688e ldr r6, [r1, #8]
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
8001ffe: ea0a 0808 and.w r8, sl, r8
temp |= ((GPIO_Init->Pull) << (position * 2U));
8002002: fa06 fe07 lsl.w lr, r6, r7
8002006: ea4e 0e08 orr.w lr, lr, r8
GPIOx->PUPDR = temp;
800200a: f8c0 e00c str.w lr, [r0, #12]
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
800200e: d117 bne.n 8002040 <HAL_GPIO_Init+0x180>
temp &= ~(0xFU << ((position & 0x07U) * 4U));
8002010: f002 0e07 and.w lr, r2, #7
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
8002014: 690e ldr r6, [r1, #16]
temp = GPIOx->AFR[position >> 3U];
8002016: ea4f 08d2 mov.w r8, r2, lsr #3
temp &= ~(0xFU << ((position & 0x07U) * 4U));
800201a: ea4f 0e8e mov.w lr, lr, lsl #2
800201e: eb00 0888 add.w r8, r0, r8, lsl #2
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
8002022: fa06 f60e lsl.w r6, r6, lr
temp = GPIOx->AFR[position >> 3U];
8002026: f8d8 9020 ldr.w r9, [r8, #32]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
800202a: 9600 str r6, [sp, #0]
temp &= ~(0xFU << ((position & 0x07U) * 4U));
800202c: 260f movs r6, #15
800202e: fa06 fe0e lsl.w lr, r6, lr
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
8002032: 9e00 ldr r6, [sp, #0]
temp &= ~(0xFU << ((position & 0x07U) * 4U));
8002034: ea29 090e bic.w r9, r9, lr
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
8002038: ea46 0e09 orr.w lr, r6, r9
GPIOx->AFR[position >> 3U] = temp;
800203c: f8c8 e020 str.w lr, [r8, #32]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
8002040: 40bc lsls r4, r7
temp = GPIOx->MODER;
8002042: 6807 ldr r7, [r0, #0]
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
8002044: f415 3f40 tst.w r5, #196608 @ 0x30000
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
8002048: ea07 070a and.w r7, r7, sl
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
800204c: ea44 0407 orr.w r4, r4, r7
GPIOx->MODER = temp;
8002050: 6004 str r4, [r0, #0]
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
8002052: d045 beq.n 80020e0 <HAL_GPIO_Init+0x220>
__HAL_RCC_SYSCFG_CLK_ENABLE();
8002054: 4f52 ldr r7, [pc, #328] @ (80021a0 <HAL_GPIO_Init+0x2e0>)
temp &= ~(0x0FUL << (4U * (position & 0x03U)));
8002056: 260f movs r6, #15
__HAL_RCC_SYSCFG_CLK_ENABLE();
8002058: f8d7 40f4 ldr.w r4, [r7, #244] @ 0xf4
800205c: f044 0402 orr.w r4, r4, #2
8002060: f8c7 40f4 str.w r4, [r7, #244] @ 0xf4
8002064: f8d7 40f4 ldr.w r4, [r7, #244] @ 0xf4
8002068: f022 0703 bic.w r7, r2, #3
800206c: f004 0402 and.w r4, r4, #2
8002070: f107 47b0 add.w r7, r7, #1476395008 @ 0x58000000
8002074: 9403 str r4, [sp, #12]
8002076: f507 6780 add.w r7, r7, #1024 @ 0x400
800207a: 9c03 ldr r4, [sp, #12]
temp &= ~(0x0FUL << (4U * (position & 0x03U)));
800207c: f002 0403 and.w r4, r2, #3
temp = SYSCFG->EXTICR[position >> 2U];
8002080: f8d7 e008 ldr.w lr, [r7, #8]
temp &= ~(0x0FUL << (4U * (position & 0x03U)));
8002084: 00a4 lsls r4, r4, #2
8002086: fa06 f404 lsl.w r4, r6, r4
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
800208a: 02ee lsls r6, r5, #11
temp &= ~(0x0FUL << (4U * (position & 0x03U)));
800208c: ea2e 0404 bic.w r4, lr, r4
SYSCFG->EXTICR[position >> 2U] = temp;
8002090: 60bc str r4, [r7, #8]
temp = EXTI->RTSR1;
8002092: f04f 44b0 mov.w r4, #1476395008 @ 0x58000000
temp &= ~(iocurrent);
8002096: ea6f 070c mvn.w r7, ip
temp = EXTI->RTSR1;
800209a: 6824 ldr r4, [r4, #0]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
800209c: f100 80d2 bmi.w 8002244 <HAL_GPIO_Init+0x384>
temp &= ~(iocurrent);
80020a0: 403c ands r4, r7
{
temp |= iocurrent;
}
EXTI->RTSR1 = temp;
80020a2: f04f 46b0 mov.w r6, #1476395008 @ 0x58000000
80020a6: 6034 str r4, [r6, #0]
temp = EXTI->FTSR1;
80020a8: 6874 ldr r4, [r6, #4]
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
80020aa: 02ae lsls r6, r5, #10
80020ac: f100 80d3 bmi.w 8002256 <HAL_GPIO_Init+0x396>
temp &= ~(iocurrent);
80020b0: 403c ands r4, r7
{
temp |= iocurrent;
}
EXTI->FTSR1 = temp;
80020b2: f04f 46b0 mov.w r6, #1476395008 @ 0x58000000
80020b6: 6074 str r4, [r6, #4]
temp = EXTI_CurrentCPU->EMR1;
80020b8: f8d6 4084 ldr.w r4, [r6, #132] @ 0x84
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
80020bc: 03ae lsls r6, r5, #14
80020be: f100 80c7 bmi.w 8002250 <HAL_GPIO_Init+0x390>
temp &= ~(iocurrent);
80020c2: 403c ands r4, r7
{
temp |= iocurrent;
}
EXTI_CurrentCPU->EMR1 = temp;
80020c4: f04f 46b0 mov.w r6, #1476395008 @ 0x58000000
/* Clear EXTI line configuration */
temp = EXTI_CurrentCPU->IMR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
80020c8: 03ed lsls r5, r5, #15
EXTI_CurrentCPU->EMR1 = temp;
80020ca: f8c6 4084 str.w r4, [r6, #132] @ 0x84
temp = EXTI_CurrentCPU->IMR1;
80020ce: f8d6 4080 ldr.w r4, [r6, #128] @ 0x80
if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
80020d2: f100 80ba bmi.w 800224a <HAL_GPIO_Init+0x38a>
temp &= ~(iocurrent);
80020d6: 403c ands r4, r7
{
temp |= iocurrent;
}
EXTI_CurrentCPU->IMR1 = temp;
80020d8: f04f 45b0 mov.w r5, #1476395008 @ 0x58000000
80020dc: f8c5 4080 str.w r4, [r5, #128] @ 0x80
}
}
position++;
80020e0: 3201 adds r2, #1
while (((GPIO_Init->Pin) >> position) != 0x00U)
80020e2: fa33 f402 lsrs.w r4, r3, r2
80020e6: d055 beq.n 8002194 <HAL_GPIO_Init+0x2d4>
iocurrent = (GPIO_Init->Pin) & (1UL << position);
80020e8: fa0b fe02 lsl.w lr, fp, r2
if (iocurrent != 0x00U)
80020ec: ea13 0c0e ands.w ip, r3, lr
80020f0: d0f6 beq.n 80020e0 <HAL_GPIO_Init+0x220>
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
80020f2: 684d ldr r5, [r1, #4]
80020f4: 0057 lsls r7, r2, #1
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
80020f6: 2603 movs r6, #3
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
80020f8: f005 0403 and.w r4, r5, #3
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
80020fc: fa06 f807 lsl.w r8, r6, r7
8002100: ea6f 0a08 mvn.w sl, r8
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8002104: f104 38ff add.w r8, r4, #4294967295 @ 0xffffffff
8002108: f1b8 0f01 cmp.w r8, #1
800210c: f67f af5c bls.w 8001fc8 <HAL_GPIO_Init+0x108>
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8002110: 2c03 cmp r4, #3
8002112: d095 beq.n 8002040 <HAL_GPIO_Init+0x180>
temp = GPIOx->PUPDR;
8002114: f8df 8084 ldr.w r8, [pc, #132] @ 800219c <HAL_GPIO_Init+0x2dc>
temp |= ((GPIO_Init->Pull) << (position * 2U));
8002118: 688e ldr r6, [r1, #8]
temp = GPIOx->PUPDR;
800211a: f8d8 900c ldr.w r9, [r8, #12]
temp |= ((GPIO_Init->Pull) << (position * 2U));
800211e: fa06 fe07 lsl.w lr, r6, r7
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
8002122: ea0a 0909 and.w r9, sl, r9
temp |= ((GPIO_Init->Pull) << (position * 2U));
8002126: ea4e 0e09 orr.w lr, lr, r9
GPIOx->PUPDR = temp;
800212a: f8c8 e00c str.w lr, [r8, #12]
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
800212e: e787 b.n 8002040 <HAL_GPIO_Init+0x180>
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
8002130: f04f 0c02 mov.w ip, #2
8002134: fa0c f707 lsl.w r7, ip, r7
8002138: 433c orrs r4, r7
SYSCFG->EXTICR[position >> 2U] = temp;
800213a: 60b4 str r4, [r6, #8]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
800213c: 02ef lsls r7, r5, #11
temp = EXTI->RTSR1;
800213e: f8de 4000 ldr.w r4, [lr]
temp &= ~(iocurrent);
8002142: ea6f 060a mvn.w r6, sl
temp |= iocurrent;
8002146: bf4c ite mi
8002148: ea4a 0404 orrmi.w r4, sl, r4
temp &= ~(iocurrent);
800214c: 4034 andpl r4, r6
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
800214e: 02ab lsls r3, r5, #10
EXTI->RTSR1 = temp;
8002150: f8ce 4000 str.w r4, [lr]
temp = EXTI->FTSR1;
8002154: f8de 4004 ldr.w r4, [lr, #4]
temp &= ~(iocurrent);
8002158: bf54 ite pl
800215a: 4034 andpl r4, r6
temp |= iocurrent;
800215c: ea4a 0404 orrmi.w r4, sl, r4
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
8002160: 03af lsls r7, r5, #14
EXTI->FTSR1 = temp;
8002162: f8ce 4004 str.w r4, [lr, #4]
temp = EXTI_CurrentCPU->EMR1;
8002166: f8de 4084 ldr.w r4, [lr, #132] @ 0x84
temp &= ~(iocurrent);
800216a: bf54 ite pl
800216c: 4034 andpl r4, r6
temp |= iocurrent;
800216e: ea4a 0404 orrmi.w r4, sl, r4
if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
8002172: 03eb lsls r3, r5, #15
EXTI_CurrentCPU->EMR1 = temp;
8002174: f8ce 4084 str.w r4, [lr, #132] @ 0x84
temp = EXTI_CurrentCPU->IMR1;
8002178: f8de 4080 ldr.w r4, [lr, #128] @ 0x80
temp &= ~(iocurrent);
800217c: bf54 ite pl
800217e: 4034 andpl r4, r6
temp |= iocurrent;
8002180: ea4a 0404 orrmi.w r4, sl, r4
EXTI_CurrentCPU->IMR1 = temp;
8002184: f8ce 4080 str.w r4, [lr, #128] @ 0x80
position++;
8002188: 3201 adds r2, #1
while (((GPIO_Init->Pin) >> position) != 0x00U)
800218a: 9b00 ldr r3, [sp, #0]
800218c: fa33 f402 lsrs.w r4, r3, r2
8002190: f47f aea8 bne.w 8001ee4 <HAL_GPIO_Init+0x24>
}
}
8002194: b005 add sp, #20
8002196: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
800219a: bf00 nop
800219c: 58020000 .word 0x58020000
80021a0: 58024400 .word 0x58024400
80021a4: 58020400 .word 0x58020400
80021a8: 58020800 .word 0x58020800
80021ac: 58020c00 .word 0x58020c00
80021b0: 58021000 .word 0x58021000
80021b4: 58021400 .word 0x58021400
80021b8: 58021800 .word 0x58021800
80021bc: 58021c00 .word 0x58021c00
80021c0: 58022000 .word 0x58022000
80021c4: 58022400 .word 0x58022400
temp = GPIOx->OSPEEDR;
80021c8: f8d0 9008 ldr.w r9, [r0, #8]
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
80021cc: 2f02 cmp r7, #2
temp |= (GPIO_Init->Speed << (position * 2U));
80021ce: 68cb ldr r3, [r1, #12]
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
80021d0: ea09 0906 and.w r9, r9, r6
temp |= (GPIO_Init->Speed << (position * 2U));
80021d4: fa03 f804 lsl.w r8, r3, r4
temp |= ((GPIO_Init->Pull) << (position * 2U));
80021d8: 688b ldr r3, [r1, #8]
temp |= (GPIO_Init->Speed << (position * 2U));
80021da: ea48 0809 orr.w r8, r8, r9
GPIOx->OSPEEDR = temp;
80021de: f8c0 8008 str.w r8, [r0, #8]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
80021e2: f3c5 1800 ubfx r8, r5, #4, #1
temp = GPIOx->OTYPER;
80021e6: f8d0 9004 ldr.w r9, [r0, #4]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
80021ea: fa08 f802 lsl.w r8, r8, r2
temp &= ~(GPIO_OTYPER_OT0 << position) ;
80021ee: ea29 0c0c bic.w ip, r9, ip
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
80021f2: ea48 0c0c orr.w ip, r8, ip
GPIOx->OTYPER = temp;
80021f6: f8c0 c004 str.w ip, [r0, #4]
temp |= ((GPIO_Init->Pull) << (position * 2U));
80021fa: fa03 fc04 lsl.w ip, r3, r4
temp = GPIOx->PUPDR;
80021fe: f8d0 800c ldr.w r8, [r0, #12]
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
8002202: ea08 0806 and.w r8, r8, r6
temp |= ((GPIO_Init->Pull) << (position * 2U));
8002206: ea4c 0c08 orr.w ip, ip, r8
GPIOx->PUPDR = temp;
800220a: f8c0 c00c str.w ip, [r0, #12]
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
800220e: f47f ae81 bne.w 8001f14 <HAL_GPIO_Init+0x54>
temp &= ~(0xFU << ((position & 0x07U) * 4U));
8002212: f002 0c07 and.w ip, r2, #7
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
8002216: 690b ldr r3, [r1, #16]
temp = GPIOx->AFR[position >> 3U];
8002218: ea4f 08d2 mov.w r8, r2, lsr #3
temp &= ~(0xFU << ((position & 0x07U) * 4U));
800221c: ea4f 0c8c mov.w ip, ip, lsl #2
8002220: eb00 0888 add.w r8, r0, r8, lsl #2
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
8002224: fa03 f30c lsl.w r3, r3, ip
temp = GPIOx->AFR[position >> 3U];
8002228: f8d8 9020 ldr.w r9, [r8, #32]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
800222c: 9301 str r3, [sp, #4]
temp &= ~(0xFU << ((position & 0x07U) * 4U));
800222e: 230f movs r3, #15
8002230: fa03 fc0c lsl.w ip, r3, ip
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
8002234: 9b01 ldr r3, [sp, #4]
temp &= ~(0xFU << ((position & 0x07U) * 4U));
8002236: ea29 090c bic.w r9, r9, ip
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
800223a: ea43 0c09 orr.w ip, r3, r9
GPIOx->AFR[position >> 3U] = temp;
800223e: f8c8 c020 str.w ip, [r8, #32]
8002242: e667 b.n 8001f14 <HAL_GPIO_Init+0x54>
temp |= iocurrent;
8002244: ea44 040c orr.w r4, r4, ip
8002248: e72b b.n 80020a2 <HAL_GPIO_Init+0x1e2>
temp |= iocurrent;
800224a: ea44 040c orr.w r4, r4, ip
800224e: e743 b.n 80020d8 <HAL_GPIO_Init+0x218>
temp |= iocurrent;
8002250: ea4c 0404 orr.w r4, ip, r4
8002254: e736 b.n 80020c4 <HAL_GPIO_Init+0x204>
temp |= iocurrent;
8002256: ea44 040c orr.w r4, r4, ip
800225a: e72a b.n 80020b2 <HAL_GPIO_Init+0x1f2>
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
800225c: f04f 0c01 mov.w ip, #1
8002260: fa0c f707 lsl.w r7, ip, r7
8002264: 433c orrs r4, r7
8002266: e768 b.n 800213a <HAL_GPIO_Init+0x27a>
8002268: f04f 0c05 mov.w ip, #5
800226c: fa0c f707 lsl.w r7, ip, r7
8002270: 433c orrs r4, r7
8002272: e762 b.n 800213a <HAL_GPIO_Init+0x27a>
8002274: f04f 0c03 mov.w ip, #3
8002278: fa0c f707 lsl.w r7, ip, r7
800227c: 433c orrs r4, r7
800227e: e75c b.n 800213a <HAL_GPIO_Init+0x27a>
8002280: 4770 bx lr
8002282: f04f 0c04 mov.w ip, #4
8002286: fa0c f707 lsl.w r7, ip, r7
800228a: 433c orrs r4, r7
800228c: e755 b.n 800213a <HAL_GPIO_Init+0x27a>
800228e: f04f 0c06 mov.w ip, #6
8002292: fa0c f707 lsl.w r7, ip, r7
8002296: 433c orrs r4, r7
8002298: e74f b.n 800213a <HAL_GPIO_Init+0x27a>
800229a: f04f 0c07 mov.w ip, #7
800229e: fa0c f707 lsl.w r7, ip, r7
80022a2: 433c orrs r4, r7
80022a4: e749 b.n 800213a <HAL_GPIO_Init+0x27a>
80022a6: f04f 0c08 mov.w ip, #8
80022aa: fa0c f707 lsl.w r7, ip, r7
80022ae: 433c orrs r4, r7
80022b0: e743 b.n 800213a <HAL_GPIO_Init+0x27a>
temp = GPIOx->PUPDR;
80022b2: f8d0 800c ldr.w r8, [r0, #12]
temp |= ((GPIO_Init->Pull) << (position * 2U));
80022b6: 688b ldr r3, [r1, #8]
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
80022b8: ea08 0806 and.w r8, r8, r6
temp |= ((GPIO_Init->Pull) << (position * 2U));
80022bc: fa03 fc04 lsl.w ip, r3, r4
80022c0: ea4c 0c08 orr.w ip, ip, r8
GPIOx->PUPDR = temp;
80022c4: f8c0 c00c str.w ip, [r0, #12]
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
80022c8: e624 b.n 8001f14 <HAL_GPIO_Init+0x54>
80022ca: bf00 nop
080022cc <HAL_GPIO_WritePin>:
{
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
80022cc: b902 cbnz r2, 80022d0 <HAL_GPIO_WritePin+0x4>
{
GPIOx->BSRR = GPIO_Pin;
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
80022ce: 0409 lsls r1, r1, #16
80022d0: 6181 str r1, [r0, #24]
}
}
80022d2: 4770 bx lr
080022d4 <HAL_PWREx_ConfigSupply>:
* process during startup.
* For more details, please refer to the power control chapter in the reference manual
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource)
{
80022d4: b538 push {r3, r4, r5, lr}
/* Check the parameters */
assert_param (IS_PWR_SUPPLY (SupplySource));
/* Check if supply source was configured */
#if defined (PWR_FLAG_SCUEN)
if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U)
80022d6: 4c10 ldr r4, [pc, #64] @ (8002318 <HAL_PWREx_ConfigSupply+0x44>)
80022d8: 68e3 ldr r3, [r4, #12]
80022da: f013 0f04 tst.w r3, #4
#else
if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN))
#endif /* defined (PWR_FLAG_SCUEN) */
{
/* Check supply configuration */
if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource)
80022de: 68e3 ldr r3, [r4, #12]
if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U)
80022e0: d105 bne.n 80022ee <HAL_PWREx_ConfigSupply+0x1a>
if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource)
80022e2: f003 0307 and.w r3, r3, #7
80022e6: 1a18 subs r0, r3, r0
80022e8: bf18 it ne
80022ea: 2001 movne r0, #1
}
}
#endif /* defined (SMPS) */
return HAL_OK;
}
80022ec: bd38 pop {r3, r4, r5, pc}
MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource);
80022ee: f023 0307 bic.w r3, r3, #7
80022f2: 4303 orrs r3, r0
80022f4: 60e3 str r3, [r4, #12]
tickstart = HAL_GetTick ();
80022f6: f7fe fd6f bl 8000dd8 <HAL_GetTick>
80022fa: 4605 mov r5, r0
while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
80022fc: e005 b.n 800230a <HAL_PWREx_ConfigSupply+0x36>
if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
80022fe: f7fe fd6b bl 8000dd8 <HAL_GetTick>
8002302: 1b40 subs r0, r0, r5
8002304: f5b0 7f7a cmp.w r0, #1000 @ 0x3e8
8002308: d804 bhi.n 8002314 <HAL_PWREx_ConfigSupply+0x40>
while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
800230a: 6863 ldr r3, [r4, #4]
800230c: 049b lsls r3, r3, #18
800230e: d5f6 bpl.n 80022fe <HAL_PWREx_ConfigSupply+0x2a>
return HAL_OK;
8002310: 2000 movs r0, #0
}
8002312: bd38 pop {r3, r4, r5, pc}
return HAL_ERROR;
8002314: 2001 movs r0, #1
}
8002316: bd38 pop {r3, r4, r5, pc}
8002318: 58024800 .word 0x58024800
0800231c <HAL_RCC_GetSysClockFreq.part.0>:
case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
800231c: 4b33 ldr r3, [pc, #204] @ (80023ec <HAL_RCC_GetSysClockFreq.part.0+0xd0>)
uint32_t HAL_RCC_GetSysClockFreq(void)
800231e: b430 push {r4, r5}
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
8002320: 6a99 ldr r1, [r3, #40] @ 0x28
pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ;
8002322: 6a9c ldr r4, [r3, #40] @ 0x28
pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
8002324: 6add ldr r5, [r3, #44] @ 0x2c
fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
if (pllm != 0U)
8002326: f414 7f7c tst.w r4, #1008 @ 0x3f0
fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
800232a: 6b5a ldr r2, [r3, #52] @ 0x34
pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ;
800232c: f3c4 1005 ubfx r0, r4, #4, #6
if (pllm != 0U)
8002330: d036 beq.n 80023a0 <HAL_RCC_GetSysClockFreq.part.0+0x84>
fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
8002332: f3c2 02cc ubfx r2, r2, #3, #13
pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
8002336: f005 0501 and.w r5, r5, #1
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
800233a: f001 0103 and.w r1, r1, #3
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
{
hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
800233e: ee07 0a90 vmov s15, r0
fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
8002342: fb05 f202 mul.w r2, r5, r2
switch (pllsource)
8002346: 2901 cmp r1, #1
pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
8002348: eeb8 7ae7 vcvt.f32.s32 s14, s15
800234c: ee06 2a90 vmov s13, r2
8002350: eefa 6ae9 vcvt.f32.s32 s13, s13, #13
switch (pllsource)
8002354: d002 beq.n 800235c <HAL_RCC_GetSysClockFreq.part.0+0x40>
8002356: 2902 cmp r1, #2
8002358: d042 beq.n 80023e0 <HAL_RCC_GetSysClockFreq.part.0+0xc4>
800235a: b319 cbz r1, 80023a4 <HAL_RCC_GetSysClockFreq.part.0+0x88>
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
break;
default:
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
800235c: eddf 7a24 vldr s15, [pc, #144] @ 80023f0 <HAL_RCC_GetSysClockFreq.part.0+0xd4>
8002360: ee87 6a87 vdiv.f32 s12, s15, s14
8002364: 6b1b ldr r3, [r3, #48] @ 0x30
8002366: f3c3 0308 ubfx r3, r3, #0, #9
800236a: ee07 3a90 vmov s15, r3
800236e: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
8002372: eef8 7ae7 vcvt.f32.s32 s15, s15
8002376: ee77 7aa6 vadd.f32 s15, s15, s13
800237a: ee77 7aa5 vadd.f32 s15, s15, s11
800237e: ee67 7a86 vmul.f32 s15, s15, s12
break;
}
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ;
8002382: 4b1a ldr r3, [pc, #104] @ (80023ec <HAL_RCC_GetSysClockFreq.part.0+0xd0>)
8002384: 6b1b ldr r3, [r3, #48] @ 0x30
8002386: f3c3 2346 ubfx r3, r3, #9, #7
800238a: 3301 adds r3, #1
sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp);
800238c: ee07 3a10 vmov s14, r3
8002390: eef8 6ac7 vcvt.f32.s32 s13, s14
8002394: ee87 7aa6 vdiv.f32 s14, s15, s13
8002398: eefc 7ac7 vcvt.u32.f32 s15, s14
800239c: ee17 0a90 vmov r0, s15
sysclockfreq = CSI_VALUE;
break;
}
return sysclockfreq;
}
80023a0: bc30 pop {r4, r5}
80023a2: 4770 bx lr
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
80023a4: 681a ldr r2, [r3, #0]
80023a6: 0692 lsls r2, r2, #26
80023a8: d51d bpl.n 80023e6 <HAL_RCC_GetSysClockFreq.part.0+0xca>
hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
80023aa: 6819 ldr r1, [r3, #0]
pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
80023ac: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
80023b0: 4a10 ldr r2, [pc, #64] @ (80023f4 <HAL_RCC_GetSysClockFreq.part.0+0xd8>)
pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
80023b2: 6b1b ldr r3, [r3, #48] @ 0x30
hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
80023b4: f3c1 01c1 ubfx r1, r1, #3, #2
pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
80023b8: f3c3 0308 ubfx r3, r3, #0, #9
hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
80023bc: 40ca lsrs r2, r1
pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
80023be: ee07 3a90 vmov s15, r3
80023c2: ee06 2a10 vmov s12, r2
80023c6: eef8 7ae7 vcvt.f32.s32 s15, s15
80023ca: eeb8 6ac6 vcvt.f32.s32 s12, s12
80023ce: ee77 6aa6 vadd.f32 s13, s15, s13
80023d2: eec6 7a07 vdiv.f32 s15, s12, s14
80023d6: ee36 7aa5 vadd.f32 s14, s13, s11
80023da: ee67 7a87 vmul.f32 s15, s15, s14
80023de: e7d0 b.n 8002382 <HAL_RCC_GetSysClockFreq.part.0+0x66>
pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
80023e0: eddf 7a05 vldr s15, [pc, #20] @ 80023f8 <HAL_RCC_GetSysClockFreq.part.0+0xdc>
80023e4: e7bc b.n 8002360 <HAL_RCC_GetSysClockFreq.part.0+0x44>
pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
80023e6: eddf 7a05 vldr s15, [pc, #20] @ 80023fc <HAL_RCC_GetSysClockFreq.part.0+0xe0>
80023ea: e7b9 b.n 8002360 <HAL_RCC_GetSysClockFreq.part.0+0x44>
80023ec: 58024400 .word 0x58024400
80023f0: 4a742400 .word 0x4a742400
80023f4: 03d09000 .word 0x03d09000
80023f8: 4bbebc20 .word 0x4bbebc20
80023fc: 4c742400 .word 0x4c742400
08002400 <HAL_RCC_OscConfig>:
if (RCC_OscInitStruct == NULL)
8002400: 2800 cmp r0, #0
8002402: f000 82e7 beq.w 80029d4 <HAL_RCC_OscConfig+0x5d4>
{
8002406: b5f8 push {r3, r4, r5, r6, r7, lr}
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8002408: 6803 ldr r3, [r0, #0]
800240a: 4604 mov r4, r0
800240c: 07d9 lsls r1, r3, #31
800240e: d52e bpl.n 800246e <HAL_RCC_OscConfig+0x6e>
const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
8002410: 4997 ldr r1, [pc, #604] @ (8002670 <HAL_RCC_OscConfig+0x270>)
8002412: 690a ldr r2, [r1, #16]
const uint32_t temp_pllckselr = RCC->PLLCKSELR;
8002414: 6a89 ldr r1, [r1, #40] @ 0x28
const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
8002416: f002 0238 and.w r2, r2, #56 @ 0x38
if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE)))
800241a: 2a10 cmp r2, #16
800241c: f000 80ee beq.w 80025fc <HAL_RCC_OscConfig+0x1fc>
8002420: 2a18 cmp r2, #24
8002422: f000 80e6 beq.w 80025f2 <HAL_RCC_OscConfig+0x1f2>
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8002426: 6863 ldr r3, [r4, #4]
8002428: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
800242c: f000 8111 beq.w 8002652 <HAL_RCC_OscConfig+0x252>
8002430: 2b00 cmp r3, #0
8002432: f000 8167 beq.w 8002704 <HAL_RCC_OscConfig+0x304>
8002436: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
800243a: 4b8d ldr r3, [pc, #564] @ (8002670 <HAL_RCC_OscConfig+0x270>)
800243c: 681a ldr r2, [r3, #0]
800243e: f000 8288 beq.w 8002952 <HAL_RCC_OscConfig+0x552>
8002442: f422 3280 bic.w r2, r2, #65536 @ 0x10000
8002446: 601a str r2, [r3, #0]
8002448: 681a ldr r2, [r3, #0]
800244a: f422 2280 bic.w r2, r2, #262144 @ 0x40000
800244e: 601a str r2, [r3, #0]
tickstart = HAL_GetTick();
8002450: f7fe fcc2 bl 8000dd8 <HAL_GetTick>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
8002454: 4e86 ldr r6, [pc, #536] @ (8002670 <HAL_RCC_OscConfig+0x270>)
tickstart = HAL_GetTick();
8002456: 4605 mov r5, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
8002458: e005 b.n 8002466 <HAL_RCC_OscConfig+0x66>
if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
800245a: f7fe fcbd bl 8000dd8 <HAL_GetTick>
800245e: 1b40 subs r0, r0, r5
8002460: 2864 cmp r0, #100 @ 0x64
8002462: f200 814d bhi.w 8002700 <HAL_RCC_OscConfig+0x300>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
8002466: 6833 ldr r3, [r6, #0]
8002468: 039b lsls r3, r3, #14
800246a: d5f6 bpl.n 800245a <HAL_RCC_OscConfig+0x5a>
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
800246c: 6823 ldr r3, [r4, #0]
800246e: 079d lsls r5, r3, #30
8002470: d470 bmi.n 8002554 <HAL_RCC_OscConfig+0x154>
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
8002472: 06d9 lsls r1, r3, #27
8002474: d533 bpl.n 80024de <HAL_RCC_OscConfig+0xde>
const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
8002476: 4a7e ldr r2, [pc, #504] @ (8002670 <HAL_RCC_OscConfig+0x270>)
8002478: 6913 ldr r3, [r2, #16]
const uint32_t temp_pllckselr = RCC->PLLCKSELR;
800247a: 6a92 ldr r2, [r2, #40] @ 0x28
const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
800247c: f003 0338 and.w r3, r3, #56 @ 0x38
if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI)))
8002480: 2b08 cmp r3, #8
8002482: f000 80cb beq.w 800261c <HAL_RCC_OscConfig+0x21c>
8002486: 2b18 cmp r3, #24
8002488: f000 80c3 beq.w 8002612 <HAL_RCC_OscConfig+0x212>
if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF)
800248c: 69e3 ldr r3, [r4, #28]
__HAL_RCC_CSI_ENABLE();
800248e: 4d78 ldr r5, [pc, #480] @ (8002670 <HAL_RCC_OscConfig+0x270>)
if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF)
8002490: 2b00 cmp r3, #0
8002492: f000 816f beq.w 8002774 <HAL_RCC_OscConfig+0x374>
__HAL_RCC_CSI_ENABLE();
8002496: 682b ldr r3, [r5, #0]
8002498: f043 0380 orr.w r3, r3, #128 @ 0x80
800249c: 602b str r3, [r5, #0]
tickstart = HAL_GetTick();
800249e: f7fe fc9b bl 8000dd8 <HAL_GetTick>
80024a2: 4606 mov r6, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
80024a4: e005 b.n 80024b2 <HAL_RCC_OscConfig+0xb2>
if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
80024a6: f7fe fc97 bl 8000dd8 <HAL_GetTick>
80024aa: 1b80 subs r0, r0, r6
80024ac: 2802 cmp r0, #2
80024ae: f200 8127 bhi.w 8002700 <HAL_RCC_OscConfig+0x300>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
80024b2: 682b ldr r3, [r5, #0]
80024b4: 05db lsls r3, r3, #23
80024b6: d5f6 bpl.n 80024a6 <HAL_RCC_OscConfig+0xa6>
__HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
80024b8: f7fe fca6 bl 8000e08 <HAL_GetREVID>
80024bc: f241 0303 movw r3, #4099 @ 0x1003
80024c0: 4298 cmp r0, r3
80024c2: f200 8267 bhi.w 8002994 <HAL_RCC_OscConfig+0x594>
80024c6: 6a22 ldr r2, [r4, #32]
80024c8: 686b ldr r3, [r5, #4]
80024ca: 2a20 cmp r2, #32
80024cc: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000
80024d0: bf0c ite eq
80024d2: f043 4380 orreq.w r3, r3, #1073741824 @ 0x40000000
80024d6: ea43 6382 orrne.w r3, r3, r2, lsl #26
80024da: 606b str r3, [r5, #4]
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80024dc: 6823 ldr r3, [r4, #0]
80024de: 071d lsls r5, r3, #28
80024e0: d516 bpl.n 8002510 <HAL_RCC_OscConfig+0x110>
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
80024e2: 6963 ldr r3, [r4, #20]
__HAL_RCC_LSI_ENABLE();
80024e4: 4d62 ldr r5, [pc, #392] @ (8002670 <HAL_RCC_OscConfig+0x270>)
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
80024e6: 2b00 cmp r3, #0
80024e8: f000 8122 beq.w 8002730 <HAL_RCC_OscConfig+0x330>
__HAL_RCC_LSI_ENABLE();
80024ec: 6f6b ldr r3, [r5, #116] @ 0x74
80024ee: f043 0301 orr.w r3, r3, #1
80024f2: 676b str r3, [r5, #116] @ 0x74
tickstart = HAL_GetTick();
80024f4: f7fe fc70 bl 8000dd8 <HAL_GetTick>
80024f8: 4606 mov r6, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
80024fa: e005 b.n 8002508 <HAL_RCC_OscConfig+0x108>
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
80024fc: f7fe fc6c bl 8000dd8 <HAL_GetTick>
8002500: 1b80 subs r0, r0, r6
8002502: 2802 cmp r0, #2
8002504: f200 80fc bhi.w 8002700 <HAL_RCC_OscConfig+0x300>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
8002508: 6f6b ldr r3, [r5, #116] @ 0x74
800250a: 0798 lsls r0, r3, #30
800250c: d5f6 bpl.n 80024fc <HAL_RCC_OscConfig+0xfc>
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
800250e: 6823 ldr r3, [r4, #0]
8002510: 069a lsls r2, r3, #26
8002512: d516 bpl.n 8002542 <HAL_RCC_OscConfig+0x142>
if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF)
8002514: 69a3 ldr r3, [r4, #24]
__HAL_RCC_HSI48_ENABLE();
8002516: 4d56 ldr r5, [pc, #344] @ (8002670 <HAL_RCC_OscConfig+0x270>)
if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF)
8002518: 2b00 cmp r3, #0
800251a: f000 811a beq.w 8002752 <HAL_RCC_OscConfig+0x352>
__HAL_RCC_HSI48_ENABLE();
800251e: 682b ldr r3, [r5, #0]
8002520: f443 5380 orr.w r3, r3, #4096 @ 0x1000
8002524: 602b str r3, [r5, #0]
tickstart = HAL_GetTick();
8002526: f7fe fc57 bl 8000dd8 <HAL_GetTick>
800252a: 4606 mov r6, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
800252c: e005 b.n 800253a <HAL_RCC_OscConfig+0x13a>
if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
800252e: f7fe fc53 bl 8000dd8 <HAL_GetTick>
8002532: 1b80 subs r0, r0, r6
8002534: 2802 cmp r0, #2
8002536: f200 80e3 bhi.w 8002700 <HAL_RCC_OscConfig+0x300>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
800253a: 682b ldr r3, [r5, #0]
800253c: 049f lsls r7, r3, #18
800253e: d5f6 bpl.n 800252e <HAL_RCC_OscConfig+0x12e>
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8002540: 6823 ldr r3, [r4, #0]
8002542: 0759 lsls r1, r3, #29
8002544: f100 808b bmi.w 800265e <HAL_RCC_OscConfig+0x25e>
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8002548: 6a63 ldr r3, [r4, #36] @ 0x24
800254a: 2b00 cmp r3, #0
800254c: f040 80bf bne.w 80026ce <HAL_RCC_OscConfig+0x2ce>
return HAL_OK;
8002550: 2000 movs r0, #0
}
8002552: bdf8 pop {r3, r4, r5, r6, r7, pc}
const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
8002554: 4a46 ldr r2, [pc, #280] @ (8002670 <HAL_RCC_OscConfig+0x270>)
8002556: 6913 ldr r3, [r2, #16]
const uint32_t temp_pllckselr = RCC->PLLCKSELR;
8002558: 6a92 ldr r2, [r2, #40] @ 0x28
if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
800255a: f013 0338 ands.w r3, r3, #56 @ 0x38
800255e: d12d bne.n 80025bc <HAL_RCC_OscConfig+0x1bc>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
8002560: 4b43 ldr r3, [pc, #268] @ (8002670 <HAL_RCC_OscConfig+0x270>)
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
8002562: 68e2 ldr r2, [r4, #12]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
8002564: 681b ldr r3, [r3, #0]
8002566: 0759 lsls r1, r3, #29
8002568: d501 bpl.n 800256e <HAL_RCC_OscConfig+0x16e>
800256a: 2a00 cmp r2, #0
800256c: d04f beq.n 800260e <HAL_RCC_OscConfig+0x20e>
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
800256e: 4d40 ldr r5, [pc, #256] @ (8002670 <HAL_RCC_OscConfig+0x270>)
8002570: 682b ldr r3, [r5, #0]
8002572: f023 0319 bic.w r3, r3, #25
8002576: 4313 orrs r3, r2
8002578: 602b str r3, [r5, #0]
tickstart = HAL_GetTick();
800257a: f7fe fc2d bl 8000dd8 <HAL_GetTick>
800257e: 4606 mov r6, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
8002580: e005 b.n 800258e <HAL_RCC_OscConfig+0x18e>
if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8002582: f7fe fc29 bl 8000dd8 <HAL_GetTick>
8002586: 1b80 subs r0, r0, r6
8002588: 2802 cmp r0, #2
800258a: f200 80b9 bhi.w 8002700 <HAL_RCC_OscConfig+0x300>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
800258e: 682b ldr r3, [r5, #0]
8002590: 075b lsls r3, r3, #29
8002592: d5f6 bpl.n 8002582 <HAL_RCC_OscConfig+0x182>
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8002594: f7fe fc38 bl 8000e08 <HAL_GetREVID>
8002598: f241 0303 movw r3, #4099 @ 0x1003
800259c: 4298 cmp r0, r3
800259e: f200 8110 bhi.w 80027c2 <HAL_RCC_OscConfig+0x3c2>
80025a2: 6922 ldr r2, [r4, #16]
80025a4: 686b ldr r3, [r5, #4]
80025a6: 2a40 cmp r2, #64 @ 0x40
80025a8: f423 337c bic.w r3, r3, #258048 @ 0x3f000
80025ac: bf0c ite eq
80025ae: f443 3300 orreq.w r3, r3, #131072 @ 0x20000
80025b2: ea43 3302 orrne.w r3, r3, r2, lsl #12
80025b6: 606b str r3, [r5, #4]
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
80025b8: 6823 ldr r3, [r4, #0]
80025ba: e75a b.n 8002472 <HAL_RCC_OscConfig+0x72>
if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
80025bc: 2b18 cmp r3, #24
80025be: f000 80fc beq.w 80027ba <HAL_RCC_OscConfig+0x3ba>
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
80025c2: 4d2b ldr r5, [pc, #172] @ (8002670 <HAL_RCC_OscConfig+0x270>)
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
80025c4: 68e2 ldr r2, [r4, #12]
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
80025c6: 682b ldr r3, [r5, #0]
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
80025c8: 2a00 cmp r2, #0
80025ca: f000 80e5 beq.w 8002798 <HAL_RCC_OscConfig+0x398>
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
80025ce: f023 0319 bic.w r3, r3, #25
80025d2: 4313 orrs r3, r2
80025d4: 602b str r3, [r5, #0]
tickstart = HAL_GetTick();
80025d6: f7fe fbff bl 8000dd8 <HAL_GetTick>
80025da: 4606 mov r6, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
80025dc: e005 b.n 80025ea <HAL_RCC_OscConfig+0x1ea>
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
80025de: f7fe fbfb bl 8000dd8 <HAL_GetTick>
80025e2: 1b80 subs r0, r0, r6
80025e4: 2802 cmp r0, #2
80025e6: f200 808b bhi.w 8002700 <HAL_RCC_OscConfig+0x300>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
80025ea: 682b ldr r3, [r5, #0]
80025ec: 075f lsls r7, r3, #29
80025ee: d5f6 bpl.n 80025de <HAL_RCC_OscConfig+0x1de>
80025f0: e7d0 b.n 8002594 <HAL_RCC_OscConfig+0x194>
if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE)))
80025f2: f001 0103 and.w r1, r1, #3
80025f6: 2902 cmp r1, #2
80025f8: f47f af15 bne.w 8002426 <HAL_RCC_OscConfig+0x26>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80025fc: 4a1c ldr r2, [pc, #112] @ (8002670 <HAL_RCC_OscConfig+0x270>)
80025fe: 6812 ldr r2, [r2, #0]
8002600: 0392 lsls r2, r2, #14
8002602: f57f af34 bpl.w 800246e <HAL_RCC_OscConfig+0x6e>
8002606: 6862 ldr r2, [r4, #4]
8002608: 2a00 cmp r2, #0
800260a: f47f af30 bne.w 800246e <HAL_RCC_OscConfig+0x6e>
return HAL_ERROR;
800260e: 2001 movs r0, #1
}
8002610: bdf8 pop {r3, r4, r5, r6, r7, pc}
if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI)))
8002612: f002 0203 and.w r2, r2, #3
8002616: 2a01 cmp r2, #1
8002618: f47f af38 bne.w 800248c <HAL_RCC_OscConfig+0x8c>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
800261c: 4b14 ldr r3, [pc, #80] @ (8002670 <HAL_RCC_OscConfig+0x270>)
800261e: 681b ldr r3, [r3, #0]
8002620: 05da lsls r2, r3, #23
8002622: d502 bpl.n 800262a <HAL_RCC_OscConfig+0x22a>
8002624: 69e3 ldr r3, [r4, #28]
8002626: 2b80 cmp r3, #128 @ 0x80
8002628: d1f1 bne.n 800260e <HAL_RCC_OscConfig+0x20e>
__HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
800262a: f7fe fbed bl 8000e08 <HAL_GetREVID>
800262e: f241 0303 movw r3, #4099 @ 0x1003
8002632: 4298 cmp r0, r3
8002634: f200 80ce bhi.w 80027d4 <HAL_RCC_OscConfig+0x3d4>
8002638: 6a22 ldr r2, [r4, #32]
800263a: 2a20 cmp r2, #32
800263c: f000 81b9 beq.w 80029b2 <HAL_RCC_OscConfig+0x5b2>
8002640: 490b ldr r1, [pc, #44] @ (8002670 <HAL_RCC_OscConfig+0x270>)
8002642: 684b ldr r3, [r1, #4]
8002644: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000
8002648: ea43 6382 orr.w r3, r3, r2, lsl #26
800264c: 604b str r3, [r1, #4]
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
800264e: 6823 ldr r3, [r4, #0]
8002650: e745 b.n 80024de <HAL_RCC_OscConfig+0xde>
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8002652: 4a07 ldr r2, [pc, #28] @ (8002670 <HAL_RCC_OscConfig+0x270>)
8002654: 6813 ldr r3, [r2, #0]
8002656: f443 3380 orr.w r3, r3, #65536 @ 0x10000
800265a: 6013 str r3, [r2, #0]
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
800265c: e6f8 b.n 8002450 <HAL_RCC_OscConfig+0x50>
PWR->CR1 |= PWR_CR1_DBP;
800265e: 4d05 ldr r5, [pc, #20] @ (8002674 <HAL_RCC_OscConfig+0x274>)
8002660: 682b ldr r3, [r5, #0]
8002662: f443 7380 orr.w r3, r3, #256 @ 0x100
8002666: 602b str r3, [r5, #0]
tickstart = HAL_GetTick();
8002668: f7fe fbb6 bl 8000dd8 <HAL_GetTick>
800266c: 4606 mov r6, r0
while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
800266e: e008 b.n 8002682 <HAL_RCC_OscConfig+0x282>
8002670: 58024400 .word 0x58024400
8002674: 58024800 .word 0x58024800
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8002678: f7fe fbae bl 8000dd8 <HAL_GetTick>
800267c: 1b80 subs r0, r0, r6
800267e: 2864 cmp r0, #100 @ 0x64
8002680: d83e bhi.n 8002700 <HAL_RCC_OscConfig+0x300>
while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
8002682: 682b ldr r3, [r5, #0]
8002684: 05da lsls r2, r3, #23
8002686: d5f7 bpl.n 8002678 <HAL_RCC_OscConfig+0x278>
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8002688: 68a3 ldr r3, [r4, #8]
800268a: 2b01 cmp r3, #1
800268c: f000 818b beq.w 80029a6 <HAL_RCC_OscConfig+0x5a6>
8002690: 2b00 cmp r3, #0
8002692: f000 8166 beq.w 8002962 <HAL_RCC_OscConfig+0x562>
8002696: 2b05 cmp r3, #5
8002698: 4b85 ldr r3, [pc, #532] @ (80028b0 <HAL_RCC_OscConfig+0x4b0>)
800269a: 6f1a ldr r2, [r3, #112] @ 0x70
800269c: f000 8192 beq.w 80029c4 <HAL_RCC_OscConfig+0x5c4>
80026a0: f022 0201 bic.w r2, r2, #1
80026a4: 671a str r2, [r3, #112] @ 0x70
80026a6: 6f1a ldr r2, [r3, #112] @ 0x70
80026a8: f022 0204 bic.w r2, r2, #4
80026ac: 671a str r2, [r3, #112] @ 0x70
tickstart = HAL_GetTick();
80026ae: f7fe fb93 bl 8000dd8 <HAL_GetTick>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
80026b2: 4e7f ldr r6, [pc, #508] @ (80028b0 <HAL_RCC_OscConfig+0x4b0>)
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
80026b4: f241 3788 movw r7, #5000 @ 0x1388
tickstart = HAL_GetTick();
80026b8: 4605 mov r5, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
80026ba: e004 b.n 80026c6 <HAL_RCC_OscConfig+0x2c6>
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
80026bc: f7fe fb8c bl 8000dd8 <HAL_GetTick>
80026c0: 1b40 subs r0, r0, r5
80026c2: 42b8 cmp r0, r7
80026c4: d81c bhi.n 8002700 <HAL_RCC_OscConfig+0x300>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
80026c6: 6f33 ldr r3, [r6, #112] @ 0x70
80026c8: 079b lsls r3, r3, #30
80026ca: d5f7 bpl.n 80026bc <HAL_RCC_OscConfig+0x2bc>
80026cc: e73c b.n 8002548 <HAL_RCC_OscConfig+0x148>
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1)
80026ce: 4d78 ldr r5, [pc, #480] @ (80028b0 <HAL_RCC_OscConfig+0x4b0>)
80026d0: 692a ldr r2, [r5, #16]
80026d2: f002 0238 and.w r2, r2, #56 @ 0x38
80026d6: 2a18 cmp r2, #24
80026d8: f000 80ee beq.w 80028b8 <HAL_RCC_OscConfig+0x4b8>
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
80026dc: 2b02 cmp r3, #2
__HAL_RCC_PLL_DISABLE();
80026de: 682b ldr r3, [r5, #0]
80026e0: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
80026e4: 602b str r3, [r5, #0]
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
80026e6: d07f beq.n 80027e8 <HAL_RCC_OscConfig+0x3e8>
tickstart = HAL_GetTick();
80026e8: f7fe fb76 bl 8000dd8 <HAL_GetTick>
80026ec: 4604 mov r4, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
80026ee: 682b ldr r3, [r5, #0]
80026f0: 019b lsls r3, r3, #6
80026f2: f57f af2d bpl.w 8002550 <HAL_RCC_OscConfig+0x150>
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80026f6: f7fe fb6f bl 8000dd8 <HAL_GetTick>
80026fa: 1b00 subs r0, r0, r4
80026fc: 2802 cmp r0, #2
80026fe: d9f6 bls.n 80026ee <HAL_RCC_OscConfig+0x2ee>
return HAL_TIMEOUT;
8002700: 2003 movs r0, #3
}
8002702: bdf8 pop {r3, r4, r5, r6, r7, pc}
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8002704: 4d6a ldr r5, [pc, #424] @ (80028b0 <HAL_RCC_OscConfig+0x4b0>)
8002706: 682b ldr r3, [r5, #0]
8002708: f423 3380 bic.w r3, r3, #65536 @ 0x10000
800270c: 602b str r3, [r5, #0]
800270e: 682b ldr r3, [r5, #0]
8002710: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8002714: 602b str r3, [r5, #0]
tickstart = HAL_GetTick();
8002716: f7fe fb5f bl 8000dd8 <HAL_GetTick>
800271a: 4606 mov r6, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
800271c: e004 b.n 8002728 <HAL_RCC_OscConfig+0x328>
if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
800271e: f7fe fb5b bl 8000dd8 <HAL_GetTick>
8002722: 1b80 subs r0, r0, r6
8002724: 2864 cmp r0, #100 @ 0x64
8002726: d8eb bhi.n 8002700 <HAL_RCC_OscConfig+0x300>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
8002728: 682b ldr r3, [r5, #0]
800272a: 039f lsls r7, r3, #14
800272c: d4f7 bmi.n 800271e <HAL_RCC_OscConfig+0x31e>
800272e: e69d b.n 800246c <HAL_RCC_OscConfig+0x6c>
__HAL_RCC_LSI_DISABLE();
8002730: 6f6b ldr r3, [r5, #116] @ 0x74
8002732: f023 0301 bic.w r3, r3, #1
8002736: 676b str r3, [r5, #116] @ 0x74
tickstart = HAL_GetTick();
8002738: f7fe fb4e bl 8000dd8 <HAL_GetTick>
800273c: 4606 mov r6, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
800273e: e004 b.n 800274a <HAL_RCC_OscConfig+0x34a>
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8002740: f7fe fb4a bl 8000dd8 <HAL_GetTick>
8002744: 1b80 subs r0, r0, r6
8002746: 2802 cmp r0, #2
8002748: d8da bhi.n 8002700 <HAL_RCC_OscConfig+0x300>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
800274a: 6f6b ldr r3, [r5, #116] @ 0x74
800274c: 0799 lsls r1, r3, #30
800274e: d4f7 bmi.n 8002740 <HAL_RCC_OscConfig+0x340>
8002750: e6dd b.n 800250e <HAL_RCC_OscConfig+0x10e>
__HAL_RCC_HSI48_DISABLE();
8002752: 682b ldr r3, [r5, #0]
8002754: f423 5380 bic.w r3, r3, #4096 @ 0x1000
8002758: 602b str r3, [r5, #0]
tickstart = HAL_GetTick();
800275a: f7fe fb3d bl 8000dd8 <HAL_GetTick>
800275e: 4606 mov r6, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
8002760: e004 b.n 800276c <HAL_RCC_OscConfig+0x36c>
if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
8002762: f7fe fb39 bl 8000dd8 <HAL_GetTick>
8002766: 1b80 subs r0, r0, r6
8002768: 2802 cmp r0, #2
800276a: d8c9 bhi.n 8002700 <HAL_RCC_OscConfig+0x300>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
800276c: 682b ldr r3, [r5, #0]
800276e: 0498 lsls r0, r3, #18
8002770: d4f7 bmi.n 8002762 <HAL_RCC_OscConfig+0x362>
8002772: e6e5 b.n 8002540 <HAL_RCC_OscConfig+0x140>
__HAL_RCC_CSI_DISABLE();
8002774: 682b ldr r3, [r5, #0]
8002776: f023 0380 bic.w r3, r3, #128 @ 0x80
800277a: 602b str r3, [r5, #0]
tickstart = HAL_GetTick();
800277c: f7fe fb2c bl 8000dd8 <HAL_GetTick>
8002780: 4606 mov r6, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
8002782: e004 b.n 800278e <HAL_RCC_OscConfig+0x38e>
if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
8002784: f7fe fb28 bl 8000dd8 <HAL_GetTick>
8002788: 1b80 subs r0, r0, r6
800278a: 2802 cmp r0, #2
800278c: d8b8 bhi.n 8002700 <HAL_RCC_OscConfig+0x300>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
800278e: 682b ldr r3, [r5, #0]
8002790: 05df lsls r7, r3, #23
8002792: d4f7 bmi.n 8002784 <HAL_RCC_OscConfig+0x384>
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8002794: 6823 ldr r3, [r4, #0]
8002796: e6a2 b.n 80024de <HAL_RCC_OscConfig+0xde>
__HAL_RCC_HSI_DISABLE();
8002798: f023 0301 bic.w r3, r3, #1
800279c: 602b str r3, [r5, #0]
tickstart = HAL_GetTick();
800279e: f7fe fb1b bl 8000dd8 <HAL_GetTick>
80027a2: 4606 mov r6, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
80027a4: e004 b.n 80027b0 <HAL_RCC_OscConfig+0x3b0>
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
80027a6: f7fe fb17 bl 8000dd8 <HAL_GetTick>
80027aa: 1b80 subs r0, r0, r6
80027ac: 2802 cmp r0, #2
80027ae: d8a7 bhi.n 8002700 <HAL_RCC_OscConfig+0x300>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
80027b0: 682b ldr r3, [r5, #0]
80027b2: 0758 lsls r0, r3, #29
80027b4: d4f7 bmi.n 80027a6 <HAL_RCC_OscConfig+0x3a6>
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
80027b6: 6823 ldr r3, [r4, #0]
80027b8: e65b b.n 8002472 <HAL_RCC_OscConfig+0x72>
if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
80027ba: 0790 lsls r0, r2, #30
80027bc: f47f af01 bne.w 80025c2 <HAL_RCC_OscConfig+0x1c2>
80027c0: e6ce b.n 8002560 <HAL_RCC_OscConfig+0x160>
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80027c2: 686b ldr r3, [r5, #4]
80027c4: 6922 ldr r2, [r4, #16]
80027c6: f023 43fe bic.w r3, r3, #2130706432 @ 0x7f000000
80027ca: ea43 6302 orr.w r3, r3, r2, lsl #24
80027ce: 606b str r3, [r5, #4]
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
80027d0: 6823 ldr r3, [r4, #0]
80027d2: e64e b.n 8002472 <HAL_RCC_OscConfig+0x72>
__HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
80027d4: 4a36 ldr r2, [pc, #216] @ (80028b0 <HAL_RCC_OscConfig+0x4b0>)
80027d6: 6a21 ldr r1, [r4, #32]
80027d8: 68d3 ldr r3, [r2, #12]
80027da: f023 537c bic.w r3, r3, #1056964608 @ 0x3f000000
80027de: ea43 6301 orr.w r3, r3, r1, lsl #24
80027e2: 60d3 str r3, [r2, #12]
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80027e4: 6823 ldr r3, [r4, #0]
80027e6: e67a b.n 80024de <HAL_RCC_OscConfig+0xde>
tickstart = HAL_GetTick();
80027e8: f7fe faf6 bl 8000dd8 <HAL_GetTick>
80027ec: 4606 mov r6, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
80027ee: e004 b.n 80027fa <HAL_RCC_OscConfig+0x3fa>
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80027f0: f7fe faf2 bl 8000dd8 <HAL_GetTick>
80027f4: 1b80 subs r0, r0, r6
80027f6: 2802 cmp r0, #2
80027f8: d882 bhi.n 8002700 <HAL_RCC_OscConfig+0x300>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
80027fa: 682b ldr r3, [r5, #0]
80027fc: 0199 lsls r1, r3, #6
80027fe: d4f7 bmi.n 80027f0 <HAL_RCC_OscConfig+0x3f0>
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8002800: 6aa9 ldr r1, [r5, #40] @ 0x28
8002802: 4b2c ldr r3, [pc, #176] @ (80028b4 <HAL_RCC_OscConfig+0x4b4>)
8002804: 6aa2 ldr r2, [r4, #40] @ 0x28
8002806: 400b ands r3, r1
8002808: 4313 orrs r3, r2
800280a: 6ae2 ldr r2, [r4, #44] @ 0x2c
800280c: ea43 1302 orr.w r3, r3, r2, lsl #4
8002810: 62ab str r3, [r5, #40] @ 0x28
8002812: 6b21 ldr r1, [r4, #48] @ 0x30
8002814: e9d4 320d ldrd r3, r2, [r4, #52] @ 0x34
8002818: 3901 subs r1, #1
800281a: 3b01 subs r3, #1
800281c: 3a01 subs r2, #1
800281e: f3c1 0108 ubfx r1, r1, #0, #9
8002822: 025b lsls r3, r3, #9
8002824: 0412 lsls r2, r2, #16
8002826: b29b uxth r3, r3
8002828: f402 02fe and.w r2, r2, #8323072 @ 0x7f0000
800282c: 4313 orrs r3, r2
800282e: 6be2 ldr r2, [r4, #60] @ 0x3c
8002830: 3a01 subs r2, #1
8002832: 430b orrs r3, r1
8002834: 0612 lsls r2, r2, #24
8002836: f002 42fe and.w r2, r2, #2130706432 @ 0x7f000000
800283a: 4313 orrs r3, r2
800283c: 632b str r3, [r5, #48] @ 0x30
__HAL_RCC_PLLFRACN_DISABLE();
800283e: 6aeb ldr r3, [r5, #44] @ 0x2c
8002840: f023 0301 bic.w r3, r3, #1
8002844: 62eb str r3, [r5, #44] @ 0x2c
__HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
8002846: 6b6b ldr r3, [r5, #52] @ 0x34
8002848: 6ca2 ldr r2, [r4, #72] @ 0x48
800284a: f36f 03cf bfc r3, #3, #13
800284e: ea43 03c2 orr.w r3, r3, r2, lsl #3
8002852: 636b str r3, [r5, #52] @ 0x34
__HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ;
8002854: 6aeb ldr r3, [r5, #44] @ 0x2c
8002856: 6c22 ldr r2, [r4, #64] @ 0x40
8002858: f023 030c bic.w r3, r3, #12
800285c: 4313 orrs r3, r2
800285e: 62eb str r3, [r5, #44] @ 0x2c
__HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ;
8002860: 6aeb ldr r3, [r5, #44] @ 0x2c
8002862: 6c62 ldr r2, [r4, #68] @ 0x44
8002864: f023 0302 bic.w r3, r3, #2
8002868: 4313 orrs r3, r2
800286a: 62eb str r3, [r5, #44] @ 0x2c
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
800286c: 6aeb ldr r3, [r5, #44] @ 0x2c
800286e: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8002872: 62eb str r3, [r5, #44] @ 0x2c
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
8002874: 6aeb ldr r3, [r5, #44] @ 0x2c
8002876: f443 3300 orr.w r3, r3, #131072 @ 0x20000
800287a: 62eb str r3, [r5, #44] @ 0x2c
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
800287c: 6aeb ldr r3, [r5, #44] @ 0x2c
800287e: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8002882: 62eb str r3, [r5, #44] @ 0x2c
__HAL_RCC_PLLFRACN_ENABLE();
8002884: 6aeb ldr r3, [r5, #44] @ 0x2c
8002886: f043 0301 orr.w r3, r3, #1
800288a: 62eb str r3, [r5, #44] @ 0x2c
__HAL_RCC_PLL_ENABLE();
800288c: 682b ldr r3, [r5, #0]
800288e: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
8002892: 602b str r3, [r5, #0]
tickstart = HAL_GetTick();
8002894: f7fe faa0 bl 8000dd8 <HAL_GetTick>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
8002898: 4d05 ldr r5, [pc, #20] @ (80028b0 <HAL_RCC_OscConfig+0x4b0>)
tickstart = HAL_GetTick();
800289a: 4604 mov r4, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
800289c: 682b ldr r3, [r5, #0]
800289e: 019a lsls r2, r3, #6
80028a0: f53f ae56 bmi.w 8002550 <HAL_RCC_OscConfig+0x150>
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80028a4: f7fe fa98 bl 8000dd8 <HAL_GetTick>
80028a8: 1b00 subs r0, r0, r4
80028aa: 2802 cmp r0, #2
80028ac: d9f6 bls.n 800289c <HAL_RCC_OscConfig+0x49c>
80028ae: e727 b.n 8002700 <HAL_RCC_OscConfig+0x300>
80028b0: 58024400 .word 0x58024400
80028b4: fffffc0c .word 0xfffffc0c
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
80028b8: 2b01 cmp r3, #1
temp1_pllckcfg = RCC->PLLCKSELR;
80028ba: 6aaa ldr r2, [r5, #40] @ 0x28
temp2_pllckcfg = RCC->PLL1DIVR;
80028bc: 6b28 ldr r0, [r5, #48] @ 0x30
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
80028be: f43f aea6 beq.w 800260e <HAL_RCC_OscConfig+0x20e>
(READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80028c2: f002 0303 and.w r3, r2, #3
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
80028c6: 6aa1 ldr r1, [r4, #40] @ 0x28
80028c8: 428b cmp r3, r1
80028ca: f47f aea0 bne.w 800260e <HAL_RCC_OscConfig+0x20e>
((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
80028ce: f3c2 1205 ubfx r2, r2, #4, #6
(READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80028d2: 6ae3 ldr r3, [r4, #44] @ 0x2c
80028d4: 429a cmp r2, r3
80028d6: f47f ae9a bne.w 800260e <HAL_RCC_OscConfig+0x20e>
(READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
80028da: 6b23 ldr r3, [r4, #48] @ 0x30
80028dc: f3c0 0208 ubfx r2, r0, #0, #9
80028e0: 3b01 subs r3, #1
((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
80028e2: 429a cmp r2, r3
80028e4: f47f ae93 bne.w 800260e <HAL_RCC_OscConfig+0x20e>
((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
80028e8: 6b63 ldr r3, [r4, #52] @ 0x34
80028ea: f3c0 2246 ubfx r2, r0, #9, #7
80028ee: 3b01 subs r3, #1
(READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
80028f0: 429a cmp r2, r3
80028f2: f47f ae8c bne.w 800260e <HAL_RCC_OscConfig+0x20e>
((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
80028f6: 6ba3 ldr r3, [r4, #56] @ 0x38
80028f8: f3c0 4206 ubfx r2, r0, #16, #7
80028fc: 3b01 subs r3, #1
((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
80028fe: 429a cmp r2, r3
8002900: f47f ae85 bne.w 800260e <HAL_RCC_OscConfig+0x20e>
((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U)))
8002904: 6be3 ldr r3, [r4, #60] @ 0x3c
8002906: f3c0 6006 ubfx r0, r0, #24, #7
800290a: 3b01 subs r3, #1
((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
800290c: 4298 cmp r0, r3
800290e: f47f ae7e bne.w 800260e <HAL_RCC_OscConfig+0x20e>
temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos);
8002912: 6b6b ldr r3, [r5, #52] @ 0x34
if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg)
8002914: 6ca2 ldr r2, [r4, #72] @ 0x48
temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos);
8002916: f3c3 03cc ubfx r3, r3, #3, #13
if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg)
800291a: 429a cmp r2, r3
800291c: f43f ae18 beq.w 8002550 <HAL_RCC_OscConfig+0x150>
__HAL_RCC_PLLFRACN_DISABLE();
8002920: 4a2d ldr r2, [pc, #180] @ (80029d8 <HAL_RCC_OscConfig+0x5d8>)
8002922: 6ad3 ldr r3, [r2, #44] @ 0x2c
8002924: f023 0301 bic.w r3, r3, #1
8002928: 62d3 str r3, [r2, #44] @ 0x2c
tickstart = HAL_GetTick();
800292a: f7fe fa55 bl 8000dd8 <HAL_GetTick>
800292e: 4605 mov r5, r0
while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE)
8002930: f7fe fa52 bl 8000dd8 <HAL_GetTick>
8002934: 42a8 cmp r0, r5
8002936: d0fb beq.n 8002930 <HAL_RCC_OscConfig+0x530>
__HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
8002938: 4a27 ldr r2, [pc, #156] @ (80029d8 <HAL_RCC_OscConfig+0x5d8>)
800293a: 6ca1 ldr r1, [r4, #72] @ 0x48
800293c: 6b53 ldr r3, [r2, #52] @ 0x34
800293e: f36f 03cf bfc r3, #3, #13
8002942: ea43 03c1 orr.w r3, r3, r1, lsl #3
8002946: 6353 str r3, [r2, #52] @ 0x34
__HAL_RCC_PLLFRACN_ENABLE();
8002948: 6ad3 ldr r3, [r2, #44] @ 0x2c
800294a: f043 0301 orr.w r3, r3, #1
800294e: 62d3 str r3, [r2, #44] @ 0x2c
8002950: e5fe b.n 8002550 <HAL_RCC_OscConfig+0x150>
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8002952: f442 2280 orr.w r2, r2, #262144 @ 0x40000
8002956: 601a str r2, [r3, #0]
8002958: 681a ldr r2, [r3, #0]
800295a: f442 3280 orr.w r2, r2, #65536 @ 0x10000
800295e: 601a str r2, [r3, #0]
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8002960: e576 b.n 8002450 <HAL_RCC_OscConfig+0x50>
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8002962: 4d1d ldr r5, [pc, #116] @ (80029d8 <HAL_RCC_OscConfig+0x5d8>)
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8002964: f241 3788 movw r7, #5000 @ 0x1388
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8002968: 6f2b ldr r3, [r5, #112] @ 0x70
800296a: f023 0301 bic.w r3, r3, #1
800296e: 672b str r3, [r5, #112] @ 0x70
8002970: 6f2b ldr r3, [r5, #112] @ 0x70
8002972: f023 0304 bic.w r3, r3, #4
8002976: 672b str r3, [r5, #112] @ 0x70
tickstart = HAL_GetTick();
8002978: f7fe fa2e bl 8000dd8 <HAL_GetTick>
800297c: 4606 mov r6, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
800297e: e005 b.n 800298c <HAL_RCC_OscConfig+0x58c>
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8002980: f7fe fa2a bl 8000dd8 <HAL_GetTick>
8002984: 1b80 subs r0, r0, r6
8002986: 42b8 cmp r0, r7
8002988: f63f aeba bhi.w 8002700 <HAL_RCC_OscConfig+0x300>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
800298c: 6f2b ldr r3, [r5, #112] @ 0x70
800298e: 0798 lsls r0, r3, #30
8002990: d4f6 bmi.n 8002980 <HAL_RCC_OscConfig+0x580>
8002992: e5d9 b.n 8002548 <HAL_RCC_OscConfig+0x148>
__HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
8002994: 68eb ldr r3, [r5, #12]
8002996: 6a22 ldr r2, [r4, #32]
8002998: f023 537c bic.w r3, r3, #1056964608 @ 0x3f000000
800299c: ea43 6302 orr.w r3, r3, r2, lsl #24
80029a0: 60eb str r3, [r5, #12]
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80029a2: 6823 ldr r3, [r4, #0]
80029a4: e59b b.n 80024de <HAL_RCC_OscConfig+0xde>
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80029a6: 4a0c ldr r2, [pc, #48] @ (80029d8 <HAL_RCC_OscConfig+0x5d8>)
80029a8: 6f13 ldr r3, [r2, #112] @ 0x70
80029aa: f043 0301 orr.w r3, r3, #1
80029ae: 6713 str r3, [r2, #112] @ 0x70
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
80029b0: e67d b.n 80026ae <HAL_RCC_OscConfig+0x2ae>
__HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
80029b2: 4a09 ldr r2, [pc, #36] @ (80029d8 <HAL_RCC_OscConfig+0x5d8>)
80029b4: 6853 ldr r3, [r2, #4]
80029b6: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000
80029ba: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
80029be: 6053 str r3, [r2, #4]
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80029c0: 6823 ldr r3, [r4, #0]
80029c2: e58c b.n 80024de <HAL_RCC_OscConfig+0xde>
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80029c4: f042 0204 orr.w r2, r2, #4
80029c8: 671a str r2, [r3, #112] @ 0x70
80029ca: 6f1a ldr r2, [r3, #112] @ 0x70
80029cc: f042 0201 orr.w r2, r2, #1
80029d0: 671a str r2, [r3, #112] @ 0x70
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
80029d2: e66c b.n 80026ae <HAL_RCC_OscConfig+0x2ae>
return HAL_ERROR;
80029d4: 2001 movs r0, #1
}
80029d6: 4770 bx lr
80029d8: 58024400 .word 0x58024400
080029dc <HAL_RCC_GetSysClockFreq>:
switch (RCC->CFGR & RCC_CFGR_SWS)
80029dc: 4a3f ldr r2, [pc, #252] @ (8002adc <HAL_RCC_GetSysClockFreq+0x100>)
80029de: 6913 ldr r3, [r2, #16]
80029e0: f003 0338 and.w r3, r3, #56 @ 0x38
80029e4: 2b10 cmp r3, #16
80029e6: d04f beq.n 8002a88 <HAL_RCC_GetSysClockFreq+0xac>
80029e8: 2b18 cmp r3, #24
80029ea: d00a beq.n 8002a02 <HAL_RCC_GetSysClockFreq+0x26>
80029ec: 2b00 cmp r3, #0
80029ee: d14d bne.n 8002a8c <HAL_RCC_GetSysClockFreq+0xb0>
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
80029f0: 6813 ldr r3, [r2, #0]
80029f2: 0699 lsls r1, r3, #26
80029f4: d54c bpl.n 8002a90 <HAL_RCC_GetSysClockFreq+0xb4>
sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
80029f6: 6813 ldr r3, [r2, #0]
80029f8: 4839 ldr r0, [pc, #228] @ (8002ae0 <HAL_RCC_GetSysClockFreq+0x104>)
80029fa: f3c3 03c1 ubfx r3, r3, #3, #2
80029fe: 40d8 lsrs r0, r3
8002a00: 4770 bx lr
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
8002a02: 6a91 ldr r1, [r2, #40] @ 0x28
{
8002a04: b430 push {r4, r5}
pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ;
8002a06: 6a94 ldr r4, [r2, #40] @ 0x28
pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
8002a08: 6ad5 ldr r5, [r2, #44] @ 0x2c
if (pllm != 0U)
8002a0a: f414 7f7c tst.w r4, #1008 @ 0x3f0
fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
8002a0e: 6b53 ldr r3, [r2, #52] @ 0x34
pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ;
8002a10: f3c4 1005 ubfx r0, r4, #4, #6
if (pllm != 0U)
8002a14: d036 beq.n 8002a84 <HAL_RCC_GetSysClockFreq+0xa8>
fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
8002a16: f3c3 03cc ubfx r3, r3, #3, #13
pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
8002a1a: f005 0501 and.w r5, r5, #1
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
8002a1e: f001 0103 and.w r1, r1, #3
pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
8002a22: ee07 0a90 vmov s15, r0
fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
8002a26: fb05 f303 mul.w r3, r5, r3
switch (pllsource)
8002a2a: 2901 cmp r1, #1
pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
8002a2c: eef8 7ae7 vcvt.f32.s32 s15, s15
8002a30: ee06 3a90 vmov s13, r3
8002a34: eefa 6ae9 vcvt.f32.s32 s13, s13, #13
switch (pllsource)
8002a38: d002 beq.n 8002a40 <HAL_RCC_GetSysClockFreq+0x64>
8002a3a: 2902 cmp r1, #2
8002a3c: d048 beq.n 8002ad0 <HAL_RCC_GetSysClockFreq+0xf4>
8002a3e: b349 cbz r1, 8002a94 <HAL_RCC_GetSysClockFreq+0xb8>
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
8002a40: ed9f 7a28 vldr s14, [pc, #160] @ 8002ae4 <HAL_RCC_GetSysClockFreq+0x108>
8002a44: ee87 6a27 vdiv.f32 s12, s14, s15
8002a48: 6b13 ldr r3, [r2, #48] @ 0x30
8002a4a: f3c3 0308 ubfx r3, r3, #0, #9
8002a4e: ee07 3a10 vmov s14, r3
8002a52: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
8002a56: eeb8 7ac7 vcvt.f32.s32 s14, s14
8002a5a: ee37 7a26 vadd.f32 s14, s14, s13
8002a5e: ee37 7a25 vadd.f32 s14, s14, s11
8002a62: ee27 7a06 vmul.f32 s14, s14, s12
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ;
8002a66: 4b1d ldr r3, [pc, #116] @ (8002adc <HAL_RCC_GetSysClockFreq+0x100>)
8002a68: 6b1b ldr r3, [r3, #48] @ 0x30
8002a6a: f3c3 2346 ubfx r3, r3, #9, #7
8002a6e: 3301 adds r3, #1
sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp);
8002a70: ee07 3a90 vmov s15, r3
8002a74: eef8 6ae7 vcvt.f32.s32 s13, s15
8002a78: eec7 7a26 vdiv.f32 s15, s14, s13
8002a7c: eefc 7ae7 vcvt.u32.f32 s15, s15
8002a80: ee17 0a90 vmov r0, s15
}
8002a84: bc30 pop {r4, r5}
8002a86: 4770 bx lr
switch (RCC->CFGR & RCC_CFGR_SWS)
8002a88: 4817 ldr r0, [pc, #92] @ (8002ae8 <HAL_RCC_GetSysClockFreq+0x10c>)
8002a8a: 4770 bx lr
sysclockfreq = CSI_VALUE;
8002a8c: 4817 ldr r0, [pc, #92] @ (8002aec <HAL_RCC_GetSysClockFreq+0x110>)
8002a8e: 4770 bx lr
sysclockfreq = (uint32_t) HSI_VALUE;
8002a90: 4813 ldr r0, [pc, #76] @ (8002ae0 <HAL_RCC_GetSysClockFreq+0x104>)
}
8002a92: 4770 bx lr
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
8002a94: 6813 ldr r3, [r2, #0]
8002a96: 069b lsls r3, r3, #26
8002a98: d51d bpl.n 8002ad6 <HAL_RCC_GetSysClockFreq+0xfa>
hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
8002a9a: 6810 ldr r0, [r2, #0]
pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
8002a9c: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
8002aa0: 6b13 ldr r3, [r2, #48] @ 0x30
hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
8002aa2: 490f ldr r1, [pc, #60] @ (8002ae0 <HAL_RCC_GetSysClockFreq+0x104>)
8002aa4: f3c0 02c1 ubfx r2, r0, #3, #2
pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
8002aa8: f3c3 0308 ubfx r3, r3, #0, #9
hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
8002aac: 40d1 lsrs r1, r2
pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
8002aae: ee07 3a10 vmov s14, r3
8002ab2: ee06 1a10 vmov s12, r1
8002ab6: eeb8 7ac7 vcvt.f32.s32 s14, s14
8002aba: eeb8 6ac6 vcvt.f32.s32 s12, s12
8002abe: ee77 6a26 vadd.f32 s13, s14, s13
8002ac2: ee86 7a27 vdiv.f32 s14, s12, s15
8002ac6: ee76 7aa5 vadd.f32 s15, s13, s11
8002aca: ee27 7a27 vmul.f32 s14, s14, s15
8002ace: e7ca b.n 8002a66 <HAL_RCC_GetSysClockFreq+0x8a>
pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
8002ad0: ed9f 7a07 vldr s14, [pc, #28] @ 8002af0 <HAL_RCC_GetSysClockFreq+0x114>
8002ad4: e7b6 b.n 8002a44 <HAL_RCC_GetSysClockFreq+0x68>
pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
8002ad6: ed9f 7a07 vldr s14, [pc, #28] @ 8002af4 <HAL_RCC_GetSysClockFreq+0x118>
8002ada: e7b3 b.n 8002a44 <HAL_RCC_GetSysClockFreq+0x68>
8002adc: 58024400 .word 0x58024400
8002ae0: 03d09000 .word 0x03d09000
8002ae4: 4a742400 .word 0x4a742400
8002ae8: 017d7840 .word 0x017d7840
8002aec: 003d0900 .word 0x003d0900
8002af0: 4bbebc20 .word 0x4bbebc20
8002af4: 4c742400 .word 0x4c742400
08002af8 <HAL_RCC_ClockConfig>:
if (RCC_ClkInitStruct == NULL)
8002af8: 2800 cmp r0, #0
8002afa: f000 810e beq.w 8002d1a <HAL_RCC_ClockConfig+0x222>
if (FLatency > __HAL_FLASH_GET_LATENCY())
8002afe: 4a8d ldr r2, [pc, #564] @ (8002d34 <HAL_RCC_ClockConfig+0x23c>)
8002b00: 6813 ldr r3, [r2, #0]
8002b02: f003 030f and.w r3, r3, #15
8002b06: 428b cmp r3, r1
{
8002b08: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
8002b0c: 4604 mov r4, r0
8002b0e: 460d mov r5, r1
if (FLatency > __HAL_FLASH_GET_LATENCY())
8002b10: d20c bcs.n 8002b2c <HAL_RCC_ClockConfig+0x34>
__HAL_FLASH_SET_LATENCY(FLatency);
8002b12: 6813 ldr r3, [r2, #0]
8002b14: f023 030f bic.w r3, r3, #15
8002b18: 430b orrs r3, r1
8002b1a: 6013 str r3, [r2, #0]
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8002b1c: 6813 ldr r3, [r2, #0]
8002b1e: f003 030f and.w r3, r3, #15
8002b22: 428b cmp r3, r1
8002b24: d002 beq.n 8002b2c <HAL_RCC_ClockConfig+0x34>
return HAL_ERROR;
8002b26: 2001 movs r0, #1
}
8002b28: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
8002b2c: 6823 ldr r3, [r4, #0]
8002b2e: 0758 lsls r0, r3, #29
8002b30: d50b bpl.n 8002b4a <HAL_RCC_ClockConfig+0x52>
if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
8002b32: 4981 ldr r1, [pc, #516] @ (8002d38 <HAL_RCC_ClockConfig+0x240>)
8002b34: 6920 ldr r0, [r4, #16]
8002b36: 698a ldr r2, [r1, #24]
8002b38: f002 0270 and.w r2, r2, #112 @ 0x70
8002b3c: 4290 cmp r0, r2
8002b3e: d904 bls.n 8002b4a <HAL_RCC_ClockConfig+0x52>
MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
8002b40: 698a ldr r2, [r1, #24]
8002b42: f022 0270 bic.w r2, r2, #112 @ 0x70
8002b46: 4302 orrs r2, r0
8002b48: 618a str r2, [r1, #24]
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8002b4a: 0719 lsls r1, r3, #28
8002b4c: d50b bpl.n 8002b66 <HAL_RCC_ClockConfig+0x6e>
if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
8002b4e: 497a ldr r1, [pc, #488] @ (8002d38 <HAL_RCC_ClockConfig+0x240>)
8002b50: 6960 ldr r0, [r4, #20]
8002b52: 69ca ldr r2, [r1, #28]
8002b54: f002 0270 and.w r2, r2, #112 @ 0x70
8002b58: 4290 cmp r0, r2
8002b5a: d904 bls.n 8002b66 <HAL_RCC_ClockConfig+0x6e>
MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
8002b5c: 69ca ldr r2, [r1, #28]
8002b5e: f022 0270 bic.w r2, r2, #112 @ 0x70
8002b62: 4302 orrs r2, r0
8002b64: 61ca str r2, [r1, #28]
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8002b66: 06da lsls r2, r3, #27
8002b68: d50b bpl.n 8002b82 <HAL_RCC_ClockConfig+0x8a>
if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
8002b6a: 4973 ldr r1, [pc, #460] @ (8002d38 <HAL_RCC_ClockConfig+0x240>)
8002b6c: 69a0 ldr r0, [r4, #24]
8002b6e: 69ca ldr r2, [r1, #28]
8002b70: f402 62e0 and.w r2, r2, #1792 @ 0x700
8002b74: 4290 cmp r0, r2
8002b76: d904 bls.n 8002b82 <HAL_RCC_ClockConfig+0x8a>
MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
8002b78: 69ca ldr r2, [r1, #28]
8002b7a: f422 62e0 bic.w r2, r2, #1792 @ 0x700
8002b7e: 4302 orrs r2, r0
8002b80: 61ca str r2, [r1, #28]
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
8002b82: 069f lsls r7, r3, #26
8002b84: d50b bpl.n 8002b9e <HAL_RCC_ClockConfig+0xa6>
if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
8002b86: 496c ldr r1, [pc, #432] @ (8002d38 <HAL_RCC_ClockConfig+0x240>)
8002b88: 69e0 ldr r0, [r4, #28]
8002b8a: 6a0a ldr r2, [r1, #32]
8002b8c: f002 0270 and.w r2, r2, #112 @ 0x70
8002b90: 4290 cmp r0, r2
8002b92: d904 bls.n 8002b9e <HAL_RCC_ClockConfig+0xa6>
MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider));
8002b94: 6a0a ldr r2, [r1, #32]
8002b96: f022 0270 bic.w r2, r2, #112 @ 0x70
8002b9a: 4302 orrs r2, r0
8002b9c: 620a str r2, [r1, #32]
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8002b9e: 079e lsls r6, r3, #30
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8002ba0: f003 0201 and.w r2, r3, #1
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8002ba4: f140 80ab bpl.w 8002cfe <HAL_RCC_ClockConfig+0x206>
if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE))
8002ba8: 4e63 ldr r6, [pc, #396] @ (8002d38 <HAL_RCC_ClockConfig+0x240>)
8002baa: 68e0 ldr r0, [r4, #12]
8002bac: 69b1 ldr r1, [r6, #24]
8002bae: f001 010f and.w r1, r1, #15
8002bb2: 4288 cmp r0, r1
8002bb4: d904 bls.n 8002bc0 <HAL_RCC_ClockConfig+0xc8>
MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8002bb6: 69b1 ldr r1, [r6, #24]
8002bb8: f021 010f bic.w r1, r1, #15
8002bbc: 4301 orrs r1, r0
8002bbe: 61b1 str r1, [r6, #24]
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8002bc0: 2a00 cmp r2, #0
8002bc2: d030 beq.n 8002c26 <HAL_RCC_ClockConfig+0x12e>
MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider);
8002bc4: 4a5c ldr r2, [pc, #368] @ (8002d38 <HAL_RCC_ClockConfig+0x240>)
8002bc6: 68a1 ldr r1, [r4, #8]
8002bc8: 6993 ldr r3, [r2, #24]
8002bca: f423 6370 bic.w r3, r3, #3840 @ 0xf00
8002bce: 430b orrs r3, r1
8002bd0: 6193 str r3, [r2, #24]
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8002bd2: 6861 ldr r1, [r4, #4]
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
8002bd4: 6813 ldr r3, [r2, #0]
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8002bd6: 2902 cmp r1, #2
8002bd8: f000 80a1 beq.w 8002d1e <HAL_RCC_ClockConfig+0x226>
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8002bdc: 2903 cmp r1, #3
8002bde: f000 8098 beq.w 8002d12 <HAL_RCC_ClockConfig+0x21a>
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)
8002be2: 2901 cmp r1, #1
8002be4: f000 80a1 beq.w 8002d2a <HAL_RCC_ClockConfig+0x232>
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
8002be8: 075f lsls r7, r3, #29
8002bea: d59c bpl.n 8002b26 <HAL_RCC_ClockConfig+0x2e>
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
8002bec: 4e52 ldr r6, [pc, #328] @ (8002d38 <HAL_RCC_ClockConfig+0x240>)
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8002bee: f241 3888 movw r8, #5000 @ 0x1388
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
8002bf2: 6933 ldr r3, [r6, #16]
8002bf4: f023 0307 bic.w r3, r3, #7
8002bf8: 430b orrs r3, r1
8002bfa: 6133 str r3, [r6, #16]
tickstart = HAL_GetTick();
8002bfc: f7fe f8ec bl 8000dd8 <HAL_GetTick>
8002c00: 4607 mov r7, r0
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8002c02: e005 b.n 8002c10 <HAL_RCC_ClockConfig+0x118>
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8002c04: f7fe f8e8 bl 8000dd8 <HAL_GetTick>
8002c08: 1bc0 subs r0, r0, r7
8002c0a: 4540 cmp r0, r8
8002c0c: f200 808b bhi.w 8002d26 <HAL_RCC_ClockConfig+0x22e>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8002c10: 6933 ldr r3, [r6, #16]
8002c12: 6862 ldr r2, [r4, #4]
8002c14: f003 0338 and.w r3, r3, #56 @ 0x38
8002c18: ebb3 0fc2 cmp.w r3, r2, lsl #3
8002c1c: d1f2 bne.n 8002c04 <HAL_RCC_ClockConfig+0x10c>
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8002c1e: 6823 ldr r3, [r4, #0]
8002c20: 079e lsls r6, r3, #30
8002c22: d506 bpl.n 8002c32 <HAL_RCC_ClockConfig+0x13a>
if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE))
8002c24: 68e0 ldr r0, [r4, #12]
8002c26: 4944 ldr r1, [pc, #272] @ (8002d38 <HAL_RCC_ClockConfig+0x240>)
8002c28: 698a ldr r2, [r1, #24]
8002c2a: f002 020f and.w r2, r2, #15
8002c2e: 4290 cmp r0, r2
8002c30: d369 bcc.n 8002d06 <HAL_RCC_ClockConfig+0x20e>
if (FLatency < __HAL_FLASH_GET_LATENCY())
8002c32: 4940 ldr r1, [pc, #256] @ (8002d34 <HAL_RCC_ClockConfig+0x23c>)
8002c34: 680a ldr r2, [r1, #0]
8002c36: f002 020f and.w r2, r2, #15
8002c3a: 42aa cmp r2, r5
8002c3c: d90a bls.n 8002c54 <HAL_RCC_ClockConfig+0x15c>
__HAL_FLASH_SET_LATENCY(FLatency);
8002c3e: 680a ldr r2, [r1, #0]
8002c40: f022 020f bic.w r2, r2, #15
8002c44: 432a orrs r2, r5
8002c46: 600a str r2, [r1, #0]
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8002c48: 680a ldr r2, [r1, #0]
8002c4a: f002 020f and.w r2, r2, #15
8002c4e: 42aa cmp r2, r5
8002c50: f47f af69 bne.w 8002b26 <HAL_RCC_ClockConfig+0x2e>
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
8002c54: 0758 lsls r0, r3, #29
8002c56: d50b bpl.n 8002c70 <HAL_RCC_ClockConfig+0x178>
if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
8002c58: 4937 ldr r1, [pc, #220] @ (8002d38 <HAL_RCC_ClockConfig+0x240>)
8002c5a: 6920 ldr r0, [r4, #16]
8002c5c: 698a ldr r2, [r1, #24]
8002c5e: f002 0270 and.w r2, r2, #112 @ 0x70
8002c62: 4290 cmp r0, r2
8002c64: d204 bcs.n 8002c70 <HAL_RCC_ClockConfig+0x178>
MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
8002c66: 698a ldr r2, [r1, #24]
8002c68: f022 0270 bic.w r2, r2, #112 @ 0x70
8002c6c: 4302 orrs r2, r0
8002c6e: 618a str r2, [r1, #24]
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8002c70: 0719 lsls r1, r3, #28
8002c72: d50b bpl.n 8002c8c <HAL_RCC_ClockConfig+0x194>
if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
8002c74: 4930 ldr r1, [pc, #192] @ (8002d38 <HAL_RCC_ClockConfig+0x240>)
8002c76: 6960 ldr r0, [r4, #20]
8002c78: 69ca ldr r2, [r1, #28]
8002c7a: f002 0270 and.w r2, r2, #112 @ 0x70
8002c7e: 4290 cmp r0, r2
8002c80: d204 bcs.n 8002c8c <HAL_RCC_ClockConfig+0x194>
MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
8002c82: 69ca ldr r2, [r1, #28]
8002c84: f022 0270 bic.w r2, r2, #112 @ 0x70
8002c88: 4302 orrs r2, r0
8002c8a: 61ca str r2, [r1, #28]
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8002c8c: 06da lsls r2, r3, #27
8002c8e: d50b bpl.n 8002ca8 <HAL_RCC_ClockConfig+0x1b0>
if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
8002c90: 4929 ldr r1, [pc, #164] @ (8002d38 <HAL_RCC_ClockConfig+0x240>)
8002c92: 69a0 ldr r0, [r4, #24]
8002c94: 69ca ldr r2, [r1, #28]
8002c96: f402 62e0 and.w r2, r2, #1792 @ 0x700
8002c9a: 4290 cmp r0, r2
8002c9c: d204 bcs.n 8002ca8 <HAL_RCC_ClockConfig+0x1b0>
MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
8002c9e: 69ca ldr r2, [r1, #28]
8002ca0: f422 62e0 bic.w r2, r2, #1792 @ 0x700
8002ca4: 4302 orrs r2, r0
8002ca6: 61ca str r2, [r1, #28]
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
8002ca8: 069b lsls r3, r3, #26
8002caa: d50b bpl.n 8002cc4 <HAL_RCC_ClockConfig+0x1cc>
if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
8002cac: 4a22 ldr r2, [pc, #136] @ (8002d38 <HAL_RCC_ClockConfig+0x240>)
8002cae: 69e1 ldr r1, [r4, #28]
8002cb0: 6a13 ldr r3, [r2, #32]
8002cb2: f003 0370 and.w r3, r3, #112 @ 0x70
8002cb6: 4299 cmp r1, r3
8002cb8: d204 bcs.n 8002cc4 <HAL_RCC_ClockConfig+0x1cc>
MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider));
8002cba: 6a13 ldr r3, [r2, #32]
8002cbc: f023 0370 bic.w r3, r3, #112 @ 0x70
8002cc0: 430b orrs r3, r1
8002cc2: 6213 str r3, [r2, #32]
common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
8002cc4: f7ff fe8a bl 80029dc <HAL_RCC_GetSysClockFreq>
8002cc8: 4a1b ldr r2, [pc, #108] @ (8002d38 <HAL_RCC_ClockConfig+0x240>)
8002cca: 4603 mov r3, r0
8002ccc: 481b ldr r0, [pc, #108] @ (8002d3c <HAL_RCC_ClockConfig+0x244>)
8002cce: 6991 ldr r1, [r2, #24]
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
8002cd0: 6992 ldr r2, [r2, #24]
common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
8002cd2: f3c1 2103 ubfx r1, r1, #8, #4
SystemCoreClock = common_system_clock;
8002cd6: 4d1a ldr r5, [pc, #104] @ (8002d40 <HAL_RCC_ClockConfig+0x248>)
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
8002cd8: f002 020f and.w r2, r2, #15
8002cdc: 4c19 ldr r4, [pc, #100] @ (8002d44 <HAL_RCC_ClockConfig+0x24c>)
common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
8002cde: 5c41 ldrb r1, [r0, r1]
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
8002ce0: 5c82 ldrb r2, [r0, r2]
common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
8002ce2: f001 011f and.w r1, r1, #31
halstatus = HAL_InitTick(uwTickPrio);
8002ce6: 4818 ldr r0, [pc, #96] @ (8002d48 <HAL_RCC_ClockConfig+0x250>)
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
8002ce8: f002 021f and.w r2, r2, #31
common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
8002cec: 40cb lsrs r3, r1
halstatus = HAL_InitTick(uwTickPrio);
8002cee: 6800 ldr r0, [r0, #0]
SystemCoreClock = common_system_clock;
8002cf0: 602b str r3, [r5, #0]
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
8002cf2: 40d3 lsrs r3, r2
8002cf4: 6023 str r3, [r4, #0]
}
8002cf6: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
halstatus = HAL_InitTick(uwTickPrio);
8002cfa: f7fe b80b b.w 8000d14 <HAL_InitTick>
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8002cfe: 2a00 cmp r2, #0
8002d00: f47f af60 bne.w 8002bc4 <HAL_RCC_ClockConfig+0xcc>
8002d04: e795 b.n 8002c32 <HAL_RCC_ClockConfig+0x13a>
MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8002d06: 698a ldr r2, [r1, #24]
8002d08: f022 020f bic.w r2, r2, #15
8002d0c: 4302 orrs r2, r0
8002d0e: 618a str r2, [r1, #24]
8002d10: e78f b.n 8002c32 <HAL_RCC_ClockConfig+0x13a>
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
8002d12: 019a lsls r2, r3, #6
8002d14: f53f af6a bmi.w 8002bec <HAL_RCC_ClockConfig+0xf4>
8002d18: e705 b.n 8002b26 <HAL_RCC_ClockConfig+0x2e>
return HAL_ERROR;
8002d1a: 2001 movs r0, #1
}
8002d1c: 4770 bx lr
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
8002d1e: 0398 lsls r0, r3, #14
8002d20: f53f af64 bmi.w 8002bec <HAL_RCC_ClockConfig+0xf4>
8002d24: e6ff b.n 8002b26 <HAL_RCC_ClockConfig+0x2e>
return HAL_TIMEOUT;
8002d26: 2003 movs r0, #3
8002d28: e6fe b.n 8002b28 <HAL_RCC_ClockConfig+0x30>
if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
8002d2a: 05db lsls r3, r3, #23
8002d2c: f53f af5e bmi.w 8002bec <HAL_RCC_ClockConfig+0xf4>
8002d30: e6f9 b.n 8002b26 <HAL_RCC_ClockConfig+0x2e>
8002d32: bf00 nop
8002d34: 52002000 .word 0x52002000
8002d38: 58024400 .word 0x58024400
8002d3c: 08005618 .word 0x08005618
8002d40: 24000004 .word 0x24000004
8002d44: 24000000 .word 0x24000000
8002d48: 2400000c .word 0x2400000c
08002d4c <HAL_RCC_GetHCLKFreq>:
switch (RCC->CFGR & RCC_CFGR_SWS)
8002d4c: 4a18 ldr r2, [pc, #96] @ (8002db0 <HAL_RCC_GetHCLKFreq+0x64>)
* @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8002d4e: b538 push {r3, r4, r5, lr}
switch (RCC->CFGR & RCC_CFGR_SWS)
8002d50: 6913 ldr r3, [r2, #16]
8002d52: f003 0338 and.w r3, r3, #56 @ 0x38
8002d56: 2b10 cmp r3, #16
8002d58: d024 beq.n 8002da4 <HAL_RCC_GetHCLKFreq+0x58>
8002d5a: 2b18 cmp r3, #24
8002d5c: d009 beq.n 8002d72 <HAL_RCC_GetHCLKFreq+0x26>
8002d5e: bb1b cbnz r3, 8002da8 <HAL_RCC_GetHCLKFreq+0x5c>
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
8002d60: 6813 ldr r3, [r2, #0]
8002d62: 069b lsls r3, r3, #26
8002d64: d522 bpl.n 8002dac <HAL_RCC_GetHCLKFreq+0x60>
sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
8002d66: 6812 ldr r2, [r2, #0]
8002d68: 4b12 ldr r3, [pc, #72] @ (8002db4 <HAL_RCC_GetHCLKFreq+0x68>)
8002d6a: f3c2 02c1 ubfx r2, r2, #3, #2
8002d6e: 40d3 lsrs r3, r2
8002d70: e002 b.n 8002d78 <HAL_RCC_GetHCLKFreq+0x2c>
8002d72: f7ff fad3 bl 800231c <HAL_RCC_GetSysClockFreq.part.0>
8002d76: 4603 mov r3, r0
uint32_t common_system_clock;
#if defined(RCC_D1CFGR_D1CPRE)
common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
8002d78: 490d ldr r1, [pc, #52] @ (8002db0 <HAL_RCC_GetHCLKFreq+0x64>)
8002d7a: 480f ldr r0, [pc, #60] @ (8002db8 <HAL_RCC_GetHCLKFreq+0x6c>)
8002d7c: 698a ldr r2, [r1, #24]
#else
common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
#endif
#if defined(RCC_D1CFGR_HPRE)
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
8002d7e: 6989 ldr r1, [r1, #24]
common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
8002d80: f3c2 2203 ubfx r2, r2, #8, #4
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
8002d84: 4c0d ldr r4, [pc, #52] @ (8002dbc <HAL_RCC_GetHCLKFreq+0x70>)
8002d86: f001 010f and.w r1, r1, #15
#endif
#if defined(DUAL_CORE) && defined(CORE_CM4)
SystemCoreClock = SystemD2Clock;
#else
SystemCoreClock = common_system_clock;
8002d8a: 4d0d ldr r5, [pc, #52] @ (8002dc0 <HAL_RCC_GetHCLKFreq+0x74>)
common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
8002d8c: 5c82 ldrb r2, [r0, r2]
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
8002d8e: 5c40 ldrb r0, [r0, r1]
common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
8002d90: f002 021f and.w r2, r2, #31
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
8002d94: f000 001f and.w r0, r0, #31
common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
8002d98: 40d3 lsrs r3, r2
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
8002d9a: fa23 f000 lsr.w r0, r3, r0
SystemCoreClock = common_system_clock;
8002d9e: 602b str r3, [r5, #0]
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
8002da0: 6020 str r0, [r4, #0]
#endif /* DUAL_CORE && CORE_CM4 */
return SystemD2Clock;
}
8002da2: bd38 pop {r3, r4, r5, pc}
switch (RCC->CFGR & RCC_CFGR_SWS)
8002da4: 4b07 ldr r3, [pc, #28] @ (8002dc4 <HAL_RCC_GetHCLKFreq+0x78>)
8002da6: e7e7 b.n 8002d78 <HAL_RCC_GetHCLKFreq+0x2c>
sysclockfreq = CSI_VALUE;
8002da8: 4b07 ldr r3, [pc, #28] @ (8002dc8 <HAL_RCC_GetHCLKFreq+0x7c>)
8002daa: e7e5 b.n 8002d78 <HAL_RCC_GetHCLKFreq+0x2c>
sysclockfreq = (uint32_t) HSI_VALUE;
8002dac: 4b01 ldr r3, [pc, #4] @ (8002db4 <HAL_RCC_GetHCLKFreq+0x68>)
8002dae: e7e3 b.n 8002d78 <HAL_RCC_GetHCLKFreq+0x2c>
8002db0: 58024400 .word 0x58024400
8002db4: 03d09000 .word 0x03d09000
8002db8: 08005618 .word 0x08005618
8002dbc: 24000000 .word 0x24000000
8002dc0: 24000004 .word 0x24000004
8002dc4: 017d7840 .word 0x017d7840
8002dc8: 003d0900 .word 0x003d0900
08002dcc <HAL_RCC_GetPCLK1Freq>:
switch (RCC->CFGR & RCC_CFGR_SWS)
8002dcc: 4a1c ldr r2, [pc, #112] @ (8002e40 <HAL_RCC_GetPCLK1Freq+0x74>)
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8002dce: b538 push {r3, r4, r5, lr}
switch (RCC->CFGR & RCC_CFGR_SWS)
8002dd0: 6913 ldr r3, [r2, #16]
8002dd2: f003 0338 and.w r3, r3, #56 @ 0x38
8002dd6: 2b10 cmp r3, #16
8002dd8: d02b beq.n 8002e32 <HAL_RCC_GetPCLK1Freq+0x66>
8002dda: 2b18 cmp r3, #24
8002ddc: d009 beq.n 8002df2 <HAL_RCC_GetPCLK1Freq+0x26>
8002dde: bb53 cbnz r3, 8002e36 <HAL_RCC_GetPCLK1Freq+0x6a>
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
8002de0: 6813 ldr r3, [r2, #0]
8002de2: 069b lsls r3, r3, #26
8002de4: d529 bpl.n 8002e3a <HAL_RCC_GetPCLK1Freq+0x6e>
sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
8002de6: 6812 ldr r2, [r2, #0]
8002de8: 4b16 ldr r3, [pc, #88] @ (8002e44 <HAL_RCC_GetPCLK1Freq+0x78>)
8002dea: f3c2 02c1 ubfx r2, r2, #3, #2
8002dee: 40d3 lsrs r3, r2
8002df0: e002 b.n 8002df8 <HAL_RCC_GetPCLK1Freq+0x2c>
8002df2: f7ff fa93 bl 800231c <HAL_RCC_GetSysClockFreq.part.0>
8002df6: 4603 mov r3, r0
common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
8002df8: 4a11 ldr r2, [pc, #68] @ (8002e40 <HAL_RCC_GetPCLK1Freq+0x74>)
8002dfa: 4913 ldr r1, [pc, #76] @ (8002e48 <HAL_RCC_GetPCLK1Freq+0x7c>)
8002dfc: 6990 ldr r0, [r2, #24]
SystemCoreClock = common_system_clock;
8002dfe: 4d13 ldr r5, [pc, #76] @ (8002e4c <HAL_RCC_GetPCLK1Freq+0x80>)
common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
8002e00: f3c0 2003 ubfx r0, r0, #8, #4
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
8002e04: 4c12 ldr r4, [pc, #72] @ (8002e50 <HAL_RCC_GetPCLK1Freq+0x84>)
common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
8002e06: 5c08 ldrb r0, [r1, r0]
8002e08: f000 001f and.w r0, r0, #31
8002e0c: 40c3 lsrs r3, r0
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
8002e0e: 6990 ldr r0, [r2, #24]
8002e10: f000 000f and.w r0, r0, #15
SystemCoreClock = common_system_clock;
8002e14: 602b str r3, [r5, #0]
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
8002e16: 5c08 ldrb r0, [r1, r0]
8002e18: f000 001f and.w r0, r0, #31
8002e1c: 40c3 lsrs r3, r0
8002e1e: 6023 str r3, [r4, #0]
#if defined (RCC_D2CFGR_D2PPRE1)
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU));
8002e20: 69d2 ldr r2, [r2, #28]
8002e22: f3c2 1202 ubfx r2, r2, #4, #3
8002e26: 5c88 ldrb r0, [r1, r2]
8002e28: f000 001f and.w r0, r0, #31
#else
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU));
#endif
}
8002e2c: fa23 f000 lsr.w r0, r3, r0
8002e30: bd38 pop {r3, r4, r5, pc}
switch (RCC->CFGR & RCC_CFGR_SWS)
8002e32: 4b08 ldr r3, [pc, #32] @ (8002e54 <HAL_RCC_GetPCLK1Freq+0x88>)
8002e34: e7e0 b.n 8002df8 <HAL_RCC_GetPCLK1Freq+0x2c>
sysclockfreq = CSI_VALUE;
8002e36: 4b08 ldr r3, [pc, #32] @ (8002e58 <HAL_RCC_GetPCLK1Freq+0x8c>)
8002e38: e7de b.n 8002df8 <HAL_RCC_GetPCLK1Freq+0x2c>
sysclockfreq = (uint32_t) HSI_VALUE;
8002e3a: 4b02 ldr r3, [pc, #8] @ (8002e44 <HAL_RCC_GetPCLK1Freq+0x78>)
8002e3c: e7dc b.n 8002df8 <HAL_RCC_GetPCLK1Freq+0x2c>
8002e3e: bf00 nop
8002e40: 58024400 .word 0x58024400
8002e44: 03d09000 .word 0x03d09000
8002e48: 08005618 .word 0x08005618
8002e4c: 24000004 .word 0x24000004
8002e50: 24000000 .word 0x24000000
8002e54: 017d7840 .word 0x017d7840
8002e58: 003d0900 .word 0x003d0900
08002e5c <HAL_RCC_GetPCLK2Freq>:
switch (RCC->CFGR & RCC_CFGR_SWS)
8002e5c: 4a1c ldr r2, [pc, #112] @ (8002ed0 <HAL_RCC_GetPCLK2Freq+0x74>)
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8002e5e: b538 push {r3, r4, r5, lr}
switch (RCC->CFGR & RCC_CFGR_SWS)
8002e60: 6913 ldr r3, [r2, #16]
8002e62: f003 0338 and.w r3, r3, #56 @ 0x38
8002e66: 2b10 cmp r3, #16
8002e68: d02b beq.n 8002ec2 <HAL_RCC_GetPCLK2Freq+0x66>
8002e6a: 2b18 cmp r3, #24
8002e6c: d009 beq.n 8002e82 <HAL_RCC_GetPCLK2Freq+0x26>
8002e6e: bb53 cbnz r3, 8002ec6 <HAL_RCC_GetPCLK2Freq+0x6a>
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
8002e70: 6813 ldr r3, [r2, #0]
8002e72: 069b lsls r3, r3, #26
8002e74: d529 bpl.n 8002eca <HAL_RCC_GetPCLK2Freq+0x6e>
sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
8002e76: 6812 ldr r2, [r2, #0]
8002e78: 4b16 ldr r3, [pc, #88] @ (8002ed4 <HAL_RCC_GetPCLK2Freq+0x78>)
8002e7a: f3c2 02c1 ubfx r2, r2, #3, #2
8002e7e: 40d3 lsrs r3, r2
8002e80: e002 b.n 8002e88 <HAL_RCC_GetPCLK2Freq+0x2c>
8002e82: f7ff fa4b bl 800231c <HAL_RCC_GetSysClockFreq.part.0>
8002e86: 4603 mov r3, r0
common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
8002e88: 4a11 ldr r2, [pc, #68] @ (8002ed0 <HAL_RCC_GetPCLK2Freq+0x74>)
8002e8a: 4913 ldr r1, [pc, #76] @ (8002ed8 <HAL_RCC_GetPCLK2Freq+0x7c>)
8002e8c: 6990 ldr r0, [r2, #24]
SystemCoreClock = common_system_clock;
8002e8e: 4d13 ldr r5, [pc, #76] @ (8002edc <HAL_RCC_GetPCLK2Freq+0x80>)
common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
8002e90: f3c0 2003 ubfx r0, r0, #8, #4
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
8002e94: 4c12 ldr r4, [pc, #72] @ (8002ee0 <HAL_RCC_GetPCLK2Freq+0x84>)
common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
8002e96: 5c08 ldrb r0, [r1, r0]
8002e98: f000 001f and.w r0, r0, #31
8002e9c: 40c3 lsrs r3, r0
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
8002e9e: 6990 ldr r0, [r2, #24]
8002ea0: f000 000f and.w r0, r0, #15
SystemCoreClock = common_system_clock;
8002ea4: 602b str r3, [r5, #0]
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
8002ea6: 5c08 ldrb r0, [r1, r0]
8002ea8: f000 001f and.w r0, r0, #31
8002eac: 40c3 lsrs r3, r0
8002eae: 6023 str r3, [r4, #0]
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
#if defined(RCC_D2CFGR_D2PPRE2)
return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU));
8002eb0: 69d2 ldr r2, [r2, #28]
8002eb2: f3c2 2202 ubfx r2, r2, #8, #3
8002eb6: 5c88 ldrb r0, [r1, r2]
8002eb8: f000 001f and.w r0, r0, #31
#else
return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU));
#endif
}
8002ebc: fa23 f000 lsr.w r0, r3, r0
8002ec0: bd38 pop {r3, r4, r5, pc}
switch (RCC->CFGR & RCC_CFGR_SWS)
8002ec2: 4b08 ldr r3, [pc, #32] @ (8002ee4 <HAL_RCC_GetPCLK2Freq+0x88>)
8002ec4: e7e0 b.n 8002e88 <HAL_RCC_GetPCLK2Freq+0x2c>
sysclockfreq = CSI_VALUE;
8002ec6: 4b08 ldr r3, [pc, #32] @ (8002ee8 <HAL_RCC_GetPCLK2Freq+0x8c>)
8002ec8: e7de b.n 8002e88 <HAL_RCC_GetPCLK2Freq+0x2c>
sysclockfreq = (uint32_t) HSI_VALUE;
8002eca: 4b02 ldr r3, [pc, #8] @ (8002ed4 <HAL_RCC_GetPCLK2Freq+0x78>)
8002ecc: e7dc b.n 8002e88 <HAL_RCC_GetPCLK2Freq+0x2c>
8002ece: bf00 nop
8002ed0: 58024400 .word 0x58024400
8002ed4: 03d09000 .word 0x03d09000
8002ed8: 08005618 .word 0x08005618
8002edc: 24000004 .word 0x24000004
8002ee0: 24000000 .word 0x24000000
8002ee4: 017d7840 .word 0x017d7840
8002ee8: 003d0900 .word 0x003d0900
08002eec <RCCEx_PLL2_Config.part.0>:
* @param Divider divider parameter to be updated
* @note PLL2 is temporary disabled to apply new parameters
*
* @retval HAL status
*/
static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2, uint32_t Divider)
8002eec: b5f8 push {r3, r4, r5, r6, r7, lr}
else
{
/* Disable PLL2. */
__HAL_RCC_PLL2_DISABLE();
8002eee: 4c36 ldr r4, [pc, #216] @ (8002fc8 <RCCEx_PLL2_Config.part.0+0xdc>)
static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2, uint32_t Divider)
8002ef0: 4606 mov r6, r0
8002ef2: 460f mov r7, r1
__HAL_RCC_PLL2_DISABLE();
8002ef4: 6823 ldr r3, [r4, #0]
8002ef6: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
8002efa: 6023 str r3, [r4, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002efc: f7fd ff6c bl 8000dd8 <HAL_GetTick>
8002f00: 4605 mov r5, r0
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
8002f02: e004 b.n 8002f0e <RCCEx_PLL2_Config.part.0+0x22>
{
if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
8002f04: f7fd ff68 bl 8000dd8 <HAL_GetTick>
8002f08: 1b40 subs r0, r0, r5
8002f0a: 2802 cmp r0, #2
8002f0c: d856 bhi.n 8002fbc <RCCEx_PLL2_Config.part.0+0xd0>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
8002f0e: 6823 ldr r3, [r4, #0]
8002f10: 011a lsls r2, r3, #4
8002f12: d4f7 bmi.n 8002f04 <RCCEx_PLL2_Config.part.0+0x18>
return HAL_TIMEOUT;
}
}
/* Configure PLL2 multiplication and division factors. */
__HAL_RCC_PLL2_CONFIG(pll2->PLL2M,
8002f14: 6aa3 ldr r3, [r4, #40] @ 0x28
8002f16: 6832 ldr r2, [r6, #0]
8002f18: f423 337c bic.w r3, r3, #258048 @ 0x3f000
8002f1c: ea43 3302 orr.w r3, r3, r2, lsl #12
8002f20: 62a3 str r3, [r4, #40] @ 0x28
8002f22: e9d6 3202 ldrd r3, r2, [r6, #8]
8002f26: 3b01 subs r3, #1
8002f28: 3a01 subs r2, #1
8002f2a: 025b lsls r3, r3, #9
8002f2c: 0412 lsls r2, r2, #16
8002f2e: b29b uxth r3, r3
8002f30: f402 02fe and.w r2, r2, #8323072 @ 0x7f0000
8002f34: 4313 orrs r3, r2
8002f36: 6872 ldr r2, [r6, #4]
8002f38: 3a01 subs r2, #1
8002f3a: f3c2 0208 ubfx r2, r2, #0, #9
8002f3e: 4313 orrs r3, r2
8002f40: 6932 ldr r2, [r6, #16]
8002f42: 3a01 subs r2, #1
8002f44: 0612 lsls r2, r2, #24
8002f46: f002 42fe and.w r2, r2, #2130706432 @ 0x7f000000
8002f4a: 4313 orrs r3, r2
8002f4c: 63a3 str r3, [r4, #56] @ 0x38
pll2->PLL2P,
pll2->PLL2Q,
pll2->PLL2R);
/* Select PLL2 input reference frequency range: VCI */
__HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ;
8002f4e: 6ae3 ldr r3, [r4, #44] @ 0x2c
8002f50: 6972 ldr r2, [r6, #20]
8002f52: f023 03c0 bic.w r3, r3, #192 @ 0xc0
8002f56: 4313 orrs r3, r2
8002f58: 62e3 str r3, [r4, #44] @ 0x2c
/* Select PLL2 output frequency range : VCO */
__HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ;
8002f5a: 6ae3 ldr r3, [r4, #44] @ 0x2c
8002f5c: 69b2 ldr r2, [r6, #24]
8002f5e: f023 0320 bic.w r3, r3, #32
8002f62: 4313 orrs r3, r2
8002f64: 62e3 str r3, [r4, #44] @ 0x2c
/* Disable PLL2FRACN . */
__HAL_RCC_PLL2FRACN_DISABLE();
8002f66: 6ae3 ldr r3, [r4, #44] @ 0x2c
8002f68: f023 0310 bic.w r3, r3, #16
8002f6c: 62e3 str r3, [r4, #44] @ 0x2c
/* Configures PLL2 clock Fractional Part Of The Multiplication Factor */
__HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);
8002f6e: 6be3 ldr r3, [r4, #60] @ 0x3c
8002f70: 69f2 ldr r2, [r6, #28]
8002f72: f36f 03cf bfc r3, #3, #13
8002f76: ea43 03c2 orr.w r3, r3, r2, lsl #3
8002f7a: 63e3 str r3, [r4, #60] @ 0x3c
/* Enable PLL2FRACN . */
__HAL_RCC_PLL2FRACN_ENABLE();
8002f7c: 6ae3 ldr r3, [r4, #44] @ 0x2c
8002f7e: f043 0310 orr.w r3, r3, #16
8002f82: 62e3 str r3, [r4, #44] @ 0x2c
/* Enable the PLL2 clock output */
if (Divider == DIVIDER_P_UPDATE)
{
__HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
8002f84: 6ae3 ldr r3, [r4, #44] @ 0x2c
if (Divider == DIVIDER_P_UPDATE)
8002f86: b1df cbz r7, 8002fc0 <RCCEx_PLL2_Config.part.0+0xd4>
}
else if (Divider == DIVIDER_Q_UPDATE)
8002f88: 2f01 cmp r7, #1
{
__HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
8002f8a: bf0c ite eq
8002f8c: f443 1380 orreq.w r3, r3, #1048576 @ 0x100000
}
else
{
__HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR);
8002f90: f443 1300 orrne.w r3, r3, #2097152 @ 0x200000
8002f94: 62e3 str r3, [r4, #44] @ 0x2c
}
/* Enable PLL2. */
__HAL_RCC_PLL2_ENABLE();
8002f96: 4c0c ldr r4, [pc, #48] @ (8002fc8 <RCCEx_PLL2_Config.part.0+0xdc>)
8002f98: 6823 ldr r3, [r4, #0]
8002f9a: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
8002f9e: 6023 str r3, [r4, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002fa0: f7fd ff1a bl 8000dd8 <HAL_GetTick>
8002fa4: 4605 mov r5, r0
/* Wait till PLL2 is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
8002fa6: e004 b.n 8002fb2 <RCCEx_PLL2_Config.part.0+0xc6>
{
if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
8002fa8: f7fd ff16 bl 8000dd8 <HAL_GetTick>
8002fac: 1b40 subs r0, r0, r5
8002fae: 2802 cmp r0, #2
8002fb0: d804 bhi.n 8002fbc <RCCEx_PLL2_Config.part.0+0xd0>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
8002fb2: 6823 ldr r3, [r4, #0]
8002fb4: 011b lsls r3, r3, #4
8002fb6: d5f7 bpl.n 8002fa8 <RCCEx_PLL2_Config.part.0+0xbc>
}
}
return status;
8002fb8: 2000 movs r0, #0
}
8002fba: bdf8 pop {r3, r4, r5, r6, r7, pc}
return HAL_TIMEOUT;
8002fbc: 2003 movs r0, #3
}
8002fbe: bdf8 pop {r3, r4, r5, r6, r7, pc}
__HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
8002fc0: f443 2300 orr.w r3, r3, #524288 @ 0x80000
8002fc4: 62e3 str r3, [r4, #44] @ 0x2c
8002fc6: e7e6 b.n 8002f96 <RCCEx_PLL2_Config.part.0+0xaa>
8002fc8: 58024400 .word 0x58024400
08002fcc <RCCEx_PLL3_Config.part.0>:
* @param Divider divider parameter to be updated
* @note PLL3 is temporary disabled to apply new parameters
*
* @retval HAL status
*/
static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3, uint32_t Divider)
8002fcc: b5f8 push {r3, r4, r5, r6, r7, lr}
else
{
/* Disable PLL3. */
__HAL_RCC_PLL3_DISABLE();
8002fce: 4c36 ldr r4, [pc, #216] @ (80030a8 <RCCEx_PLL3_Config.part.0+0xdc>)
static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3, uint32_t Divider)
8002fd0: 4606 mov r6, r0
8002fd2: 460f mov r7, r1
__HAL_RCC_PLL3_DISABLE();
8002fd4: 6823 ldr r3, [r4, #0]
8002fd6: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8002fda: 6023 str r3, [r4, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002fdc: f7fd fefc bl 8000dd8 <HAL_GetTick>
8002fe0: 4605 mov r5, r0
/* Wait till PLL3 is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
8002fe2: e004 b.n 8002fee <RCCEx_PLL3_Config.part.0+0x22>
{
if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
8002fe4: f7fd fef8 bl 8000dd8 <HAL_GetTick>
8002fe8: 1b40 subs r0, r0, r5
8002fea: 2802 cmp r0, #2
8002fec: d856 bhi.n 800309c <RCCEx_PLL3_Config.part.0+0xd0>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
8002fee: 6823 ldr r3, [r4, #0]
8002ff0: 009a lsls r2, r3, #2
8002ff2: d4f7 bmi.n 8002fe4 <RCCEx_PLL3_Config.part.0+0x18>
return HAL_TIMEOUT;
}
}
/* Configure the PLL3 multiplication and division factors. */
__HAL_RCC_PLL3_CONFIG(pll3->PLL3M,
8002ff4: 6aa3 ldr r3, [r4, #40] @ 0x28
8002ff6: 6832 ldr r2, [r6, #0]
8002ff8: f023 737c bic.w r3, r3, #66060288 @ 0x3f00000
8002ffc: ea43 5302 orr.w r3, r3, r2, lsl #20
8003000: 62a3 str r3, [r4, #40] @ 0x28
8003002: e9d6 3202 ldrd r3, r2, [r6, #8]
8003006: 3b01 subs r3, #1
8003008: 3a01 subs r2, #1
800300a: 025b lsls r3, r3, #9
800300c: 0412 lsls r2, r2, #16
800300e: b29b uxth r3, r3
8003010: f402 02fe and.w r2, r2, #8323072 @ 0x7f0000
8003014: 4313 orrs r3, r2
8003016: 6872 ldr r2, [r6, #4]
8003018: 3a01 subs r2, #1
800301a: f3c2 0208 ubfx r2, r2, #0, #9
800301e: 4313 orrs r3, r2
8003020: 6932 ldr r2, [r6, #16]
8003022: 3a01 subs r2, #1
8003024: 0612 lsls r2, r2, #24
8003026: f002 42fe and.w r2, r2, #2130706432 @ 0x7f000000
800302a: 4313 orrs r3, r2
800302c: 6423 str r3, [r4, #64] @ 0x40
pll3->PLL3P,
pll3->PLL3Q,
pll3->PLL3R);
/* Select PLL3 input reference frequency range: VCI */
__HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ;
800302e: 6ae3 ldr r3, [r4, #44] @ 0x2c
8003030: 6972 ldr r2, [r6, #20]
8003032: f423 6340 bic.w r3, r3, #3072 @ 0xc00
8003036: 4313 orrs r3, r2
8003038: 62e3 str r3, [r4, #44] @ 0x2c
/* Select PLL3 output frequency range : VCO */
__HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ;
800303a: 6ae3 ldr r3, [r4, #44] @ 0x2c
800303c: 69b2 ldr r2, [r6, #24]
800303e: f423 7300 bic.w r3, r3, #512 @ 0x200
8003042: 4313 orrs r3, r2
8003044: 62e3 str r3, [r4, #44] @ 0x2c
/* Disable PLL3FRACN . */
__HAL_RCC_PLL3FRACN_DISABLE();
8003046: 6ae3 ldr r3, [r4, #44] @ 0x2c
8003048: f423 7380 bic.w r3, r3, #256 @ 0x100
800304c: 62e3 str r3, [r4, #44] @ 0x2c
/* Configures PLL3 clock Fractional Part Of The Multiplication Factor */
__HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);
800304e: 6c63 ldr r3, [r4, #68] @ 0x44
8003050: 69f2 ldr r2, [r6, #28]
8003052: f36f 03cf bfc r3, #3, #13
8003056: ea43 03c2 orr.w r3, r3, r2, lsl #3
800305a: 6463 str r3, [r4, #68] @ 0x44
/* Enable PLL3FRACN . */
__HAL_RCC_PLL3FRACN_ENABLE();
800305c: 6ae3 ldr r3, [r4, #44] @ 0x2c
800305e: f443 7380 orr.w r3, r3, #256 @ 0x100
8003062: 62e3 str r3, [r4, #44] @ 0x2c
/* Enable the PLL3 clock output */
if (Divider == DIVIDER_P_UPDATE)
{
__HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
8003064: 6ae3 ldr r3, [r4, #44] @ 0x2c
if (Divider == DIVIDER_P_UPDATE)
8003066: b1df cbz r7, 80030a0 <RCCEx_PLL3_Config.part.0+0xd4>
}
else if (Divider == DIVIDER_Q_UPDATE)
8003068: 2f01 cmp r7, #1
{
__HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
800306a: bf0c ite eq
800306c: f443 0300 orreq.w r3, r3, #8388608 @ 0x800000
}
else
{
__HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
8003070: f043 7380 orrne.w r3, r3, #16777216 @ 0x1000000
8003074: 62e3 str r3, [r4, #44] @ 0x2c
}
/* Enable PLL3. */
__HAL_RCC_PLL3_ENABLE();
8003076: 4c0c ldr r4, [pc, #48] @ (80030a8 <RCCEx_PLL3_Config.part.0+0xdc>)
8003078: 6823 ldr r3, [r4, #0]
800307a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
800307e: 6023 str r3, [r4, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003080: f7fd feaa bl 8000dd8 <HAL_GetTick>
8003084: 4605 mov r5, r0
/* Wait till PLL3 is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
8003086: e004 b.n 8003092 <RCCEx_PLL3_Config.part.0+0xc6>
{
if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
8003088: f7fd fea6 bl 8000dd8 <HAL_GetTick>
800308c: 1b40 subs r0, r0, r5
800308e: 2802 cmp r0, #2
8003090: d804 bhi.n 800309c <RCCEx_PLL3_Config.part.0+0xd0>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
8003092: 6823 ldr r3, [r4, #0]
8003094: 009b lsls r3, r3, #2
8003096: d5f7 bpl.n 8003088 <RCCEx_PLL3_Config.part.0+0xbc>
}
}
return status;
8003098: 2000 movs r0, #0
}
800309a: bdf8 pop {r3, r4, r5, r6, r7, pc}
return HAL_TIMEOUT;
800309c: 2003 movs r0, #3
}
800309e: bdf8 pop {r3, r4, r5, r6, r7, pc}
__HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
80030a0: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
80030a4: 62e3 str r3, [r4, #44] @ 0x2c
80030a6: e7e6 b.n 8003076 <RCCEx_PLL3_Config.part.0+0xaa>
80030a8: 58024400 .word 0x58024400
080030ac <HAL_RCCEx_PeriphCLKConfig>:
{
80030ac: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
80030b0: e9d0 3200 ldrd r3, r2, [r0]
{
80030b4: 4604 mov r4, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
80030b6: 011d lsls r5, r3, #4
80030b8: f003 6600 and.w r6, r3, #134217728 @ 0x8000000
80030bc: d524 bpl.n 8003108 <HAL_RCCEx_PeriphCLKConfig+0x5c>
switch (PeriphClkInit->SpdifrxClockSelection)
80030be: 6e81 ldr r1, [r0, #104] @ 0x68
80030c0: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000
80030c4: f000 85df beq.w 8003c86 <HAL_RCCEx_PeriphCLKConfig+0xbda>
80030c8: f200 86a8 bhi.w 8003e1c <HAL_RCCEx_PeriphCLKConfig+0xd70>
80030cc: 2900 cmp r1, #0
80030ce: f000 85f6 beq.w 8003cbe <HAL_RCCEx_PeriphCLKConfig+0xc12>
80030d2: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000
80030d6: f040 86a5 bne.w 8003e24 <HAL_RCCEx_PeriphCLKConfig+0xd78>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
80030da: 49a9 ldr r1, [pc, #676] @ (8003380 <HAL_RCCEx_PeriphCLKConfig+0x2d4>)
80030dc: 6a89 ldr r1, [r1, #40] @ 0x28
80030de: f001 0103 and.w r1, r1, #3
80030e2: 2903 cmp r1, #3
80030e4: f000 869e beq.w 8003e24 <HAL_RCCEx_PeriphCLKConfig+0xd78>
80030e8: 2102 movs r1, #2
80030ea: 3008 adds r0, #8
80030ec: f7ff fefe bl 8002eec <RCCEx_PLL2_Config.part.0>
80030f0: 4606 mov r6, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
80030f2: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
80030f6: b93e cbnz r6, 8003108 <HAL_RCCEx_PeriphCLKConfig+0x5c>
__HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
80030f8: 6ea1 ldr r1, [r4, #104] @ 0x68
80030fa: 4da1 ldr r5, [pc, #644] @ (8003380 <HAL_RCCEx_PeriphCLKConfig+0x2d4>)
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
80030fc: 2600 movs r6, #0
__HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
80030fe: 6d28 ldr r0, [r5, #80] @ 0x50
8003100: f420 1040 bic.w r0, r0, #3145728 @ 0x300000
8003104: 4301 orrs r1, r0
8003106: 6529 str r1, [r5, #80] @ 0x50
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
8003108: 05d8 lsls r0, r3, #23
800310a: d50a bpl.n 8003122 <HAL_RCCEx_PeriphCLKConfig+0x76>
switch (PeriphClkInit->Sai1ClockSelection)
800310c: 6da1 ldr r1, [r4, #88] @ 0x58
800310e: 2904 cmp r1, #4
8003110: d806 bhi.n 8003120 <HAL_RCCEx_PeriphCLKConfig+0x74>
8003112: e8df f011 tbh [pc, r1, lsl #1]
8003116: 03ff .short 0x03ff
8003118: 0582056d .word 0x0582056d
800311c: 04040404 .word 0x04040404
status = ret;
8003120: 2601 movs r6, #1
ret = HAL_ERROR;
8003122: 4635 mov r5, r6
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23)
8003124: 0599 lsls r1, r3, #22
8003126: d524 bpl.n 8003172 <HAL_RCCEx_PeriphCLKConfig+0xc6>
switch (PeriphClkInit->Sai23ClockSelection)
8003128: 6de1 ldr r1, [r4, #92] @ 0x5c
800312a: 2980 cmp r1, #128 @ 0x80
800312c: f000 854b beq.w 8003bc6 <HAL_RCCEx_PeriphCLKConfig+0xb1a>
8003130: f200 8687 bhi.w 8003e42 <HAL_RCCEx_PeriphCLKConfig+0xd96>
8003134: 2900 cmp r1, #0
8003136: f000 85bb beq.w 8003cb0 <HAL_RCCEx_PeriphCLKConfig+0xc04>
800313a: 2940 cmp r1, #64 @ 0x40
800313c: f040 8688 bne.w 8003e50 <HAL_RCCEx_PeriphCLKConfig+0xda4>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003140: 498f ldr r1, [pc, #572] @ (8003380 <HAL_RCCEx_PeriphCLKConfig+0x2d4>)
8003142: 6a89 ldr r1, [r1, #40] @ 0x28
8003144: f001 0103 and.w r1, r1, #3
8003148: 2903 cmp r1, #3
800314a: f000 8681 beq.w 8003e50 <HAL_RCCEx_PeriphCLKConfig+0xda4>
800314e: 2100 movs r1, #0
8003150: f104 0008 add.w r0, r4, #8
8003154: f7ff feca bl 8002eec <RCCEx_PLL2_Config.part.0>
8003158: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)
800315a: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
800315e: 2d00 cmp r5, #0
8003160: f040 8543 bne.w 8003bea <HAL_RCCEx_PeriphCLKConfig+0xb3e>
__HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection);
8003164: 4f86 ldr r7, [pc, #536] @ (8003380 <HAL_RCCEx_PeriphCLKConfig+0x2d4>)
8003166: 6de0 ldr r0, [r4, #92] @ 0x5c
8003168: 6d39 ldr r1, [r7, #80] @ 0x50
800316a: f421 71e0 bic.w r1, r1, #448 @ 0x1c0
800316e: 4301 orrs r1, r0
8003170: 6539 str r1, [r7, #80] @ 0x50
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)
8003172: 055f lsls r7, r3, #21
8003174: d528 bpl.n 80031c8 <HAL_RCCEx_PeriphCLKConfig+0x11c>
switch (PeriphClkInit->Sai4AClockSelection)
8003176: f8d4 10a8 ldr.w r1, [r4, #168] @ 0xa8
800317a: f5b1 0f80 cmp.w r1, #4194304 @ 0x400000
800317e: f000 855c beq.w 8003c3a <HAL_RCCEx_PeriphCLKConfig+0xb8e>
8003182: f200 8652 bhi.w 8003e2a <HAL_RCCEx_PeriphCLKConfig+0xd7e>
8003186: 2900 cmp r1, #0
8003188: f000 858b beq.w 8003ca2 <HAL_RCCEx_PeriphCLKConfig+0xbf6>
800318c: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000
8003190: f040 8653 bne.w 8003e3a <HAL_RCCEx_PeriphCLKConfig+0xd8e>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003194: 497a ldr r1, [pc, #488] @ (8003380 <HAL_RCCEx_PeriphCLKConfig+0x2d4>)
8003196: 6a89 ldr r1, [r1, #40] @ 0x28
8003198: f001 0103 and.w r1, r1, #3
800319c: 2903 cmp r1, #3
800319e: f000 864c beq.w 8003e3a <HAL_RCCEx_PeriphCLKConfig+0xd8e>
80031a2: 2100 movs r1, #0
80031a4: f104 0008 add.w r0, r4, #8
80031a8: f7ff fea0 bl 8002eec <RCCEx_PLL2_Config.part.0>
80031ac: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)
80031ae: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
80031b2: 2d00 cmp r5, #0
80031b4: f040 8553 bne.w 8003c5e <HAL_RCCEx_PeriphCLKConfig+0xbb2>
__HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection);
80031b8: 4f71 ldr r7, [pc, #452] @ (8003380 <HAL_RCCEx_PeriphCLKConfig+0x2d4>)
80031ba: f8d4 00a8 ldr.w r0, [r4, #168] @ 0xa8
80031be: 6db9 ldr r1, [r7, #88] @ 0x58
80031c0: f421 0160 bic.w r1, r1, #14680064 @ 0xe00000
80031c4: 4301 orrs r1, r0
80031c6: 65b9 str r1, [r7, #88] @ 0x58
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)
80031c8: 0518 lsls r0, r3, #20
80031ca: d528 bpl.n 800321e <HAL_RCCEx_PeriphCLKConfig+0x172>
switch (PeriphClkInit->Sai4BClockSelection)
80031cc: f8d4 10ac ldr.w r1, [r4, #172] @ 0xac
80031d0: f1b1 7f00 cmp.w r1, #33554432 @ 0x2000000
80031d4: f000 8546 beq.w 8003c64 <HAL_RCCEx_PeriphCLKConfig+0xbb8>
80031d8: f200 8614 bhi.w 8003e04 <HAL_RCCEx_PeriphCLKConfig+0xd58>
80031dc: 2900 cmp r1, #0
80031de: f000 84d6 beq.w 8003b8e <HAL_RCCEx_PeriphCLKConfig+0xae2>
80031e2: f1b1 7f80 cmp.w r1, #16777216 @ 0x1000000
80031e6: f040 8615 bne.w 8003e14 <HAL_RCCEx_PeriphCLKConfig+0xd68>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
80031ea: 4965 ldr r1, [pc, #404] @ (8003380 <HAL_RCCEx_PeriphCLKConfig+0x2d4>)
80031ec: 6a89 ldr r1, [r1, #40] @ 0x28
80031ee: f001 0103 and.w r1, r1, #3
80031f2: 2903 cmp r1, #3
80031f4: f000 860e beq.w 8003e14 <HAL_RCCEx_PeriphCLKConfig+0xd68>
80031f8: 2100 movs r1, #0
80031fa: f104 0008 add.w r0, r4, #8
80031fe: f7ff fe75 bl 8002eec <RCCEx_PLL2_Config.part.0>
8003202: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
8003204: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
8003208: 2d00 cmp r5, #0
800320a: f040 84c8 bne.w 8003b9e <HAL_RCCEx_PeriphCLKConfig+0xaf2>
__HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection);
800320e: 4f5c ldr r7, [pc, #368] @ (8003380 <HAL_RCCEx_PeriphCLKConfig+0x2d4>)
8003210: f8d4 00ac ldr.w r0, [r4, #172] @ 0xac
8003214: 6db9 ldr r1, [r7, #88] @ 0x58
8003216: f021 61e0 bic.w r1, r1, #117440512 @ 0x7000000
800321a: 4301 orrs r1, r0
800321c: 65b9 str r1, [r7, #88] @ 0x58
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
800321e: 0199 lsls r1, r3, #6
8003220: d518 bpl.n 8003254 <HAL_RCCEx_PeriphCLKConfig+0x1a8>
switch (PeriphClkInit->QspiClockSelection)
8003222: 6ce1 ldr r1, [r4, #76] @ 0x4c
8003224: 2920 cmp r1, #32
8003226: f000 8434 beq.w 8003a92 <HAL_RCCEx_PeriphCLKConfig+0x9e6>
800322a: f200 8615 bhi.w 8003e58 <HAL_RCCEx_PeriphCLKConfig+0xdac>
800322e: b139 cbz r1, 8003240 <HAL_RCCEx_PeriphCLKConfig+0x194>
8003230: 2910 cmp r1, #16
8003232: f040 8614 bne.w 8003e5e <HAL_RCCEx_PeriphCLKConfig+0xdb2>
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
8003236: 4852 ldr r0, [pc, #328] @ (8003380 <HAL_RCCEx_PeriphCLKConfig+0x2d4>)
8003238: 6ac1 ldr r1, [r0, #44] @ 0x2c
800323a: f441 3100 orr.w r1, r1, #131072 @ 0x20000
800323e: 62c1 str r1, [r0, #44] @ 0x2c
if (ret == HAL_OK)
8003240: 2d00 cmp r5, #0
8003242: f040 83bf bne.w 80039c4 <HAL_RCCEx_PeriphCLKConfig+0x918>
__HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
8003246: 4f4e ldr r7, [pc, #312] @ (8003380 <HAL_RCCEx_PeriphCLKConfig+0x2d4>)
8003248: 6ce0 ldr r0, [r4, #76] @ 0x4c
800324a: 6cf9 ldr r1, [r7, #76] @ 0x4c
800324c: f021 0130 bic.w r1, r1, #48 @ 0x30
8003250: 4301 orrs r1, r0
8003252: 64f9 str r1, [r7, #76] @ 0x4c
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123)
8003254: 04df lsls r7, r3, #19
8003256: d526 bpl.n 80032a6 <HAL_RCCEx_PeriphCLKConfig+0x1fa>
switch (PeriphClkInit->Spi123ClockSelection)
8003258: 6e21 ldr r1, [r4, #96] @ 0x60
800325a: f5b1 5f00 cmp.w r1, #8192 @ 0x2000
800325e: f000 84a1 beq.w 8003ba4 <HAL_RCCEx_PeriphCLKConfig+0xaf8>
8003262: f200 85c3 bhi.w 8003dec <HAL_RCCEx_PeriphCLKConfig+0xd40>
8003266: 2900 cmp r1, #0
8003268: f000 8486 beq.w 8003b78 <HAL_RCCEx_PeriphCLKConfig+0xacc>
800326c: f5b1 5f80 cmp.w r1, #4096 @ 0x1000
8003270: f040 85c4 bne.w 8003dfc <HAL_RCCEx_PeriphCLKConfig+0xd50>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003274: 4942 ldr r1, [pc, #264] @ (8003380 <HAL_RCCEx_PeriphCLKConfig+0x2d4>)
8003276: 6a89 ldr r1, [r1, #40] @ 0x28
8003278: f001 0103 and.w r1, r1, #3
800327c: 2903 cmp r1, #3
800327e: f000 85bd beq.w 8003dfc <HAL_RCCEx_PeriphCLKConfig+0xd50>
8003282: 2100 movs r1, #0
8003284: f104 0008 add.w r0, r4, #8
8003288: f7ff fe30 bl 8002eec <RCCEx_PLL2_Config.part.0>
800328c: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
800328e: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
8003292: 2d00 cmp r5, #0
8003294: f040 8478 bne.w 8003b88 <HAL_RCCEx_PeriphCLKConfig+0xadc>
__HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection);
8003298: 4f39 ldr r7, [pc, #228] @ (8003380 <HAL_RCCEx_PeriphCLKConfig+0x2d4>)
800329a: 6e20 ldr r0, [r4, #96] @ 0x60
800329c: 6d39 ldr r1, [r7, #80] @ 0x50
800329e: f421 41e0 bic.w r1, r1, #28672 @ 0x7000
80032a2: 4301 orrs r1, r0
80032a4: 6539 str r1, [r7, #80] @ 0x50
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
80032a6: 0498 lsls r0, r3, #18
80032a8: d524 bpl.n 80032f4 <HAL_RCCEx_PeriphCLKConfig+0x248>
switch (PeriphClkInit->Spi45ClockSelection)
80032aa: 6e61 ldr r1, [r4, #100] @ 0x64
80032ac: f5b1 3f00 cmp.w r1, #131072 @ 0x20000
80032b0: f000 8415 beq.w 8003ade <HAL_RCCEx_PeriphCLKConfig+0xa32>
80032b4: f200 8556 bhi.w 8003d64 <HAL_RCCEx_PeriphCLKConfig+0xcb8>
80032b8: b191 cbz r1, 80032e0 <HAL_RCCEx_PeriphCLKConfig+0x234>
80032ba: f5b1 3f80 cmp.w r1, #65536 @ 0x10000
80032be: f040 855b bne.w 8003d78 <HAL_RCCEx_PeriphCLKConfig+0xccc>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
80032c2: 492f ldr r1, [pc, #188] @ (8003380 <HAL_RCCEx_PeriphCLKConfig+0x2d4>)
80032c4: 6a89 ldr r1, [r1, #40] @ 0x28
80032c6: f001 0103 and.w r1, r1, #3
80032ca: 2903 cmp r1, #3
80032cc: f000 8554 beq.w 8003d78 <HAL_RCCEx_PeriphCLKConfig+0xccc>
80032d0: 2101 movs r1, #1
80032d2: f104 0008 add.w r0, r4, #8
80032d6: f7ff fe09 bl 8002eec <RCCEx_PLL2_Config.part.0>
80032da: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
80032dc: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
80032e0: 2d00 cmp r5, #0
80032e2: f040 838f bne.w 8003a04 <HAL_RCCEx_PeriphCLKConfig+0x958>
__HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);
80032e6: 4f26 ldr r7, [pc, #152] @ (8003380 <HAL_RCCEx_PeriphCLKConfig+0x2d4>)
80032e8: 6e60 ldr r0, [r4, #100] @ 0x64
80032ea: 6d39 ldr r1, [r7, #80] @ 0x50
80032ec: f421 21e0 bic.w r1, r1, #458752 @ 0x70000
80032f0: 4301 orrs r1, r0
80032f2: 6539 str r1, [r7, #80] @ 0x50
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
80032f4: 0459 lsls r1, r3, #17
80032f6: d526 bpl.n 8003346 <HAL_RCCEx_PeriphCLKConfig+0x29a>
switch (PeriphClkInit->Spi6ClockSelection)
80032f8: f8d4 10b0 ldr.w r1, [r4, #176] @ 0xb0
80032fc: f1b1 5f00 cmp.w r1, #536870912 @ 0x20000000
8003300: f000 8426 beq.w 8003b50 <HAL_RCCEx_PeriphCLKConfig+0xaa4>
8003304: f200 854a bhi.w 8003d9c <HAL_RCCEx_PeriphCLKConfig+0xcf0>
8003308: b191 cbz r1, 8003330 <HAL_RCCEx_PeriphCLKConfig+0x284>
800330a: f1b1 5f80 cmp.w r1, #268435456 @ 0x10000000
800330e: f040 854f bne.w 8003db0 <HAL_RCCEx_PeriphCLKConfig+0xd04>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003312: 491b ldr r1, [pc, #108] @ (8003380 <HAL_RCCEx_PeriphCLKConfig+0x2d4>)
8003314: 6a89 ldr r1, [r1, #40] @ 0x28
8003316: f001 0103 and.w r1, r1, #3
800331a: 2903 cmp r1, #3
800331c: f000 8548 beq.w 8003db0 <HAL_RCCEx_PeriphCLKConfig+0xd04>
8003320: 2101 movs r1, #1
8003322: f104 0008 add.w r0, r4, #8
8003326: f7ff fde1 bl 8002eec <RCCEx_PLL2_Config.part.0>
800332a: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
800332c: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
8003330: 2d00 cmp r5, #0
8003332: f040 835b bne.w 80039ec <HAL_RCCEx_PeriphCLKConfig+0x940>
__HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
8003336: 4f12 ldr r7, [pc, #72] @ (8003380 <HAL_RCCEx_PeriphCLKConfig+0x2d4>)
8003338: f8d4 00b0 ldr.w r0, [r4, #176] @ 0xb0
800333c: 6db9 ldr r1, [r7, #88] @ 0x58
800333e: f021 41e0 bic.w r1, r1, #1879048192 @ 0x70000000
8003342: 4301 orrs r1, r0
8003344: 65b9 str r1, [r7, #88] @ 0x58
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
8003346: 041f lsls r7, r3, #16
8003348: d50d bpl.n 8003366 <HAL_RCCEx_PeriphCLKConfig+0x2ba>
switch (PeriphClkInit->FdcanClockSelection)
800334a: 6f21 ldr r1, [r4, #112] @ 0x70
800334c: f1b1 5f80 cmp.w r1, #268435456 @ 0x10000000
8003350: f000 8260 beq.w 8003814 <HAL_RCCEx_PeriphCLKConfig+0x768>
8003354: f1b1 5f00 cmp.w r1, #536870912 @ 0x20000000
8003358: f000 8591 beq.w 8003e7e <HAL_RCCEx_PeriphCLKConfig+0xdd2>
800335c: 2900 cmp r1, #0
800335e: f000 825e beq.w 800381e <HAL_RCCEx_PeriphCLKConfig+0x772>
status = ret;
8003362: 2601 movs r6, #1
ret = HAL_ERROR;
8003364: 4635 mov r5, r6
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
8003366: 01d8 lsls r0, r3, #7
8003368: d515 bpl.n 8003396 <HAL_RCCEx_PeriphCLKConfig+0x2ea>
switch (PeriphClkInit->FmcClockSelection)
800336a: 6ca1 ldr r1, [r4, #72] @ 0x48
800336c: 2903 cmp r1, #3
800336e: f200 85b4 bhi.w 8003eda <HAL_RCCEx_PeriphCLKConfig+0xe2e>
8003372: e8df f011 tbh [pc, r1, lsl #1]
8003376: 000c .short 0x000c
8003378: 03a10007 .word 0x03a10007
800337c: 000c .short 0x000c
800337e: bf00 nop
8003380: 58024400 .word 0x58024400
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
8003384: 4836 ldr r0, [pc, #216] @ (8003460 <HAL_RCCEx_PeriphCLKConfig+0x3b4>)
8003386: 6ac1 ldr r1, [r0, #44] @ 0x2c
8003388: f441 3100 orr.w r1, r1, #131072 @ 0x20000
800338c: 62c1 str r1, [r0, #44] @ 0x2c
if (ret == HAL_OK)
800338e: 2d00 cmp r5, #0
8003390: f000 831a beq.w 80039c8 <HAL_RCCEx_PeriphCLKConfig+0x91c>
status = ret;
8003394: 462e mov r6, r5
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
8003396: 0259 lsls r1, r3, #9
8003398: f100 827a bmi.w 8003890 <HAL_RCCEx_PeriphCLKConfig+0x7e4>
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
800339c: 07df lsls r7, r3, #31
800339e: d52f bpl.n 8003400 <HAL_RCCEx_PeriphCLKConfig+0x354>
switch (PeriphClkInit->Usart16ClockSelection)
80033a0: 6fe1 ldr r1, [r4, #124] @ 0x7c
80033a2: 2928 cmp r1, #40 @ 0x28
80033a4: d82a bhi.n 80033fc <HAL_RCCEx_PeriphCLKConfig+0x350>
80033a6: e8df f011 tbh [pc, r1, lsl #1]
80033aa: 0257 .short 0x0257
80033ac: 00290029 .word 0x00290029
80033b0: 00290029 .word 0x00290029
80033b4: 00290029 .word 0x00290029
80033b8: 02480029 .word 0x02480029
80033bc: 00290029 .word 0x00290029
80033c0: 00290029 .word 0x00290029
80033c4: 00290029 .word 0x00290029
80033c8: 04b90029 .word 0x04b90029
80033cc: 00290029 .word 0x00290029
80033d0: 00290029 .word 0x00290029
80033d4: 00290029 .word 0x00290029
80033d8: 02570029 .word 0x02570029
80033dc: 00290029 .word 0x00290029
80033e0: 00290029 .word 0x00290029
80033e4: 00290029 .word 0x00290029
80033e8: 02570029 .word 0x02570029
80033ec: 00290029 .word 0x00290029
80033f0: 00290029 .word 0x00290029
80033f4: 00290029 .word 0x00290029
80033f8: 02570029 .word 0x02570029
status = ret;
80033fc: 2601 movs r6, #1
ret = HAL_ERROR;
80033fe: 4635 mov r5, r6
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
8003400: 0798 lsls r0, r3, #30
8003402: d51e bpl.n 8003442 <HAL_RCCEx_PeriphCLKConfig+0x396>
switch (PeriphClkInit->Usart234578ClockSelection)
8003404: 6fa1 ldr r1, [r4, #120] @ 0x78
8003406: 2905 cmp r1, #5
8003408: f200 8550 bhi.w 8003eac <HAL_RCCEx_PeriphCLKConfig+0xe00>
800340c: e8df f011 tbh [pc, r1, lsl #1]
8003410: 00060015 .word 0x00060015
8003414: 00150471 .word 0x00150471
8003418: 00150015 .word 0x00150015
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
800341c: 4910 ldr r1, [pc, #64] @ (8003460 <HAL_RCCEx_PeriphCLKConfig+0x3b4>)
800341e: 6a89 ldr r1, [r1, #40] @ 0x28
8003420: f001 0103 and.w r1, r1, #3
8003424: 2903 cmp r1, #3
8003426: f000 8541 beq.w 8003eac <HAL_RCCEx_PeriphCLKConfig+0xe00>
800342a: 2101 movs r1, #1
800342c: f104 0008 add.w r0, r4, #8
8003430: f7ff fd5c bl 8002eec <RCCEx_PLL2_Config.part.0>
8003434: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
8003436: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
800343a: 2d00 cmp r5, #0
800343c: f000 82cc beq.w 80039d8 <HAL_RCCEx_PeriphCLKConfig+0x92c>
status = ret;
8003440: 462e mov r6, r5
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
8003442: 0759 lsls r1, r3, #29
8003444: d521 bpl.n 800348a <HAL_RCCEx_PeriphCLKConfig+0x3de>
switch (PeriphClkInit->Lpuart1ClockSelection)
8003446: f8d4 1094 ldr.w r1, [r4, #148] @ 0x94
800344a: 2905 cmp r1, #5
800344c: f200 852a bhi.w 8003ea4 <HAL_RCCEx_PeriphCLKConfig+0xdf8>
8003450: e8df f011 tbh [pc, r1, lsl #1]
8003454: 00080017 .word 0x00080017
8003458: 0017043c .word 0x0017043c
800345c: 00170017 .word 0x00170017
8003460: 58024400 .word 0x58024400
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003464: 49ae ldr r1, [pc, #696] @ (8003720 <HAL_RCCEx_PeriphCLKConfig+0x674>)
8003466: 6a89 ldr r1, [r1, #40] @ 0x28
8003468: f001 0103 and.w r1, r1, #3
800346c: 2903 cmp r1, #3
800346e: f000 8519 beq.w 8003ea4 <HAL_RCCEx_PeriphCLKConfig+0xdf8>
8003472: 2101 movs r1, #1
8003474: f104 0008 add.w r0, r4, #8
8003478: f7ff fd38 bl 8002eec <RCCEx_PLL2_Config.part.0>
800347c: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
800347e: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
8003482: 2d00 cmp r5, #0
8003484: f000 82c2 beq.w 8003a0c <HAL_RCCEx_PeriphCLKConfig+0x960>
status = ret;
8003488: 462e mov r6, r5
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
800348a: 069f lsls r7, r3, #26
800348c: d526 bpl.n 80034dc <HAL_RCCEx_PeriphCLKConfig+0x430>
switch (PeriphClkInit->Lptim1ClockSelection)
800348e: f8d4 1090 ldr.w r1, [r4, #144] @ 0x90
8003492: f1b1 5f00 cmp.w r1, #536870912 @ 0x20000000
8003496: f000 82c6 beq.w 8003a26 <HAL_RCCEx_PeriphCLKConfig+0x97a>
800349a: f200 8455 bhi.w 8003d48 <HAL_RCCEx_PeriphCLKConfig+0xc9c>
800349e: b191 cbz r1, 80034c6 <HAL_RCCEx_PeriphCLKConfig+0x41a>
80034a0: f1b1 5f80 cmp.w r1, #268435456 @ 0x10000000
80034a4: f040 845a bne.w 8003d5c <HAL_RCCEx_PeriphCLKConfig+0xcb0>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
80034a8: 499d ldr r1, [pc, #628] @ (8003720 <HAL_RCCEx_PeriphCLKConfig+0x674>)
80034aa: 6a89 ldr r1, [r1, #40] @ 0x28
80034ac: f001 0103 and.w r1, r1, #3
80034b0: 2903 cmp r1, #3
80034b2: f000 8453 beq.w 8003d5c <HAL_RCCEx_PeriphCLKConfig+0xcb0>
80034b6: 2100 movs r1, #0
80034b8: f104 0008 add.w r0, r4, #8
80034bc: f7ff fd16 bl 8002eec <RCCEx_PLL2_Config.part.0>
80034c0: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
80034c2: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
80034c6: 2d00 cmp r5, #0
80034c8: f040 828e bne.w 80039e8 <HAL_RCCEx_PeriphCLKConfig+0x93c>
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
80034cc: 4f94 ldr r7, [pc, #592] @ (8003720 <HAL_RCCEx_PeriphCLKConfig+0x674>)
80034ce: f8d4 0090 ldr.w r0, [r4, #144] @ 0x90
80034d2: 6d79 ldr r1, [r7, #84] @ 0x54
80034d4: f021 41e0 bic.w r1, r1, #1879048192 @ 0x70000000
80034d8: 4301 orrs r1, r0
80034da: 6579 str r1, [r7, #84] @ 0x54
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
80034dc: 0658 lsls r0, r3, #25
80034de: d526 bpl.n 800352e <HAL_RCCEx_PeriphCLKConfig+0x482>
switch (PeriphClkInit->Lptim2ClockSelection)
80034e0: f8d4 109c ldr.w r1, [r4, #156] @ 0x9c
80034e4: f5b1 6f00 cmp.w r1, #2048 @ 0x800
80034e8: f000 82af beq.w 8003a4a <HAL_RCCEx_PeriphCLKConfig+0x99e>
80034ec: f200 8464 bhi.w 8003db8 <HAL_RCCEx_PeriphCLKConfig+0xd0c>
80034f0: b191 cbz r1, 8003518 <HAL_RCCEx_PeriphCLKConfig+0x46c>
80034f2: f5b1 6f80 cmp.w r1, #1024 @ 0x400
80034f6: f040 8469 bne.w 8003dcc <HAL_RCCEx_PeriphCLKConfig+0xd20>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
80034fa: 4989 ldr r1, [pc, #548] @ (8003720 <HAL_RCCEx_PeriphCLKConfig+0x674>)
80034fc: 6a89 ldr r1, [r1, #40] @ 0x28
80034fe: f001 0103 and.w r1, r1, #3
8003502: 2903 cmp r1, #3
8003504: f000 8462 beq.w 8003dcc <HAL_RCCEx_PeriphCLKConfig+0xd20>
8003508: 2100 movs r1, #0
800350a: f104 0008 add.w r0, r4, #8
800350e: f7ff fced bl 8002eec <RCCEx_PLL2_Config.part.0>
8003512: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)
8003514: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
8003518: 2d00 cmp r5, #0
800351a: f040 8269 bne.w 80039f0 <HAL_RCCEx_PeriphCLKConfig+0x944>
__HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
800351e: 4f80 ldr r7, [pc, #512] @ (8003720 <HAL_RCCEx_PeriphCLKConfig+0x674>)
8003520: f8d4 009c ldr.w r0, [r4, #156] @ 0x9c
8003524: 6db9 ldr r1, [r7, #88] @ 0x58
8003526: f421 51e0 bic.w r1, r1, #7168 @ 0x1c00
800352a: 4301 orrs r1, r0
800352c: 65b9 str r1, [r7, #88] @ 0x58
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)
800352e: 0619 lsls r1, r3, #24
8003530: d526 bpl.n 8003580 <HAL_RCCEx_PeriphCLKConfig+0x4d4>
switch (PeriphClkInit->Lptim345ClockSelection)
8003532: f8d4 10a0 ldr.w r1, [r4, #160] @ 0xa0
8003536: f5b1 4f80 cmp.w r1, #16384 @ 0x4000
800353a: f000 8298 beq.w 8003a6e <HAL_RCCEx_PeriphCLKConfig+0x9c2>
800353e: f200 841f bhi.w 8003d80 <HAL_RCCEx_PeriphCLKConfig+0xcd4>
8003542: b191 cbz r1, 800356a <HAL_RCCEx_PeriphCLKConfig+0x4be>
8003544: f5b1 5f00 cmp.w r1, #8192 @ 0x2000
8003548: f040 8424 bne.w 8003d94 <HAL_RCCEx_PeriphCLKConfig+0xce8>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
800354c: 4974 ldr r1, [pc, #464] @ (8003720 <HAL_RCCEx_PeriphCLKConfig+0x674>)
800354e: 6a89 ldr r1, [r1, #40] @ 0x28
8003550: f001 0103 and.w r1, r1, #3
8003554: 2903 cmp r1, #3
8003556: f000 841d beq.w 8003d94 <HAL_RCCEx_PeriphCLKConfig+0xce8>
800355a: 2100 movs r1, #0
800355c: f104 0008 add.w r0, r4, #8
8003560: f7ff fcc4 bl 8002eec <RCCEx_PLL2_Config.part.0>
8003564: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123)
8003566: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
800356a: 2d00 cmp r5, #0
800356c: f040 8244 bne.w 80039f8 <HAL_RCCEx_PeriphCLKConfig+0x94c>
__HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection);
8003570: 4f6b ldr r7, [pc, #428] @ (8003720 <HAL_RCCEx_PeriphCLKConfig+0x674>)
8003572: f8d4 00a0 ldr.w r0, [r4, #160] @ 0xa0
8003576: 6db9 ldr r1, [r7, #88] @ 0x58
8003578: f421 4160 bic.w r1, r1, #57344 @ 0xe000
800357c: 4301 orrs r1, r0
800357e: 65b9 str r1, [r7, #88] @ 0x58
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123)
8003580: 071f lsls r7, r3, #28
8003582: d50b bpl.n 800359c <HAL_RCCEx_PeriphCLKConfig+0x4f0>
if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3)
8003584: f8d4 0084 ldr.w r0, [r4, #132] @ 0x84
8003588: f5b0 5f80 cmp.w r0, #4096 @ 0x1000
800358c: f000 81d4 beq.w 8003938 <HAL_RCCEx_PeriphCLKConfig+0x88c>
__HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection);
8003590: 4f63 ldr r7, [pc, #396] @ (8003720 <HAL_RCCEx_PeriphCLKConfig+0x674>)
8003592: 6d79 ldr r1, [r7, #84] @ 0x54
8003594: f421 5140 bic.w r1, r1, #12288 @ 0x3000
8003598: 4301 orrs r1, r0
800359a: 6579 str r1, [r7, #84] @ 0x54
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
800359c: 06d8 lsls r0, r3, #27
800359e: d50b bpl.n 80035b8 <HAL_RCCEx_PeriphCLKConfig+0x50c>
if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3)
80035a0: f8d4 0098 ldr.w r0, [r4, #152] @ 0x98
80035a4: f5b0 7f80 cmp.w r0, #256 @ 0x100
80035a8: f000 81db beq.w 8003962 <HAL_RCCEx_PeriphCLKConfig+0x8b6>
__HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
80035ac: 4f5c ldr r7, [pc, #368] @ (8003720 <HAL_RCCEx_PeriphCLKConfig+0x674>)
80035ae: 6db9 ldr r1, [r7, #88] @ 0x58
80035b0: f421 7140 bic.w r1, r1, #768 @ 0x300
80035b4: 4301 orrs r1, r0
80035b6: 65b9 str r1, [r7, #88] @ 0x58
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
80035b8: 0319 lsls r1, r3, #12
80035ba: d524 bpl.n 8003606 <HAL_RCCEx_PeriphCLKConfig+0x55a>
switch (PeriphClkInit->AdcClockSelection)
80035bc: f8d4 10a4 ldr.w r1, [r4, #164] @ 0xa4
80035c0: f5b1 3f80 cmp.w r1, #65536 @ 0x10000
80035c4: f000 82b1 beq.w 8003b2a <HAL_RCCEx_PeriphCLKConfig+0xa7e>
80035c8: f5b1 3f00 cmp.w r1, #131072 @ 0x20000
80035cc: d010 beq.n 80035f0 <HAL_RCCEx_PeriphCLKConfig+0x544>
80035ce: 2900 cmp r1, #0
80035d0: f040 8130 bne.w 8003834 <HAL_RCCEx_PeriphCLKConfig+0x788>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
80035d4: 4852 ldr r0, [pc, #328] @ (8003720 <HAL_RCCEx_PeriphCLKConfig+0x674>)
80035d6: 6a80 ldr r0, [r0, #40] @ 0x28
80035d8: f000 0003 and.w r0, r0, #3
80035dc: 2803 cmp r0, #3
80035de: f000 8129 beq.w 8003834 <HAL_RCCEx_PeriphCLKConfig+0x788>
80035e2: f104 0008 add.w r0, r4, #8
80035e6: f7ff fc81 bl 8002eec <RCCEx_PLL2_Config.part.0>
80035ea: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
80035ec: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
80035f0: 2d00 cmp r5, #0
80035f2: f040 81ff bne.w 80039f4 <HAL_RCCEx_PeriphCLKConfig+0x948>
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
80035f6: 4f4a ldr r7, [pc, #296] @ (8003720 <HAL_RCCEx_PeriphCLKConfig+0x674>)
80035f8: f8d4 00a4 ldr.w r0, [r4, #164] @ 0xa4
80035fc: 6db9 ldr r1, [r7, #88] @ 0x58
80035fe: f421 3140 bic.w r1, r1, #196608 @ 0x30000
8003602: 4301 orrs r1, r0
8003604: 65b9 str r1, [r7, #88] @ 0x58
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
8003606: 035f lsls r7, r3, #13
8003608: d50f bpl.n 800362a <HAL_RCCEx_PeriphCLKConfig+0x57e>
switch (PeriphClkInit->UsbClockSelection)
800360a: f8d4 1088 ldr.w r1, [r4, #136] @ 0x88
800360e: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000
8003612: f000 8277 beq.w 8003b04 <HAL_RCCEx_PeriphCLKConfig+0xa58>
8003616: f5b1 1f40 cmp.w r1, #3145728 @ 0x300000
800361a: f000 812d beq.w 8003878 <HAL_RCCEx_PeriphCLKConfig+0x7cc>
800361e: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000
8003622: f000 8124 beq.w 800386e <HAL_RCCEx_PeriphCLKConfig+0x7c2>
status = ret;
8003626: 2601 movs r6, #1
ret = HAL_ERROR;
8003628: 4635 mov r5, r6
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC)
800362a: 03d8 lsls r0, r3, #15
800362c: d520 bpl.n 8003670 <HAL_RCCEx_PeriphCLKConfig+0x5c4>
switch (PeriphClkInit->SdmmcClockSelection)
800362e: 6d21 ldr r1, [r4, #80] @ 0x50
8003630: 2900 cmp r1, #0
8003632: f000 81aa beq.w 800398a <HAL_RCCEx_PeriphCLKConfig+0x8de>
8003636: f5b1 3f80 cmp.w r1, #65536 @ 0x10000
800363a: f040 80e8 bne.w 800380e <HAL_RCCEx_PeriphCLKConfig+0x762>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
800363e: 4938 ldr r1, [pc, #224] @ (8003720 <HAL_RCCEx_PeriphCLKConfig+0x674>)
8003640: 6a89 ldr r1, [r1, #40] @ 0x28
8003642: f001 0103 and.w r1, r1, #3
8003646: 2903 cmp r1, #3
8003648: f000 80e1 beq.w 800380e <HAL_RCCEx_PeriphCLKConfig+0x762>
800364c: 2102 movs r1, #2
800364e: f104 0008 add.w r0, r4, #8
8003652: f7ff fc4b bl 8002eec <RCCEx_PLL2_Config.part.0>
8003656: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
8003658: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
800365c: 2d00 cmp r5, #0
800365e: f040 819c bne.w 800399a <HAL_RCCEx_PeriphCLKConfig+0x8ee>
__HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection);
8003662: 4f2f ldr r7, [pc, #188] @ (8003720 <HAL_RCCEx_PeriphCLKConfig+0x674>)
8003664: 6d20 ldr r0, [r4, #80] @ 0x50
8003666: 6cf9 ldr r1, [r7, #76] @ 0x4c
8003668: f421 3180 bic.w r1, r1, #65536 @ 0x10000
800366c: 4301 orrs r1, r0
800366e: 64f9 str r1, [r7, #76] @ 0x4c
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
8003670: 0099 lsls r1, r3, #2
8003672: d50e bpl.n 8003692 <HAL_RCCEx_PeriphCLKConfig+0x5e6>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003674: 492a ldr r1, [pc, #168] @ (8003720 <HAL_RCCEx_PeriphCLKConfig+0x674>)
8003676: 6a89 ldr r1, [r1, #40] @ 0x28
8003678: f001 0103 and.w r1, r1, #3
800367c: 2903 cmp r1, #3
800367e: d007 beq.n 8003690 <HAL_RCCEx_PeriphCLKConfig+0x5e4>
8003680: 2102 movs r1, #2
8003682: f104 0028 add.w r0, r4, #40 @ 0x28
8003686: f7ff fca1 bl 8002fcc <RCCEx_PLL3_Config.part.0>
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
800368a: e9d4 3200 ldrd r3, r2, [r4]
if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
800368e: b100 cbz r0, 8003692 <HAL_RCCEx_PeriphCLKConfig+0x5e6>
status = HAL_ERROR;
8003690: 2601 movs r6, #1
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
8003692: 039f lsls r7, r3, #14
8003694: f100 80ab bmi.w 80037ee <HAL_RCCEx_PeriphCLKConfig+0x742>
status = HAL_ERROR;
8003698: 4635 mov r5, r6
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
800369a: 02d8 lsls r0, r3, #11
800369c: d506 bpl.n 80036ac <HAL_RCCEx_PeriphCLKConfig+0x600>
__HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
800369e: 4820 ldr r0, [pc, #128] @ (8003720 <HAL_RCCEx_PeriphCLKConfig+0x674>)
80036a0: 6f66 ldr r6, [r4, #116] @ 0x74
80036a2: 6d01 ldr r1, [r0, #80] @ 0x50
80036a4: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
80036a8: 4331 orrs r1, r6
80036aa: 6501 str r1, [r0, #80] @ 0x50
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
80036ac: 00d9 lsls r1, r3, #3
80036ae: d507 bpl.n 80036c0 <HAL_RCCEx_PeriphCLKConfig+0x614>
__HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
80036b0: 481b ldr r0, [pc, #108] @ (8003720 <HAL_RCCEx_PeriphCLKConfig+0x674>)
80036b2: f8d4 60b8 ldr.w r6, [r4, #184] @ 0xb8
80036b6: 6901 ldr r1, [r0, #16]
80036b8: f421 4180 bic.w r1, r1, #16384 @ 0x4000
80036bc: 4331 orrs r1, r6
80036be: 6101 str r1, [r0, #16]
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
80036c0: 029f lsls r7, r3, #10
80036c2: d506 bpl.n 80036d2 <HAL_RCCEx_PeriphCLKConfig+0x626>
__HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
80036c4: 4816 ldr r0, [pc, #88] @ (8003720 <HAL_RCCEx_PeriphCLKConfig+0x674>)
80036c6: 6ee6 ldr r6, [r4, #108] @ 0x6c
80036c8: 6d01 ldr r1, [r0, #80] @ 0x50
80036ca: f021 7180 bic.w r1, r1, #16777216 @ 0x1000000
80036ce: 4331 orrs r1, r6
80036d0: 6501 str r1, [r0, #80] @ 0x50
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
80036d2: 005e lsls r6, r3, #1
80036d4: d509 bpl.n 80036ea <HAL_RCCEx_PeriphCLKConfig+0x63e>
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
80036d6: 4912 ldr r1, [pc, #72] @ (8003720 <HAL_RCCEx_PeriphCLKConfig+0x674>)
80036d8: 6908 ldr r0, [r1, #16]
80036da: f420 4000 bic.w r0, r0, #32768 @ 0x8000
80036de: 6108 str r0, [r1, #16]
80036e0: 6908 ldr r0, [r1, #16]
80036e2: f8d4 60bc ldr.w r6, [r4, #188] @ 0xbc
80036e6: 4330 orrs r0, r6
80036e8: 6108 str r0, [r1, #16]
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
80036ea: 2b00 cmp r3, #0
80036ec: da06 bge.n 80036fc <HAL_RCCEx_PeriphCLKConfig+0x650>
__HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection);
80036ee: 480c ldr r0, [pc, #48] @ (8003720 <HAL_RCCEx_PeriphCLKConfig+0x674>)
80036f0: 6d66 ldr r6, [r4, #84] @ 0x54
80036f2: 6cc1 ldr r1, [r0, #76] @ 0x4c
80036f4: f021 5140 bic.w r1, r1, #805306368 @ 0x30000000
80036f8: 4331 orrs r1, r6
80036fa: 64c1 str r1, [r0, #76] @ 0x4c
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
80036fc: 0218 lsls r0, r3, #8
80036fe: d507 bpl.n 8003710 <HAL_RCCEx_PeriphCLKConfig+0x664>
__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
8003700: 4907 ldr r1, [pc, #28] @ (8003720 <HAL_RCCEx_PeriphCLKConfig+0x674>)
8003702: f8d4 008c ldr.w r0, [r4, #140] @ 0x8c
8003706: 6d4b ldr r3, [r1, #84] @ 0x54
8003708: f423 0340 bic.w r3, r3, #12582912 @ 0xc00000
800370c: 4303 orrs r3, r0
800370e: 654b str r3, [r1, #84] @ 0x54
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP)
8003710: 07d1 lsls r1, r2, #31
8003712: d511 bpl.n 8003738 <HAL_RCCEx_PeriphCLKConfig+0x68c>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003714: 4b02 ldr r3, [pc, #8] @ (8003720 <HAL_RCCEx_PeriphCLKConfig+0x674>)
8003716: 6a9b ldr r3, [r3, #40] @ 0x28
8003718: f003 0303 and.w r3, r3, #3
800371c: 2b03 cmp r3, #3
800371e: e001 b.n 8003724 <HAL_RCCEx_PeriphCLKConfig+0x678>
8003720: 58024400 .word 0x58024400
8003724: f000 835c beq.w 8003de0 <HAL_RCCEx_PeriphCLKConfig+0xd34>
8003728: 2100 movs r1, #0
800372a: f104 0008 add.w r0, r4, #8
800372e: f7ff fbdd bl 8002eec <RCCEx_PLL2_Config.part.0>
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ)
8003732: 6862 ldr r2, [r4, #4]
if (ret == HAL_OK)
8003734: b100 cbz r0, 8003738 <HAL_RCCEx_PeriphCLKConfig+0x68c>
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ)
8003736: 4605 mov r5, r0
8003738: 0793 lsls r3, r2, #30
800373a: d50e bpl.n 800375a <HAL_RCCEx_PeriphCLKConfig+0x6ae>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
800373c: 4baf ldr r3, [pc, #700] @ (80039fc <HAL_RCCEx_PeriphCLKConfig+0x950>)
800373e: 6a9b ldr r3, [r3, #40] @ 0x28
8003740: f003 0303 and.w r3, r3, #3
8003744: 2b03 cmp r3, #3
8003746: f000 834d beq.w 8003de4 <HAL_RCCEx_PeriphCLKConfig+0xd38>
800374a: 2101 movs r1, #1
800374c: f104 0008 add.w r0, r4, #8
8003750: f7ff fbcc bl 8002eec <RCCEx_PLL2_Config.part.0>
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR)
8003754: 6862 ldr r2, [r4, #4]
if (ret == HAL_OK)
8003756: b100 cbz r0, 800375a <HAL_RCCEx_PeriphCLKConfig+0x6ae>
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR)
8003758: 4605 mov r5, r0
800375a: 0757 lsls r7, r2, #29
800375c: d50e bpl.n 800377c <HAL_RCCEx_PeriphCLKConfig+0x6d0>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
800375e: 4ba7 ldr r3, [pc, #668] @ (80039fc <HAL_RCCEx_PeriphCLKConfig+0x950>)
8003760: 6a9b ldr r3, [r3, #40] @ 0x28
8003762: f003 0303 and.w r3, r3, #3
8003766: 2b03 cmp r3, #3
8003768: f000 833e beq.w 8003de8 <HAL_RCCEx_PeriphCLKConfig+0xd3c>
800376c: 2102 movs r1, #2
800376e: f104 0008 add.w r0, r4, #8
8003772: f7ff fbbb bl 8002eec <RCCEx_PLL2_Config.part.0>
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP)
8003776: 6862 ldr r2, [r4, #4]
if (ret == HAL_OK)
8003778: b100 cbz r0, 800377c <HAL_RCCEx_PeriphCLKConfig+0x6d0>
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP)
800377a: 4605 mov r5, r0
800377c: 0716 lsls r6, r2, #28
800377e: d50e bpl.n 800379e <HAL_RCCEx_PeriphCLKConfig+0x6f2>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003780: 4b9e ldr r3, [pc, #632] @ (80039fc <HAL_RCCEx_PeriphCLKConfig+0x950>)
8003782: 6a9b ldr r3, [r3, #40] @ 0x28
8003784: f003 0303 and.w r3, r3, #3
8003788: 2b03 cmp r3, #3
800378a: f000 8323 beq.w 8003dd4 <HAL_RCCEx_PeriphCLKConfig+0xd28>
800378e: 2100 movs r1, #0
8003790: f104 0028 add.w r0, r4, #40 @ 0x28
8003794: f7ff fc1a bl 8002fcc <RCCEx_PLL3_Config.part.0>
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ)
8003798: 6862 ldr r2, [r4, #4]
if (ret == HAL_OK)
800379a: b100 cbz r0, 800379e <HAL_RCCEx_PeriphCLKConfig+0x6f2>
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ)
800379c: 4605 mov r5, r0
800379e: 06d0 lsls r0, r2, #27
80037a0: d50f bpl.n 80037c2 <HAL_RCCEx_PeriphCLKConfig+0x716>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
80037a2: 4b96 ldr r3, [pc, #600] @ (80039fc <HAL_RCCEx_PeriphCLKConfig+0x950>)
80037a4: 6a9b ldr r3, [r3, #40] @ 0x28
80037a6: f003 0303 and.w r3, r3, #3
80037aa: 2b03 cmp r3, #3
80037ac: f000 8314 beq.w 8003dd8 <HAL_RCCEx_PeriphCLKConfig+0xd2c>
80037b0: 2101 movs r1, #1
80037b2: f104 0028 add.w r0, r4, #40 @ 0x28
80037b6: f7ff fc09 bl 8002fcc <RCCEx_PLL3_Config.part.0>
if (ret == HAL_OK)
80037ba: 2800 cmp r0, #0
80037bc: f040 8359 bne.w 8003e72 <HAL_RCCEx_PeriphCLKConfig+0xdc6>
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR)
80037c0: 6862 ldr r2, [r4, #4]
80037c2: 0693 lsls r3, r2, #26
80037c4: d50e bpl.n 80037e4 <HAL_RCCEx_PeriphCLKConfig+0x738>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
80037c6: 4b8d ldr r3, [pc, #564] @ (80039fc <HAL_RCCEx_PeriphCLKConfig+0x950>)
80037c8: 6a9b ldr r3, [r3, #40] @ 0x28
80037ca: f003 0303 and.w r3, r3, #3
80037ce: 2b03 cmp r3, #3
80037d0: f000 82b7 beq.w 8003d42 <HAL_RCCEx_PeriphCLKConfig+0xc96>
80037d4: 2102 movs r1, #2
80037d6: f104 0028 add.w r0, r4, #40 @ 0x28
80037da: f7ff fbf7 bl 8002fcc <RCCEx_PLL3_Config.part.0>
if (ret == HAL_OK)
80037de: 2800 cmp r0, #0
80037e0: f040 82af bne.w 8003d42 <HAL_RCCEx_PeriphCLKConfig+0xc96>
if (status == HAL_OK)
80037e4: 1e28 subs r0, r5, #0
80037e6: bf18 it ne
80037e8: 2001 movne r0, #1
}
80037ea: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
switch (PeriphClkInit->RngClockSelection)
80037ee: f8d4 1080 ldr.w r1, [r4, #128] @ 0x80
80037f2: f5b1 7f80 cmp.w r1, #256 @ 0x100
80037f6: f000 80d2 beq.w 800399e <HAL_RCCEx_PeriphCLKConfig+0x8f2>
80037fa: f240 8110 bls.w 8003a1e <HAL_RCCEx_PeriphCLKConfig+0x972>
80037fe: f421 7080 bic.w r0, r1, #256 @ 0x100
8003802: f5b0 7f00 cmp.w r0, #512 @ 0x200
8003806: f000 80cf beq.w 80039a8 <HAL_RCCEx_PeriphCLKConfig+0x8fc>
800380a: 2501 movs r5, #1
800380c: e745 b.n 800369a <HAL_RCCEx_PeriphCLKConfig+0x5ee>
status = ret;
800380e: 2601 movs r6, #1
ret = HAL_ERROR;
8003810: 4635 mov r5, r6
8003812: e72d b.n 8003670 <HAL_RCCEx_PeriphCLKConfig+0x5c4>
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
8003814: 4879 ldr r0, [pc, #484] @ (80039fc <HAL_RCCEx_PeriphCLKConfig+0x950>)
8003816: 6ac1 ldr r1, [r0, #44] @ 0x2c
8003818: f441 3100 orr.w r1, r1, #131072 @ 0x20000
800381c: 62c1 str r1, [r0, #44] @ 0x2c
if (ret == HAL_OK)
800381e: 2d00 cmp r5, #0
8003820: f040 80ce bne.w 80039c0 <HAL_RCCEx_PeriphCLKConfig+0x914>
__HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
8003824: 4f75 ldr r7, [pc, #468] @ (80039fc <HAL_RCCEx_PeriphCLKConfig+0x950>)
8003826: 6f20 ldr r0, [r4, #112] @ 0x70
8003828: 6d39 ldr r1, [r7, #80] @ 0x50
800382a: f021 5140 bic.w r1, r1, #805306368 @ 0x30000000
800382e: 4301 orrs r1, r0
8003830: 6539 str r1, [r7, #80] @ 0x50
8003832: e598 b.n 8003366 <HAL_RCCEx_PeriphCLKConfig+0x2ba>
status = ret;
8003834: 2601 movs r6, #1
ret = HAL_ERROR;
8003836: 4635 mov r5, r6
8003838: e6e5 b.n 8003606 <HAL_RCCEx_PeriphCLKConfig+0x55a>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
800383a: 4970 ldr r1, [pc, #448] @ (80039fc <HAL_RCCEx_PeriphCLKConfig+0x950>)
800383c: 6a89 ldr r1, [r1, #40] @ 0x28
800383e: f001 0103 and.w r1, r1, #3
8003842: 2903 cmp r1, #3
8003844: f43f adda beq.w 80033fc <HAL_RCCEx_PeriphCLKConfig+0x350>
8003848: 2101 movs r1, #1
800384a: f104 0008 add.w r0, r4, #8
800384e: f7ff fb4d bl 8002eec <RCCEx_PLL2_Config.part.0>
8003852: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
8003854: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
8003858: 2d00 cmp r5, #0
800385a: f040 80d5 bne.w 8003a08 <HAL_RCCEx_PeriphCLKConfig+0x95c>
__HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection);
800385e: 4f67 ldr r7, [pc, #412] @ (80039fc <HAL_RCCEx_PeriphCLKConfig+0x950>)
8003860: 6fe0 ldr r0, [r4, #124] @ 0x7c
8003862: 6d79 ldr r1, [r7, #84] @ 0x54
8003864: f021 0138 bic.w r1, r1, #56 @ 0x38
8003868: 4301 orrs r1, r0
800386a: 6579 str r1, [r7, #84] @ 0x54
800386c: e5c8 b.n 8003400 <HAL_RCCEx_PeriphCLKConfig+0x354>
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
800386e: 4863 ldr r0, [pc, #396] @ (80039fc <HAL_RCCEx_PeriphCLKConfig+0x950>)
8003870: 6ac1 ldr r1, [r0, #44] @ 0x2c
8003872: f441 3100 orr.w r1, r1, #131072 @ 0x20000
8003876: 62c1 str r1, [r0, #44] @ 0x2c
if (ret == HAL_OK)
8003878: 2d00 cmp r5, #0
800387a: f040 809f bne.w 80039bc <HAL_RCCEx_PeriphCLKConfig+0x910>
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
800387e: 4f5f ldr r7, [pc, #380] @ (80039fc <HAL_RCCEx_PeriphCLKConfig+0x950>)
8003880: f8d4 0088 ldr.w r0, [r4, #136] @ 0x88
8003884: 6d79 ldr r1, [r7, #84] @ 0x54
8003886: f421 1140 bic.w r1, r1, #3145728 @ 0x300000
800388a: 4301 orrs r1, r0
800388c: 6579 str r1, [r7, #84] @ 0x54
800388e: e6cc b.n 800362a <HAL_RCCEx_PeriphCLKConfig+0x57e>
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8003890: 4f5b ldr r7, [pc, #364] @ (8003a00 <HAL_RCCEx_PeriphCLKConfig+0x954>)
8003892: 683b ldr r3, [r7, #0]
8003894: f443 7380 orr.w r3, r3, #256 @ 0x100
8003898: 603b str r3, [r7, #0]
tickstart = HAL_GetTick();
800389a: f7fd fa9d bl 8000dd8 <HAL_GetTick>
800389e: 4680 mov r8, r0
while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
80038a0: e006 b.n 80038b0 <HAL_RCCEx_PeriphCLKConfig+0x804>
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80038a2: f7fd fa99 bl 8000dd8 <HAL_GetTick>
80038a6: eba0 0008 sub.w r0, r0, r8
80038aa: 2864 cmp r0, #100 @ 0x64
80038ac: f200 82db bhi.w 8003e66 <HAL_RCCEx_PeriphCLKConfig+0xdba>
while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
80038b0: 683b ldr r3, [r7, #0]
80038b2: 05da lsls r2, r3, #23
80038b4: d5f5 bpl.n 80038a2 <HAL_RCCEx_PeriphCLKConfig+0x7f6>
if (ret == HAL_OK)
80038b6: 2d00 cmp r5, #0
80038b8: f040 82d6 bne.w 8003e68 <HAL_RCCEx_PeriphCLKConfig+0xdbc>
if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
80038bc: 4a4f ldr r2, [pc, #316] @ (80039fc <HAL_RCCEx_PeriphCLKConfig+0x950>)
80038be: f8d4 30b4 ldr.w r3, [r4, #180] @ 0xb4
80038c2: 6f11 ldr r1, [r2, #112] @ 0x70
80038c4: 4059 eors r1, r3
80038c6: f411 7f40 tst.w r1, #768 @ 0x300
80038ca: d00b beq.n 80038e4 <HAL_RCCEx_PeriphCLKConfig+0x838>
tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
80038cc: 6f11 ldr r1, [r2, #112] @ 0x70
__HAL_RCC_BACKUPRESET_FORCE();
80038ce: 6f10 ldr r0, [r2, #112] @ 0x70
tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
80038d0: f421 7140 bic.w r1, r1, #768 @ 0x300
__HAL_RCC_BACKUPRESET_FORCE();
80038d4: f440 3080 orr.w r0, r0, #65536 @ 0x10000
80038d8: 6710 str r0, [r2, #112] @ 0x70
__HAL_RCC_BACKUPRESET_RELEASE();
80038da: 6f10 ldr r0, [r2, #112] @ 0x70
80038dc: f420 3080 bic.w r0, r0, #65536 @ 0x10000
80038e0: 6710 str r0, [r2, #112] @ 0x70
RCC->BDCR = tmpreg;
80038e2: 6711 str r1, [r2, #112] @ 0x70
if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
80038e4: f5b3 7f80 cmp.w r3, #256 @ 0x100
80038e8: f000 82fb beq.w 8003ee2 <HAL_RCCEx_PeriphCLKConfig+0xe36>
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
80038ec: f403 7240 and.w r2, r3, #768 @ 0x300
80038f0: f5b2 7f40 cmp.w r2, #768 @ 0x300
80038f4: f000 8309 beq.w 8003f0a <HAL_RCCEx_PeriphCLKConfig+0xe5e>
80038f8: 4940 ldr r1, [pc, #256] @ (80039fc <HAL_RCCEx_PeriphCLKConfig+0x950>)
80038fa: 690a ldr r2, [r1, #16]
80038fc: f422 527c bic.w r2, r2, #16128 @ 0x3f00
8003900: 610a str r2, [r1, #16]
8003902: 483e ldr r0, [pc, #248] @ (80039fc <HAL_RCCEx_PeriphCLKConfig+0x950>)
8003904: f3c3 010b ubfx r1, r3, #0, #12
8003908: 6f07 ldr r7, [r0, #112] @ 0x70
800390a: 4339 orrs r1, r7
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
800390c: e9d4 3200 ldrd r3, r2, [r4]
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8003910: 6701 str r1, [r0, #112] @ 0x70
8003912: e543 b.n 800339c <HAL_RCCEx_PeriphCLKConfig+0x2f0>
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
8003914: 4839 ldr r0, [pc, #228] @ (80039fc <HAL_RCCEx_PeriphCLKConfig+0x950>)
8003916: 6ac1 ldr r1, [r0, #44] @ 0x2c
8003918: f441 3100 orr.w r1, r1, #131072 @ 0x20000
800391c: 62c1 str r1, [r0, #44] @ 0x2c
ret = HAL_ERROR;
800391e: 4635 mov r5, r6
if (ret == HAL_OK)
8003920: 2d00 cmp r5, #0
8003922: f040 8177 bne.w 8003c14 <HAL_RCCEx_PeriphCLKConfig+0xb68>
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
8003926: 4f35 ldr r7, [pc, #212] @ (80039fc <HAL_RCCEx_PeriphCLKConfig+0x950>)
8003928: 6da0 ldr r0, [r4, #88] @ 0x58
800392a: 6d39 ldr r1, [r7, #80] @ 0x50
800392c: f021 0107 bic.w r1, r1, #7
8003930: 4301 orrs r1, r0
8003932: 6539 str r1, [r7, #80] @ 0x50
8003934: f7ff bbf6 b.w 8003124 <HAL_RCCEx_PeriphCLKConfig+0x78>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003938: 4930 ldr r1, [pc, #192] @ (80039fc <HAL_RCCEx_PeriphCLKConfig+0x950>)
800393a: 6a89 ldr r1, [r1, #40] @ 0x28
800393c: f001 0103 and.w r1, r1, #3
8003940: 2903 cmp r1, #3
8003942: f000 82ba beq.w 8003eba <HAL_RCCEx_PeriphCLKConfig+0xe0e>
8003946: 2102 movs r1, #2
8003948: f104 0028 add.w r0, r4, #40 @ 0x28
800394c: f7ff fb3e bl 8002fcc <RCCEx_PLL3_Config.part.0>
if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
8003950: 2800 cmp r0, #0
8003952: f000 82b5 beq.w 8003ec0 <HAL_RCCEx_PeriphCLKConfig+0xe14>
__HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection);
8003956: f8d4 0084 ldr.w r0, [r4, #132] @ 0x84
status = HAL_ERROR;
800395a: 2601 movs r6, #1
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
800395c: e9d4 3200 ldrd r3, r2, [r4]
8003960: e616 b.n 8003590 <HAL_RCCEx_PeriphCLKConfig+0x4e4>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003962: 4926 ldr r1, [pc, #152] @ (80039fc <HAL_RCCEx_PeriphCLKConfig+0x950>)
8003964: 6a89 ldr r1, [r1, #40] @ 0x28
8003966: f001 0103 and.w r1, r1, #3
800396a: 2903 cmp r1, #3
800396c: f000 82a2 beq.w 8003eb4 <HAL_RCCEx_PeriphCLKConfig+0xe08>
8003970: 2102 movs r1, #2
8003972: f104 0028 add.w r0, r4, #40 @ 0x28
8003976: f7ff fb29 bl 8002fcc <RCCEx_PLL3_Config.part.0>
if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
800397a: 2800 cmp r0, #0
800397c: f040 82a6 bne.w 8003ecc <HAL_RCCEx_PeriphCLKConfig+0xe20>
__HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
8003980: f8d4 0098 ldr.w r0, [r4, #152] @ 0x98
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
8003984: e9d4 3200 ldrd r3, r2, [r4]
8003988: e610 b.n 80035ac <HAL_RCCEx_PeriphCLKConfig+0x500>
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
800398a: 481c ldr r0, [pc, #112] @ (80039fc <HAL_RCCEx_PeriphCLKConfig+0x950>)
800398c: 6ac1 ldr r1, [r0, #44] @ 0x2c
800398e: f441 3100 orr.w r1, r1, #131072 @ 0x20000
8003992: 62c1 str r1, [r0, #44] @ 0x2c
if (ret == HAL_OK)
8003994: 2d00 cmp r5, #0
8003996: f43f ae64 beq.w 8003662 <HAL_RCCEx_PeriphCLKConfig+0x5b6>
status = ret;
800399a: 462e mov r6, r5
800399c: e668 b.n 8003670 <HAL_RCCEx_PeriphCLKConfig+0x5c4>
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
800399e: 4f17 ldr r7, [pc, #92] @ (80039fc <HAL_RCCEx_PeriphCLKConfig+0x950>)
80039a0: 6af8 ldr r0, [r7, #44] @ 0x2c
80039a2: f440 3000 orr.w r0, r0, #131072 @ 0x20000
80039a6: 62f8 str r0, [r7, #44] @ 0x2c
if (ret == HAL_OK)
80039a8: 2d00 cmp r5, #0
80039aa: f47f ae76 bne.w 800369a <HAL_RCCEx_PeriphCLKConfig+0x5ee>
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
80039ae: 4d13 ldr r5, [pc, #76] @ (80039fc <HAL_RCCEx_PeriphCLKConfig+0x950>)
80039b0: 6d68 ldr r0, [r5, #84] @ 0x54
80039b2: f420 7040 bic.w r0, r0, #768 @ 0x300
80039b6: 4301 orrs r1, r0
80039b8: 6569 str r1, [r5, #84] @ 0x54
80039ba: e66d b.n 8003698 <HAL_RCCEx_PeriphCLKConfig+0x5ec>
status = ret;
80039bc: 462e mov r6, r5
80039be: e634 b.n 800362a <HAL_RCCEx_PeriphCLKConfig+0x57e>
status = ret;
80039c0: 462e mov r6, r5
80039c2: e4d0 b.n 8003366 <HAL_RCCEx_PeriphCLKConfig+0x2ba>
status = ret;
80039c4: 462e mov r6, r5
80039c6: e445 b.n 8003254 <HAL_RCCEx_PeriphCLKConfig+0x1a8>
__HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
80039c8: 4f0c ldr r7, [pc, #48] @ (80039fc <HAL_RCCEx_PeriphCLKConfig+0x950>)
80039ca: 6ca0 ldr r0, [r4, #72] @ 0x48
80039cc: 6cf9 ldr r1, [r7, #76] @ 0x4c
80039ce: f021 0103 bic.w r1, r1, #3
80039d2: 4301 orrs r1, r0
80039d4: 64f9 str r1, [r7, #76] @ 0x4c
80039d6: e4de b.n 8003396 <HAL_RCCEx_PeriphCLKConfig+0x2ea>
__HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection);
80039d8: 4f08 ldr r7, [pc, #32] @ (80039fc <HAL_RCCEx_PeriphCLKConfig+0x950>)
80039da: 6fa0 ldr r0, [r4, #120] @ 0x78
80039dc: 6d79 ldr r1, [r7, #84] @ 0x54
80039de: f021 0107 bic.w r1, r1, #7
80039e2: 4301 orrs r1, r0
80039e4: 6579 str r1, [r7, #84] @ 0x54
80039e6: e52c b.n 8003442 <HAL_RCCEx_PeriphCLKConfig+0x396>
status = ret;
80039e8: 462e mov r6, r5
80039ea: e577 b.n 80034dc <HAL_RCCEx_PeriphCLKConfig+0x430>
status = ret;
80039ec: 462e mov r6, r5
80039ee: e4aa b.n 8003346 <HAL_RCCEx_PeriphCLKConfig+0x29a>
status = ret;
80039f0: 462e mov r6, r5
80039f2: e59c b.n 800352e <HAL_RCCEx_PeriphCLKConfig+0x482>
status = ret;
80039f4: 462e mov r6, r5
80039f6: e606 b.n 8003606 <HAL_RCCEx_PeriphCLKConfig+0x55a>
status = ret;
80039f8: 462e mov r6, r5
80039fa: e5c1 b.n 8003580 <HAL_RCCEx_PeriphCLKConfig+0x4d4>
80039fc: 58024400 .word 0x58024400
8003a00: 58024800 .word 0x58024800
status = ret;
8003a04: 462e mov r6, r5
8003a06: e475 b.n 80032f4 <HAL_RCCEx_PeriphCLKConfig+0x248>
status = ret;
8003a08: 462e mov r6, r5
8003a0a: e4f9 b.n 8003400 <HAL_RCCEx_PeriphCLKConfig+0x354>
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
8003a0c: 4fc2 ldr r7, [pc, #776] @ (8003d18 <HAL_RCCEx_PeriphCLKConfig+0xc6c>)
8003a0e: f8d4 0094 ldr.w r0, [r4, #148] @ 0x94
8003a12: 6db9 ldr r1, [r7, #88] @ 0x58
8003a14: f021 0107 bic.w r1, r1, #7
8003a18: 4301 orrs r1, r0
8003a1a: 65b9 str r1, [r7, #88] @ 0x58
8003a1c: e535 b.n 800348a <HAL_RCCEx_PeriphCLKConfig+0x3de>
switch (PeriphClkInit->RngClockSelection)
8003a1e: 2900 cmp r1, #0
8003a20: f47f aef3 bne.w 800380a <HAL_RCCEx_PeriphCLKConfig+0x75e>
8003a24: e7c0 b.n 80039a8 <HAL_RCCEx_PeriphCLKConfig+0x8fc>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003a26: 49bc ldr r1, [pc, #752] @ (8003d18 <HAL_RCCEx_PeriphCLKConfig+0xc6c>)
8003a28: 6a89 ldr r1, [r1, #40] @ 0x28
8003a2a: f001 0103 and.w r1, r1, #3
8003a2e: 2903 cmp r1, #3
8003a30: f000 8194 beq.w 8003d5c <HAL_RCCEx_PeriphCLKConfig+0xcb0>
8003a34: 2102 movs r1, #2
8003a36: f104 0028 add.w r0, r4, #40 @ 0x28
8003a3a: f7ff fac7 bl 8002fcc <RCCEx_PLL3_Config.part.0>
8003a3e: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
8003a40: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
8003a44: 2d00 cmp r5, #0
8003a46: d1cf bne.n 80039e8 <HAL_RCCEx_PeriphCLKConfig+0x93c>
8003a48: e540 b.n 80034cc <HAL_RCCEx_PeriphCLKConfig+0x420>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003a4a: 49b3 ldr r1, [pc, #716] @ (8003d18 <HAL_RCCEx_PeriphCLKConfig+0xc6c>)
8003a4c: 6a89 ldr r1, [r1, #40] @ 0x28
8003a4e: f001 0103 and.w r1, r1, #3
8003a52: 2903 cmp r1, #3
8003a54: f000 81ba beq.w 8003dcc <HAL_RCCEx_PeriphCLKConfig+0xd20>
8003a58: 2102 movs r1, #2
8003a5a: f104 0028 add.w r0, r4, #40 @ 0x28
8003a5e: f7ff fab5 bl 8002fcc <RCCEx_PLL3_Config.part.0>
8003a62: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)
8003a64: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
8003a68: 2d00 cmp r5, #0
8003a6a: d1c1 bne.n 80039f0 <HAL_RCCEx_PeriphCLKConfig+0x944>
8003a6c: e557 b.n 800351e <HAL_RCCEx_PeriphCLKConfig+0x472>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003a6e: 49aa ldr r1, [pc, #680] @ (8003d18 <HAL_RCCEx_PeriphCLKConfig+0xc6c>)
8003a70: 6a89 ldr r1, [r1, #40] @ 0x28
8003a72: f001 0103 and.w r1, r1, #3
8003a76: 2903 cmp r1, #3
8003a78: f000 818c beq.w 8003d94 <HAL_RCCEx_PeriphCLKConfig+0xce8>
8003a7c: 2102 movs r1, #2
8003a7e: f104 0028 add.w r0, r4, #40 @ 0x28
8003a82: f7ff faa3 bl 8002fcc <RCCEx_PLL3_Config.part.0>
8003a86: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123)
8003a88: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
8003a8c: 2d00 cmp r5, #0
8003a8e: d1b3 bne.n 80039f8 <HAL_RCCEx_PeriphCLKConfig+0x94c>
8003a90: e56e b.n 8003570 <HAL_RCCEx_PeriphCLKConfig+0x4c4>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003a92: 49a1 ldr r1, [pc, #644] @ (8003d18 <HAL_RCCEx_PeriphCLKConfig+0xc6c>)
8003a94: 6a89 ldr r1, [r1, #40] @ 0x28
8003a96: f001 0103 and.w r1, r1, #3
8003a9a: 2903 cmp r1, #3
8003a9c: f000 81df beq.w 8003e5e <HAL_RCCEx_PeriphCLKConfig+0xdb2>
8003aa0: 2102 movs r1, #2
8003aa2: f104 0008 add.w r0, r4, #8
8003aa6: f7ff fa21 bl 8002eec <RCCEx_PLL2_Config.part.0>
8003aaa: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123)
8003aac: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
8003ab0: 2d00 cmp r5, #0
8003ab2: d187 bne.n 80039c4 <HAL_RCCEx_PeriphCLKConfig+0x918>
8003ab4: f7ff bbc7 b.w 8003246 <HAL_RCCEx_PeriphCLKConfig+0x19a>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003ab8: 4997 ldr r1, [pc, #604] @ (8003d18 <HAL_RCCEx_PeriphCLKConfig+0xc6c>)
8003aba: 6a89 ldr r1, [r1, #40] @ 0x28
8003abc: f001 0103 and.w r1, r1, #3
8003ac0: 2903 cmp r1, #3
8003ac2: f000 820a beq.w 8003eda <HAL_RCCEx_PeriphCLKConfig+0xe2e>
8003ac6: 2102 movs r1, #2
8003ac8: f104 0008 add.w r0, r4, #8
8003acc: f7ff fa0e bl 8002eec <RCCEx_PLL2_Config.part.0>
8003ad0: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
8003ad2: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
8003ad6: 2d00 cmp r5, #0
8003ad8: f47f ac5c bne.w 8003394 <HAL_RCCEx_PeriphCLKConfig+0x2e8>
8003adc: e774 b.n 80039c8 <HAL_RCCEx_PeriphCLKConfig+0x91c>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003ade: 498e ldr r1, [pc, #568] @ (8003d18 <HAL_RCCEx_PeriphCLKConfig+0xc6c>)
8003ae0: 6a89 ldr r1, [r1, #40] @ 0x28
8003ae2: f001 0103 and.w r1, r1, #3
8003ae6: 2903 cmp r1, #3
8003ae8: f000 8146 beq.w 8003d78 <HAL_RCCEx_PeriphCLKConfig+0xccc>
8003aec: 2101 movs r1, #1
8003aee: f104 0028 add.w r0, r4, #40 @ 0x28
8003af2: f7ff fa6b bl 8002fcc <RCCEx_PLL3_Config.part.0>
8003af6: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
8003af8: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
8003afc: 2d00 cmp r5, #0
8003afe: d181 bne.n 8003a04 <HAL_RCCEx_PeriphCLKConfig+0x958>
8003b00: f7ff bbf1 b.w 80032e6 <HAL_RCCEx_PeriphCLKConfig+0x23a>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003b04: 4984 ldr r1, [pc, #528] @ (8003d18 <HAL_RCCEx_PeriphCLKConfig+0xc6c>)
8003b06: 6a89 ldr r1, [r1, #40] @ 0x28
8003b08: f001 0103 and.w r1, r1, #3
8003b0c: 2903 cmp r1, #3
8003b0e: f43f ad8a beq.w 8003626 <HAL_RCCEx_PeriphCLKConfig+0x57a>
8003b12: 2101 movs r1, #1
8003b14: f104 0028 add.w r0, r4, #40 @ 0x28
8003b18: f7ff fa58 bl 8002fcc <RCCEx_PLL3_Config.part.0>
8003b1c: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC)
8003b1e: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
8003b22: 2d00 cmp r5, #0
8003b24: f47f af4a bne.w 80039bc <HAL_RCCEx_PeriphCLKConfig+0x910>
8003b28: e6a9 b.n 800387e <HAL_RCCEx_PeriphCLKConfig+0x7d2>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003b2a: 497b ldr r1, [pc, #492] @ (8003d18 <HAL_RCCEx_PeriphCLKConfig+0xc6c>)
8003b2c: 6a89 ldr r1, [r1, #40] @ 0x28
8003b2e: f001 0103 and.w r1, r1, #3
8003b32: 2903 cmp r1, #3
8003b34: f43f ae7e beq.w 8003834 <HAL_RCCEx_PeriphCLKConfig+0x788>
8003b38: 2102 movs r1, #2
8003b3a: f104 0028 add.w r0, r4, #40 @ 0x28
8003b3e: f7ff fa45 bl 8002fcc <RCCEx_PLL3_Config.part.0>
8003b42: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
8003b44: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
8003b48: 2d00 cmp r5, #0
8003b4a: f47f af53 bne.w 80039f4 <HAL_RCCEx_PeriphCLKConfig+0x948>
8003b4e: e552 b.n 80035f6 <HAL_RCCEx_PeriphCLKConfig+0x54a>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003b50: 4971 ldr r1, [pc, #452] @ (8003d18 <HAL_RCCEx_PeriphCLKConfig+0xc6c>)
8003b52: 6a89 ldr r1, [r1, #40] @ 0x28
8003b54: f001 0103 and.w r1, r1, #3
8003b58: 2903 cmp r1, #3
8003b5a: f000 8129 beq.w 8003db0 <HAL_RCCEx_PeriphCLKConfig+0xd04>
8003b5e: 2101 movs r1, #1
8003b60: f104 0028 add.w r0, r4, #40 @ 0x28
8003b64: f7ff fa32 bl 8002fcc <RCCEx_PLL3_Config.part.0>
8003b68: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
8003b6a: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
8003b6e: 2d00 cmp r5, #0
8003b70: f47f af3c bne.w 80039ec <HAL_RCCEx_PeriphCLKConfig+0x940>
8003b74: f7ff bbdf b.w 8003336 <HAL_RCCEx_PeriphCLKConfig+0x28a>
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
8003b78: 4867 ldr r0, [pc, #412] @ (8003d18 <HAL_RCCEx_PeriphCLKConfig+0xc6c>)
8003b7a: 6ac1 ldr r1, [r0, #44] @ 0x2c
8003b7c: f441 3100 orr.w r1, r1, #131072 @ 0x20000
8003b80: 62c1 str r1, [r0, #44] @ 0x2c
if (ret == HAL_OK)
8003b82: 2d00 cmp r5, #0
8003b84: f43f ab88 beq.w 8003298 <HAL_RCCEx_PeriphCLKConfig+0x1ec>
status = ret;
8003b88: 462e mov r6, r5
8003b8a: f7ff bb8c b.w 80032a6 <HAL_RCCEx_PeriphCLKConfig+0x1fa>
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
8003b8e: 4862 ldr r0, [pc, #392] @ (8003d18 <HAL_RCCEx_PeriphCLKConfig+0xc6c>)
8003b90: 6ac1 ldr r1, [r0, #44] @ 0x2c
8003b92: f441 3100 orr.w r1, r1, #131072 @ 0x20000
8003b96: 62c1 str r1, [r0, #44] @ 0x2c
if (ret == HAL_OK)
8003b98: 2d00 cmp r5, #0
8003b9a: f43f ab38 beq.w 800320e <HAL_RCCEx_PeriphCLKConfig+0x162>
status = ret;
8003b9e: 462e mov r6, r5
8003ba0: f7ff bb3d b.w 800321e <HAL_RCCEx_PeriphCLKConfig+0x172>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003ba4: 495c ldr r1, [pc, #368] @ (8003d18 <HAL_RCCEx_PeriphCLKConfig+0xc6c>)
8003ba6: 6a89 ldr r1, [r1, #40] @ 0x28
8003ba8: f001 0103 and.w r1, r1, #3
8003bac: 2903 cmp r1, #3
8003bae: f000 8125 beq.w 8003dfc <HAL_RCCEx_PeriphCLKConfig+0xd50>
8003bb2: 2100 movs r1, #0
8003bb4: f104 0028 add.w r0, r4, #40 @ 0x28
8003bb8: f7ff fa08 bl 8002fcc <RCCEx_PLL3_Config.part.0>
8003bbc: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
8003bbe: e9d4 3200 ldrd r3, r2, [r4]
break;
8003bc2: f7ff bb66 b.w 8003292 <HAL_RCCEx_PeriphCLKConfig+0x1e6>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003bc6: 4954 ldr r1, [pc, #336] @ (8003d18 <HAL_RCCEx_PeriphCLKConfig+0xc6c>)
8003bc8: 6a89 ldr r1, [r1, #40] @ 0x28
8003bca: f001 0103 and.w r1, r1, #3
8003bce: 2903 cmp r1, #3
8003bd0: f000 813e beq.w 8003e50 <HAL_RCCEx_PeriphCLKConfig+0xda4>
8003bd4: 2100 movs r1, #0
8003bd6: f104 0028 add.w r0, r4, #40 @ 0x28
8003bda: f7ff f9f7 bl 8002fcc <RCCEx_PLL3_Config.part.0>
8003bde: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)
8003be0: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
8003be4: 2d00 cmp r5, #0
8003be6: f43f aabd beq.w 8003164 <HAL_RCCEx_PeriphCLKConfig+0xb8>
status = ret;
8003bea: 462e mov r6, r5
8003bec: f7ff bac1 b.w 8003172 <HAL_RCCEx_PeriphCLKConfig+0xc6>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003bf0: 4949 ldr r1, [pc, #292] @ (8003d18 <HAL_RCCEx_PeriphCLKConfig+0xc6c>)
8003bf2: 6a89 ldr r1, [r1, #40] @ 0x28
8003bf4: f001 0103 and.w r1, r1, #3
8003bf8: 2903 cmp r1, #3
8003bfa: f43f aa91 beq.w 8003120 <HAL_RCCEx_PeriphCLKConfig+0x74>
8003bfe: 2100 movs r1, #0
8003c00: f104 0008 add.w r0, r4, #8
8003c04: f7ff f972 bl 8002eec <RCCEx_PLL2_Config.part.0>
8003c08: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23)
8003c0a: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
8003c0e: 2d00 cmp r5, #0
8003c10: f43f ae89 beq.w 8003926 <HAL_RCCEx_PeriphCLKConfig+0x87a>
status = ret;
8003c14: 462e mov r6, r5
8003c16: f7ff ba85 b.w 8003124 <HAL_RCCEx_PeriphCLKConfig+0x78>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003c1a: 493f ldr r1, [pc, #252] @ (8003d18 <HAL_RCCEx_PeriphCLKConfig+0xc6c>)
8003c1c: 6a89 ldr r1, [r1, #40] @ 0x28
8003c1e: f001 0103 and.w r1, r1, #3
8003c22: 2903 cmp r1, #3
8003c24: f43f aa7c beq.w 8003120 <HAL_RCCEx_PeriphCLKConfig+0x74>
8003c28: 2100 movs r1, #0
8003c2a: f104 0028 add.w r0, r4, #40 @ 0x28
8003c2e: f7ff f9cd bl 8002fcc <RCCEx_PLL3_Config.part.0>
8003c32: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23)
8003c34: e9d4 3200 ldrd r3, r2, [r4]
break;
8003c38: e672 b.n 8003920 <HAL_RCCEx_PeriphCLKConfig+0x874>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003c3a: 4937 ldr r1, [pc, #220] @ (8003d18 <HAL_RCCEx_PeriphCLKConfig+0xc6c>)
8003c3c: 6a89 ldr r1, [r1, #40] @ 0x28
8003c3e: f001 0103 and.w r1, r1, #3
8003c42: 2903 cmp r1, #3
8003c44: f000 80f9 beq.w 8003e3a <HAL_RCCEx_PeriphCLKConfig+0xd8e>
8003c48: 2100 movs r1, #0
8003c4a: f104 0028 add.w r0, r4, #40 @ 0x28
8003c4e: f7ff f9bd bl 8002fcc <RCCEx_PLL3_Config.part.0>
8003c52: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)
8003c54: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
8003c58: 2d00 cmp r5, #0
8003c5a: f43f aaad beq.w 80031b8 <HAL_RCCEx_PeriphCLKConfig+0x10c>
status = ret;
8003c5e: 462e mov r6, r5
8003c60: f7ff bab2 b.w 80031c8 <HAL_RCCEx_PeriphCLKConfig+0x11c>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003c64: 492c ldr r1, [pc, #176] @ (8003d18 <HAL_RCCEx_PeriphCLKConfig+0xc6c>)
8003c66: 6a89 ldr r1, [r1, #40] @ 0x28
8003c68: f001 0103 and.w r1, r1, #3
8003c6c: 2903 cmp r1, #3
8003c6e: f000 80d1 beq.w 8003e14 <HAL_RCCEx_PeriphCLKConfig+0xd68>
8003c72: 2100 movs r1, #0
8003c74: f104 0028 add.w r0, r4, #40 @ 0x28
8003c78: f7ff f9a8 bl 8002fcc <RCCEx_PLL3_Config.part.0>
8003c7c: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
8003c7e: e9d4 3200 ldrd r3, r2, [r4]
break;
8003c82: f7ff bac1 b.w 8003208 <HAL_RCCEx_PeriphCLKConfig+0x15c>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003c86: 4924 ldr r1, [pc, #144] @ (8003d18 <HAL_RCCEx_PeriphCLKConfig+0xc6c>)
8003c88: 6a89 ldr r1, [r1, #40] @ 0x28
8003c8a: f001 0103 and.w r1, r1, #3
8003c8e: 2903 cmp r1, #3
8003c90: f000 80c8 beq.w 8003e24 <HAL_RCCEx_PeriphCLKConfig+0xd78>
8003c94: 2102 movs r1, #2
8003c96: 3028 adds r0, #40 @ 0x28
8003c98: f7ff f998 bl 8002fcc <RCCEx_PLL3_Config.part.0>
8003c9c: 4606 mov r6, r0
break;
8003c9e: f7ff ba28 b.w 80030f2 <HAL_RCCEx_PeriphCLKConfig+0x46>
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
8003ca2: 481d ldr r0, [pc, #116] @ (8003d18 <HAL_RCCEx_PeriphCLKConfig+0xc6c>)
8003ca4: 6ac1 ldr r1, [r0, #44] @ 0x2c
8003ca6: f441 3100 orr.w r1, r1, #131072 @ 0x20000
8003caa: 62c1 str r1, [r0, #44] @ 0x2c
break;
8003cac: f7ff ba81 b.w 80031b2 <HAL_RCCEx_PeriphCLKConfig+0x106>
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
8003cb0: 4819 ldr r0, [pc, #100] @ (8003d18 <HAL_RCCEx_PeriphCLKConfig+0xc6c>)
8003cb2: 6ac1 ldr r1, [r0, #44] @ 0x2c
8003cb4: f441 3100 orr.w r1, r1, #131072 @ 0x20000
8003cb8: 62c1 str r1, [r0, #44] @ 0x2c
break;
8003cba: f7ff ba50 b.w 800315e <HAL_RCCEx_PeriphCLKConfig+0xb2>
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
8003cbe: 4d16 ldr r5, [pc, #88] @ (8003d18 <HAL_RCCEx_PeriphCLKConfig+0xc6c>)
8003cc0: 6ae8 ldr r0, [r5, #44] @ 0x2c
8003cc2: f440 3000 orr.w r0, r0, #131072 @ 0x20000
8003cc6: 62e8 str r0, [r5, #44] @ 0x2c
if (ret == HAL_OK)
8003cc8: f7ff ba17 b.w 80030fa <HAL_RCCEx_PeriphCLKConfig+0x4e>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003ccc: 4912 ldr r1, [pc, #72] @ (8003d18 <HAL_RCCEx_PeriphCLKConfig+0xc6c>)
8003cce: 6a89 ldr r1, [r1, #40] @ 0x28
8003cd0: f001 0103 and.w r1, r1, #3
8003cd4: 2903 cmp r1, #3
8003cd6: f000 80e5 beq.w 8003ea4 <HAL_RCCEx_PeriphCLKConfig+0xdf8>
8003cda: 2101 movs r1, #1
8003cdc: f104 0028 add.w r0, r4, #40 @ 0x28
8003ce0: f7ff f974 bl 8002fcc <RCCEx_PLL3_Config.part.0>
8003ce4: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
8003ce6: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
8003cea: 2d00 cmp r5, #0
8003cec: f47f abcc bne.w 8003488 <HAL_RCCEx_PeriphCLKConfig+0x3dc>
8003cf0: e68c b.n 8003a0c <HAL_RCCEx_PeriphCLKConfig+0x960>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003cf2: 4909 ldr r1, [pc, #36] @ (8003d18 <HAL_RCCEx_PeriphCLKConfig+0xc6c>)
8003cf4: 6a89 ldr r1, [r1, #40] @ 0x28
8003cf6: f001 0103 and.w r1, r1, #3
8003cfa: 2903 cmp r1, #3
8003cfc: f000 80d6 beq.w 8003eac <HAL_RCCEx_PeriphCLKConfig+0xe00>
8003d00: 2101 movs r1, #1
8003d02: f104 0028 add.w r0, r4, #40 @ 0x28
8003d06: f7ff f961 bl 8002fcc <RCCEx_PLL3_Config.part.0>
8003d0a: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
8003d0c: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
8003d10: 2d00 cmp r5, #0
8003d12: f47f ab95 bne.w 8003440 <HAL_RCCEx_PeriphCLKConfig+0x394>
8003d16: e65f b.n 80039d8 <HAL_RCCEx_PeriphCLKConfig+0x92c>
8003d18: 58024400 .word 0x58024400
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003d1c: 4983 ldr r1, [pc, #524] @ (8003f2c <HAL_RCCEx_PeriphCLKConfig+0xe80>)
8003d1e: 6a89 ldr r1, [r1, #40] @ 0x28
8003d20: f001 0103 and.w r1, r1, #3
8003d24: 2903 cmp r1, #3
8003d26: f43f ab69 beq.w 80033fc <HAL_RCCEx_PeriphCLKConfig+0x350>
8003d2a: 2101 movs r1, #1
8003d2c: f104 0028 add.w r0, r4, #40 @ 0x28
8003d30: f7ff f94c bl 8002fcc <RCCEx_PLL3_Config.part.0>
8003d34: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
8003d36: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
8003d3a: 2d00 cmp r5, #0
8003d3c: f47f ae64 bne.w 8003a08 <HAL_RCCEx_PeriphCLKConfig+0x95c>
8003d40: e58d b.n 800385e <HAL_RCCEx_PeriphCLKConfig+0x7b2>
return HAL_ERROR;
8003d42: 2001 movs r0, #1
}
8003d44: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
switch (PeriphClkInit->Lptim1ClockSelection)
8003d48: f021 5080 bic.w r0, r1, #268435456 @ 0x10000000
8003d4c: f1b0 4f80 cmp.w r0, #1073741824 @ 0x40000000
8003d50: f43f abb9 beq.w 80034c6 <HAL_RCCEx_PeriphCLKConfig+0x41a>
8003d54: f1b1 5f40 cmp.w r1, #805306368 @ 0x30000000
8003d58: f43f abb5 beq.w 80034c6 <HAL_RCCEx_PeriphCLKConfig+0x41a>
status = ret;
8003d5c: 2601 movs r6, #1
ret = HAL_ERROR;
8003d5e: 4635 mov r5, r6
8003d60: f7ff bbbc b.w 80034dc <HAL_RCCEx_PeriphCLKConfig+0x430>
switch (PeriphClkInit->Spi45ClockSelection)
8003d64: f421 3080 bic.w r0, r1, #65536 @ 0x10000
8003d68: f5b0 2f80 cmp.w r0, #262144 @ 0x40000
8003d6c: f43f aab8 beq.w 80032e0 <HAL_RCCEx_PeriphCLKConfig+0x234>
8003d70: f5b1 3f40 cmp.w r1, #196608 @ 0x30000
8003d74: f43f aab4 beq.w 80032e0 <HAL_RCCEx_PeriphCLKConfig+0x234>
status = ret;
8003d78: 2601 movs r6, #1
ret = HAL_ERROR;
8003d7a: 4635 mov r5, r6
8003d7c: f7ff baba b.w 80032f4 <HAL_RCCEx_PeriphCLKConfig+0x248>
switch (PeriphClkInit->Lptim345ClockSelection)
8003d80: f421 5000 bic.w r0, r1, #8192 @ 0x2000
8003d84: f5b0 4f00 cmp.w r0, #32768 @ 0x8000
8003d88: f43f abef beq.w 800356a <HAL_RCCEx_PeriphCLKConfig+0x4be>
8003d8c: f5b1 4fc0 cmp.w r1, #24576 @ 0x6000
8003d90: f43f abeb beq.w 800356a <HAL_RCCEx_PeriphCLKConfig+0x4be>
status = ret;
8003d94: 2601 movs r6, #1
ret = HAL_ERROR;
8003d96: 4635 mov r5, r6
8003d98: f7ff bbf2 b.w 8003580 <HAL_RCCEx_PeriphCLKConfig+0x4d4>
switch (PeriphClkInit->Spi6ClockSelection)
8003d9c: f021 5080 bic.w r0, r1, #268435456 @ 0x10000000
8003da0: f1b0 4f80 cmp.w r0, #1073741824 @ 0x40000000
8003da4: f43f aac4 beq.w 8003330 <HAL_RCCEx_PeriphCLKConfig+0x284>
8003da8: f1b1 5f40 cmp.w r1, #805306368 @ 0x30000000
8003dac: f43f aac0 beq.w 8003330 <HAL_RCCEx_PeriphCLKConfig+0x284>
status = ret;
8003db0: 2601 movs r6, #1
ret = HAL_ERROR;
8003db2: 4635 mov r5, r6
8003db4: f7ff bac7 b.w 8003346 <HAL_RCCEx_PeriphCLKConfig+0x29a>
switch (PeriphClkInit->Lptim2ClockSelection)
8003db8: f421 6080 bic.w r0, r1, #1024 @ 0x400
8003dbc: f5b0 5f80 cmp.w r0, #4096 @ 0x1000
8003dc0: f43f abaa beq.w 8003518 <HAL_RCCEx_PeriphCLKConfig+0x46c>
8003dc4: f5b1 6f40 cmp.w r1, #3072 @ 0xc00
8003dc8: f43f aba6 beq.w 8003518 <HAL_RCCEx_PeriphCLKConfig+0x46c>
status = ret;
8003dcc: 2601 movs r6, #1
ret = HAL_ERROR;
8003dce: 4635 mov r5, r6
8003dd0: f7ff bbad b.w 800352e <HAL_RCCEx_PeriphCLKConfig+0x482>
return HAL_ERROR;
8003dd4: 2501 movs r5, #1
8003dd6: e4e2 b.n 800379e <HAL_RCCEx_PeriphCLKConfig+0x6f2>
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR)
8003dd8: 0691 lsls r1, r2, #26
8003dda: d5b2 bpl.n 8003d42 <HAL_RCCEx_PeriphCLKConfig+0xc96>
return HAL_ERROR;
8003ddc: 2501 movs r5, #1
8003dde: e4f2 b.n 80037c6 <HAL_RCCEx_PeriphCLKConfig+0x71a>
return HAL_ERROR;
8003de0: 2501 movs r5, #1
8003de2: e4a9 b.n 8003738 <HAL_RCCEx_PeriphCLKConfig+0x68c>
8003de4: 2501 movs r5, #1
8003de6: e4b8 b.n 800375a <HAL_RCCEx_PeriphCLKConfig+0x6ae>
8003de8: 2501 movs r5, #1
8003dea: e4c7 b.n 800377c <HAL_RCCEx_PeriphCLKConfig+0x6d0>
switch (PeriphClkInit->Spi123ClockSelection)
8003dec: f5b1 5f40 cmp.w r1, #12288 @ 0x3000
8003df0: f43f aa4f beq.w 8003292 <HAL_RCCEx_PeriphCLKConfig+0x1e6>
8003df4: f5b1 4f80 cmp.w r1, #16384 @ 0x4000
8003df8: f43f aa4b beq.w 8003292 <HAL_RCCEx_PeriphCLKConfig+0x1e6>
status = ret;
8003dfc: 2601 movs r6, #1
ret = HAL_ERROR;
8003dfe: 4635 mov r5, r6
8003e00: f7ff ba51 b.w 80032a6 <HAL_RCCEx_PeriphCLKConfig+0x1fa>
switch (PeriphClkInit->Sai4BClockSelection)
8003e04: f1b1 7f40 cmp.w r1, #50331648 @ 0x3000000
8003e08: f43f a9fe beq.w 8003208 <HAL_RCCEx_PeriphCLKConfig+0x15c>
8003e0c: f1b1 6f80 cmp.w r1, #67108864 @ 0x4000000
8003e10: f43f a9fa beq.w 8003208 <HAL_RCCEx_PeriphCLKConfig+0x15c>
status = ret;
8003e14: 2601 movs r6, #1
ret = HAL_ERROR;
8003e16: 4635 mov r5, r6
8003e18: f7ff ba01 b.w 800321e <HAL_RCCEx_PeriphCLKConfig+0x172>
switch (PeriphClkInit->SpdifrxClockSelection)
8003e1c: f5b1 1f40 cmp.w r1, #3145728 @ 0x300000
8003e20: f43f a96b beq.w 80030fa <HAL_RCCEx_PeriphCLKConfig+0x4e>
ret = HAL_ERROR;
8003e24: 2601 movs r6, #1
8003e26: f7ff b96f b.w 8003108 <HAL_RCCEx_PeriphCLKConfig+0x5c>
switch (PeriphClkInit->Sai4AClockSelection)
8003e2a: f5b1 0fc0 cmp.w r1, #6291456 @ 0x600000
8003e2e: f43f a9c0 beq.w 80031b2 <HAL_RCCEx_PeriphCLKConfig+0x106>
8003e32: f5b1 0f00 cmp.w r1, #8388608 @ 0x800000
8003e36: f43f a9bc beq.w 80031b2 <HAL_RCCEx_PeriphCLKConfig+0x106>
status = ret;
8003e3a: 2601 movs r6, #1
ret = HAL_ERROR;
8003e3c: 4635 mov r5, r6
8003e3e: f7ff b9c3 b.w 80031c8 <HAL_RCCEx_PeriphCLKConfig+0x11c>
switch (PeriphClkInit->Sai23ClockSelection)
8003e42: 29c0 cmp r1, #192 @ 0xc0
8003e44: f43f a98b beq.w 800315e <HAL_RCCEx_PeriphCLKConfig+0xb2>
8003e48: f5b1 7f80 cmp.w r1, #256 @ 0x100
8003e4c: f43f a987 beq.w 800315e <HAL_RCCEx_PeriphCLKConfig+0xb2>
status = ret;
8003e50: 2601 movs r6, #1
ret = HAL_ERROR;
8003e52: 4635 mov r5, r6
8003e54: f7ff b98d b.w 8003172 <HAL_RCCEx_PeriphCLKConfig+0xc6>
switch (PeriphClkInit->QspiClockSelection)
8003e58: 2930 cmp r1, #48 @ 0x30
8003e5a: f43f a9f1 beq.w 8003240 <HAL_RCCEx_PeriphCLKConfig+0x194>
status = ret;
8003e5e: 2601 movs r6, #1
ret = HAL_ERROR;
8003e60: 4635 mov r5, r6
8003e62: f7ff b9f7 b.w 8003254 <HAL_RCCEx_PeriphCLKConfig+0x1a8>
ret = HAL_TIMEOUT;
8003e66: 2503 movs r5, #3
status = ret;
8003e68: 462e mov r6, r5
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
8003e6a: e9d4 3200 ldrd r3, r2, [r4]
8003e6e: f7ff ba95 b.w 800339c <HAL_RCCEx_PeriphCLKConfig+0x2f0>
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR)
8003e72: 6863 ldr r3, [r4, #4]
8003e74: 069a lsls r2, r3, #26
8003e76: f57f af64 bpl.w 8003d42 <HAL_RCCEx_PeriphCLKConfig+0xc96>
8003e7a: 4605 mov r5, r0
8003e7c: e4a3 b.n 80037c6 <HAL_RCCEx_PeriphCLKConfig+0x71a>
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8003e7e: 492b ldr r1, [pc, #172] @ (8003f2c <HAL_RCCEx_PeriphCLKConfig+0xe80>)
8003e80: 6a89 ldr r1, [r1, #40] @ 0x28
8003e82: f001 0103 and.w r1, r1, #3
8003e86: 2903 cmp r1, #3
8003e88: f43f aa6b beq.w 8003362 <HAL_RCCEx_PeriphCLKConfig+0x2b6>
8003e8c: 2101 movs r1, #1
8003e8e: f104 0008 add.w r0, r4, #8
8003e92: f7ff f82b bl 8002eec <RCCEx_PLL2_Config.part.0>
8003e96: 4605 mov r5, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
8003e98: e9d4 3200 ldrd r3, r2, [r4]
if (ret == HAL_OK)
8003e9c: 2d00 cmp r5, #0
8003e9e: f47f ad8f bne.w 80039c0 <HAL_RCCEx_PeriphCLKConfig+0x914>
8003ea2: e4bf b.n 8003824 <HAL_RCCEx_PeriphCLKConfig+0x778>
status = ret;
8003ea4: 2601 movs r6, #1
ret = HAL_ERROR;
8003ea6: 4635 mov r5, r6
8003ea8: f7ff baef b.w 800348a <HAL_RCCEx_PeriphCLKConfig+0x3de>
status = ret;
8003eac: 2601 movs r6, #1
ret = HAL_ERROR;
8003eae: 4635 mov r5, r6
8003eb0: f7ff bac7 b.w 8003442 <HAL_RCCEx_PeriphCLKConfig+0x396>
status = HAL_ERROR;
8003eb4: 2601 movs r6, #1
8003eb6: f7ff bb79 b.w 80035ac <HAL_RCCEx_PeriphCLKConfig+0x500>
status = HAL_ERROR;
8003eba: 2601 movs r6, #1
8003ebc: f7ff bb68 b.w 8003590 <HAL_RCCEx_PeriphCLKConfig+0x4e4>
__HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection);
8003ec0: f8d4 0084 ldr.w r0, [r4, #132] @ 0x84
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
8003ec4: e9d4 3200 ldrd r3, r2, [r4]
8003ec8: f7ff bb62 b.w 8003590 <HAL_RCCEx_PeriphCLKConfig+0x4e4>
__HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
8003ecc: f8d4 0098 ldr.w r0, [r4, #152] @ 0x98
status = HAL_ERROR;
8003ed0: 2601 movs r6, #1
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
8003ed2: e9d4 3200 ldrd r3, r2, [r4]
8003ed6: f7ff bb69 b.w 80035ac <HAL_RCCEx_PeriphCLKConfig+0x500>
status = ret;
8003eda: 2601 movs r6, #1
ret = HAL_ERROR;
8003edc: 4635 mov r5, r6
8003ede: f7ff ba5a b.w 8003396 <HAL_RCCEx_PeriphCLKConfig+0x2ea>
tickstart = HAL_GetTick();
8003ee2: f7fc ff79 bl 8000dd8 <HAL_GetTick>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
8003ee6: f8df 8044 ldr.w r8, [pc, #68] @ 8003f2c <HAL_RCCEx_PeriphCLKConfig+0xe80>
tickstart = HAL_GetTick();
8003eea: 4607 mov r7, r0
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8003eec: f241 3988 movw r9, #5000 @ 0x1388
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
8003ef0: e004 b.n 8003efc <HAL_RCCEx_PeriphCLKConfig+0xe50>
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8003ef2: f7fc ff71 bl 8000dd8 <HAL_GetTick>
8003ef6: 1bc0 subs r0, r0, r7
8003ef8: 4548 cmp r0, r9
8003efa: d810 bhi.n 8003f1e <HAL_RCCEx_PeriphCLKConfig+0xe72>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
8003efc: f8d8 3070 ldr.w r3, [r8, #112] @ 0x70
8003f00: 079b lsls r3, r3, #30
8003f02: d5f6 bpl.n 8003ef2 <HAL_RCCEx_PeriphCLKConfig+0xe46>
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8003f04: f8d4 30b4 ldr.w r3, [r4, #180] @ 0xb4
8003f08: e4f0 b.n 80038ec <HAL_RCCEx_PeriphCLKConfig+0x840>
8003f0a: 4808 ldr r0, [pc, #32] @ (8003f2c <HAL_RCCEx_PeriphCLKConfig+0xe80>)
8003f0c: 4a08 ldr r2, [pc, #32] @ (8003f30 <HAL_RCCEx_PeriphCLKConfig+0xe84>)
8003f0e: 6901 ldr r1, [r0, #16]
8003f10: ea02 1213 and.w r2, r2, r3, lsr #4
8003f14: f421 517c bic.w r1, r1, #16128 @ 0x3f00
8003f18: 430a orrs r2, r1
8003f1a: 6102 str r2, [r0, #16]
8003f1c: e4f1 b.n 8003902 <HAL_RCCEx_PeriphCLKConfig+0x856>
status = ret;
8003f1e: 2603 movs r6, #3
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
8003f20: e9d4 3200 ldrd r3, r2, [r4]
8003f24: 4635 mov r5, r6
8003f26: f7ff ba39 b.w 800339c <HAL_RCCEx_PeriphCLKConfig+0x2f0>
8003f2a: bf00 nop
8003f2c: 58024400 .word 0x58024400
8003f30: 00ffffcf .word 0x00ffffcf
08003f34 <HAL_RCCEx_GetD3PCLK1Freq>:
{
8003f34: b508 push {r3, lr}
return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU));
8003f36: f7fe ff09 bl 8002d4c <HAL_RCC_GetHCLKFreq>
8003f3a: 4b05 ldr r3, [pc, #20] @ (8003f50 <HAL_RCCEx_GetD3PCLK1Freq+0x1c>)
8003f3c: 4a05 ldr r2, [pc, #20] @ (8003f54 <HAL_RCCEx_GetD3PCLK1Freq+0x20>)
8003f3e: 6a1b ldr r3, [r3, #32]
8003f40: f3c3 1302 ubfx r3, r3, #4, #3
8003f44: 5cd3 ldrb r3, [r2, r3]
8003f46: f003 031f and.w r3, r3, #31
}
8003f4a: 40d8 lsrs r0, r3
8003f4c: bd08 pop {r3, pc}
8003f4e: bf00 nop
8003f50: 58024400 .word 0x58024400
8003f54: 08005618 .word 0x08005618
08003f58 <HAL_RCCEx_GetPLL2ClockFreq>:
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
8003f58: 4a47 ldr r2, [pc, #284] @ (8004078 <HAL_RCCEx_GetPLL2ClockFreq+0x120>)
{
8003f5a: b470 push {r4, r5, r6}
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
8003f5c: 6a94 ldr r4, [r2, #40] @ 0x28
pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12);
8003f5e: 6a95 ldr r5, [r2, #40] @ 0x28
pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos;
8003f60: 6ad6 ldr r6, [r2, #44] @ 0x2c
if (pll2m != 0U)
8003f62: f415 3f7c tst.w r5, #258048 @ 0x3f000
pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12);
8003f66: f3c5 3305 ubfx r3, r5, #12, #6
fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3));
8003f6a: 6bd1 ldr r1, [r2, #60] @ 0x3c
if (pll2m != 0U)
8003f6c: d05b beq.n 8004026 <HAL_RCCEx_GetPLL2ClockFreq+0xce>
fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3));
8003f6e: f3c1 01cc ubfx r1, r1, #3, #13
pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos;
8003f72: f3c6 1600 ubfx r6, r6, #4, #1
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
8003f76: f004 0403 and.w r4, r4, #3
pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
8003f7a: ee07 3a90 vmov s15, r3
fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3));
8003f7e: fb06 f101 mul.w r1, r6, r1
switch (pllsource)
8003f82: 2c01 cmp r4, #1
pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
8003f84: eeb8 7ae7 vcvt.f32.s32 s14, s15
8003f88: ee06 1a90 vmov s13, r1
8003f8c: eefa 6ae9 vcvt.f32.s32 s13, s13, #13
switch (pllsource)
8003f90: d003 beq.n 8003f9a <HAL_RCCEx_GetPLL2ClockFreq+0x42>
8003f92: 2c02 cmp r4, #2
8003f94: d06a beq.n 800406c <HAL_RCCEx_GetPLL2ClockFreq+0x114>
8003f96: 2c00 cmp r4, #0
8003f98: d04a beq.n 8004030 <HAL_RCCEx_GetPLL2ClockFreq+0xd8>
pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
8003f9a: eddf 7a38 vldr s15, [pc, #224] @ 800407c <HAL_RCCEx_GetPLL2ClockFreq+0x124>
8003f9e: ee87 6a87 vdiv.f32 s12, s15, s14
8003fa2: 6b93 ldr r3, [r2, #56] @ 0x38
8003fa4: f3c3 0308 ubfx r3, r3, #0, #9
8003fa8: ee07 3a90 vmov s15, r3
8003fac: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
8003fb0: eef8 7ae7 vcvt.f32.s32 s15, s15
8003fb4: ee77 7aa6 vadd.f32 s15, s15, s13
8003fb8: ee77 7aa5 vadd.f32 s15, s15, s11
8003fbc: ee67 7a86 vmul.f32 s15, s15, s12
PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ;
8003fc0: 4a2d ldr r2, [pc, #180] @ (8004078 <HAL_RCCEx_GetPLL2ClockFreq+0x120>)
8003fc2: eeb7 6a00 vmov.f32 s12, #112 @ 0x3f800000 1.0
8003fc6: 6b93 ldr r3, [r2, #56] @ 0x38
8003fc8: f3c3 2346 ubfx r3, r3, #9, #7
8003fcc: ee07 3a10 vmov s14, r3
8003fd0: eeb8 7ac7 vcvt.f32.s32 s14, s14
}
8003fd4: bc70 pop {r4, r5, r6}
PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ;
8003fd6: ee37 7a06 vadd.f32 s14, s14, s12
8003fda: eec7 6a87 vdiv.f32 s13, s15, s14
8003fde: eefc 6ae6 vcvt.u32.f32 s13, s13
8003fe2: edc0 6a00 vstr s13, [r0]
PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ;
8003fe6: 6b93 ldr r3, [r2, #56] @ 0x38
8003fe8: f3c3 4306 ubfx r3, r3, #16, #7
8003fec: ee07 3a10 vmov s14, r3
8003ff0: eeb8 7ac7 vcvt.f32.s32 s14, s14
8003ff4: ee37 7a06 vadd.f32 s14, s14, s12
8003ff8: eec7 6a87 vdiv.f32 s13, s15, s14
8003ffc: eefc 6ae6 vcvt.u32.f32 s13, s13
8004000: edc0 6a01 vstr s13, [r0, #4]
PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ;
8004004: 6b93 ldr r3, [r2, #56] @ 0x38
8004006: f3c3 6306 ubfx r3, r3, #24, #7
800400a: ee06 3a90 vmov s13, r3
800400e: eef8 6ae6 vcvt.f32.s32 s13, s13
8004012: ee76 6a86 vadd.f32 s13, s13, s12
8004016: ee87 7aa6 vdiv.f32 s14, s15, s13
800401a: eefc 7ac7 vcvt.u32.f32 s15, s14
800401e: ee17 3a90 vmov r3, s15
8004022: 6083 str r3, [r0, #8]
}
8004024: 4770 bx lr
8004026: bc70 pop {r4, r5, r6}
PLL2_Clocks->PLL2_P_Frequency = 0U;
8004028: e9c0 3300 strd r3, r3, [r0]
PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ;
800402c: 6083 str r3, [r0, #8]
}
800402e: 4770 bx lr
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
8004030: 6813 ldr r3, [r2, #0]
8004032: 069b lsls r3, r3, #26
8004034: d51d bpl.n 8004072 <HAL_RCCEx_GetPLL2ClockFreq+0x11a>
hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
8004036: 6814 ldr r4, [r2, #0]
pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
8004038: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
800403c: 6b93 ldr r3, [r2, #56] @ 0x38
hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
800403e: 4910 ldr r1, [pc, #64] @ (8004080 <HAL_RCCEx_GetPLL2ClockFreq+0x128>)
8004040: f3c4 02c1 ubfx r2, r4, #3, #2
pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
8004044: f3c3 0308 ubfx r3, r3, #0, #9
hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
8004048: 40d1 lsrs r1, r2
pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
800404a: ee07 3a90 vmov s15, r3
800404e: ee06 1a10 vmov s12, r1
8004052: eef8 7ae7 vcvt.f32.s32 s15, s15
8004056: eeb8 6ac6 vcvt.f32.s32 s12, s12
800405a: ee77 6aa6 vadd.f32 s13, s15, s13
800405e: eec6 7a07 vdiv.f32 s15, s12, s14
8004062: ee36 7aa5 vadd.f32 s14, s13, s11
8004066: ee67 7a87 vmul.f32 s15, s15, s14
800406a: e7a9 b.n 8003fc0 <HAL_RCCEx_GetPLL2ClockFreq+0x68>
pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
800406c: eddf 7a05 vldr s15, [pc, #20] @ 8004084 <HAL_RCCEx_GetPLL2ClockFreq+0x12c>
8004070: e795 b.n 8003f9e <HAL_RCCEx_GetPLL2ClockFreq+0x46>
pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
8004072: eddf 7a05 vldr s15, [pc, #20] @ 8004088 <HAL_RCCEx_GetPLL2ClockFreq+0x130>
8004076: e792 b.n 8003f9e <HAL_RCCEx_GetPLL2ClockFreq+0x46>
8004078: 58024400 .word 0x58024400
800407c: 4a742400 .word 0x4a742400
8004080: 03d09000 .word 0x03d09000
8004084: 4bbebc20 .word 0x4bbebc20
8004088: 4c742400 .word 0x4c742400
0800408c <HAL_RCCEx_GetPLL3ClockFreq>:
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
800408c: 4a47 ldr r2, [pc, #284] @ (80041ac <HAL_RCCEx_GetPLL3ClockFreq+0x120>)
{
800408e: b470 push {r4, r5, r6}
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
8004090: 6a94 ldr r4, [r2, #40] @ 0x28
pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ;
8004092: 6a95 ldr r5, [r2, #40] @ 0x28
pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos;
8004094: 6ad6 ldr r6, [r2, #44] @ 0x2c
if (pll3m != 0U)
8004096: f015 7f7c tst.w r5, #66060288 @ 0x3f00000
pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ;
800409a: f3c5 5305 ubfx r3, r5, #20, #6
fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3));
800409e: 6c51 ldr r1, [r2, #68] @ 0x44
if (pll3m != 0U)
80040a0: d05b beq.n 800415a <HAL_RCCEx_GetPLL3ClockFreq+0xce>
fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3));
80040a2: f3c1 01cc ubfx r1, r1, #3, #13
pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos;
80040a6: f3c6 2600 ubfx r6, r6, #8, #1
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
80040aa: f004 0403 and.w r4, r4, #3
pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
80040ae: ee07 3a90 vmov s15, r3
fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3));
80040b2: fb06 f101 mul.w r1, r6, r1
switch (pllsource)
80040b6: 2c01 cmp r4, #1
pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
80040b8: eeb8 7ae7 vcvt.f32.s32 s14, s15
80040bc: ee06 1a90 vmov s13, r1
80040c0: eefa 6ae9 vcvt.f32.s32 s13, s13, #13
switch (pllsource)
80040c4: d003 beq.n 80040ce <HAL_RCCEx_GetPLL3ClockFreq+0x42>
80040c6: 2c02 cmp r4, #2
80040c8: d06a beq.n 80041a0 <HAL_RCCEx_GetPLL3ClockFreq+0x114>
80040ca: 2c00 cmp r4, #0
80040cc: d04a beq.n 8004164 <HAL_RCCEx_GetPLL3ClockFreq+0xd8>
pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
80040ce: eddf 7a38 vldr s15, [pc, #224] @ 80041b0 <HAL_RCCEx_GetPLL3ClockFreq+0x124>
80040d2: ee87 6a87 vdiv.f32 s12, s15, s14
80040d6: 6c13 ldr r3, [r2, #64] @ 0x40
80040d8: f3c3 0308 ubfx r3, r3, #0, #9
80040dc: ee07 3a90 vmov s15, r3
80040e0: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
80040e4: eef8 7ae7 vcvt.f32.s32 s15, s15
80040e8: ee77 7aa6 vadd.f32 s15, s15, s13
80040ec: ee77 7aa5 vadd.f32 s15, s15, s11
80040f0: ee67 7a86 vmul.f32 s15, s15, s12
PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ;
80040f4: 4a2d ldr r2, [pc, #180] @ (80041ac <HAL_RCCEx_GetPLL3ClockFreq+0x120>)
80040f6: eeb7 6a00 vmov.f32 s12, #112 @ 0x3f800000 1.0
80040fa: 6c13 ldr r3, [r2, #64] @ 0x40
80040fc: f3c3 2346 ubfx r3, r3, #9, #7
8004100: ee07 3a10 vmov s14, r3
8004104: eeb8 7ac7 vcvt.f32.s32 s14, s14
}
8004108: bc70 pop {r4, r5, r6}
PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ;
800410a: ee37 7a06 vadd.f32 s14, s14, s12
800410e: eec7 6a87 vdiv.f32 s13, s15, s14
8004112: eefc 6ae6 vcvt.u32.f32 s13, s13
8004116: edc0 6a00 vstr s13, [r0]
PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ;
800411a: 6c13 ldr r3, [r2, #64] @ 0x40
800411c: f3c3 4306 ubfx r3, r3, #16, #7
8004120: ee07 3a10 vmov s14, r3
8004124: eeb8 7ac7 vcvt.f32.s32 s14, s14
8004128: ee37 7a06 vadd.f32 s14, s14, s12
800412c: eec7 6a87 vdiv.f32 s13, s15, s14
8004130: eefc 6ae6 vcvt.u32.f32 s13, s13
8004134: edc0 6a01 vstr s13, [r0, #4]
PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ;
8004138: 6c13 ldr r3, [r2, #64] @ 0x40
800413a: f3c3 6306 ubfx r3, r3, #24, #7
800413e: ee06 3a90 vmov s13, r3
8004142: eef8 6ae6 vcvt.f32.s32 s13, s13
8004146: ee76 6a86 vadd.f32 s13, s13, s12
800414a: ee87 7aa6 vdiv.f32 s14, s15, s13
800414e: eefc 7ac7 vcvt.u32.f32 s15, s14
8004152: ee17 3a90 vmov r3, s15
8004156: 6083 str r3, [r0, #8]
}
8004158: 4770 bx lr
800415a: bc70 pop {r4, r5, r6}
PLL3_Clocks->PLL3_P_Frequency = 0U;
800415c: e9c0 3300 strd r3, r3, [r0]
PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ;
8004160: 6083 str r3, [r0, #8]
}
8004162: 4770 bx lr
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
8004164: 6813 ldr r3, [r2, #0]
8004166: 069b lsls r3, r3, #26
8004168: d51d bpl.n 80041a6 <HAL_RCCEx_GetPLL3ClockFreq+0x11a>
hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
800416a: 6814 ldr r4, [r2, #0]
pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
800416c: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
8004170: 6c13 ldr r3, [r2, #64] @ 0x40
hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
8004172: 4910 ldr r1, [pc, #64] @ (80041b4 <HAL_RCCEx_GetPLL3ClockFreq+0x128>)
8004174: f3c4 02c1 ubfx r2, r4, #3, #2
pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
8004178: f3c3 0308 ubfx r3, r3, #0, #9
hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
800417c: 40d1 lsrs r1, r2
pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
800417e: ee07 3a90 vmov s15, r3
8004182: ee06 1a10 vmov s12, r1
8004186: eef8 7ae7 vcvt.f32.s32 s15, s15
800418a: eeb8 6ac6 vcvt.f32.s32 s12, s12
800418e: ee77 6aa6 vadd.f32 s13, s15, s13
8004192: eec6 7a07 vdiv.f32 s15, s12, s14
8004196: ee36 7aa5 vadd.f32 s14, s13, s11
800419a: ee67 7a87 vmul.f32 s15, s15, s14
800419e: e7a9 b.n 80040f4 <HAL_RCCEx_GetPLL3ClockFreq+0x68>
pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
80041a0: eddf 7a05 vldr s15, [pc, #20] @ 80041b8 <HAL_RCCEx_GetPLL3ClockFreq+0x12c>
80041a4: e795 b.n 80040d2 <HAL_RCCEx_GetPLL3ClockFreq+0x46>
pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
80041a6: eddf 7a05 vldr s15, [pc, #20] @ 80041bc <HAL_RCCEx_GetPLL3ClockFreq+0x130>
80041aa: e792 b.n 80040d2 <HAL_RCCEx_GetPLL3ClockFreq+0x46>
80041ac: 58024400 .word 0x58024400
80041b0: 4a742400 .word 0x4a742400
80041b4: 03d09000 .word 0x03d09000
80041b8: 4bbebc20 .word 0x4bbebc20
80041bc: 4c742400 .word 0x4c742400
080041c0 <HAL_RCCEx_GetPLL1ClockFreq>:
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
80041c0: 4a47 ldr r2, [pc, #284] @ (80042e0 <HAL_RCCEx_GetPLL1ClockFreq+0x120>)
{
80041c2: b470 push {r4, r5, r6}
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
80041c4: 6a94 ldr r4, [r2, #40] @ 0x28
pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4);
80041c6: 6a95 ldr r5, [r2, #40] @ 0x28
pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
80041c8: 6ad6 ldr r6, [r2, #44] @ 0x2c
if (pll1m != 0U)
80041ca: f415 7f7c tst.w r5, #1008 @ 0x3f0
pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4);
80041ce: f3c5 1305 ubfx r3, r5, #4, #6
fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
80041d2: 6b51 ldr r1, [r2, #52] @ 0x34
if (pll1m != 0U)
80041d4: d05b beq.n 800428e <HAL_RCCEx_GetPLL1ClockFreq+0xce>
fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
80041d6: f3c1 01cc ubfx r1, r1, #3, #13
pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
80041da: f006 0601 and.w r6, r6, #1
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
80041de: f004 0403 and.w r4, r4, #3
pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
80041e2: ee07 3a90 vmov s15, r3
fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
80041e6: fb06 f101 mul.w r1, r6, r1
switch (pllsource)
80041ea: 2c01 cmp r4, #1
pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
80041ec: eeb8 7ae7 vcvt.f32.s32 s14, s15
80041f0: ee06 1a90 vmov s13, r1
80041f4: eefa 6ae9 vcvt.f32.s32 s13, s13, #13
switch (pllsource)
80041f8: d04e beq.n 8004298 <HAL_RCCEx_GetPLL1ClockFreq+0xd8>
80041fa: 2c02 cmp r4, #2
80041fc: d06d beq.n 80042da <HAL_RCCEx_GetPLL1ClockFreq+0x11a>
80041fe: 2c00 cmp r4, #0
8004200: d04d beq.n 800429e <HAL_RCCEx_GetPLL1ClockFreq+0xde>
pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
8004202: eddf 7a38 vldr s15, [pc, #224] @ 80042e4 <HAL_RCCEx_GetPLL1ClockFreq+0x124>
8004206: ee87 6a87 vdiv.f32 s12, s15, s14
800420a: 6b13 ldr r3, [r2, #48] @ 0x30
800420c: f3c3 0308 ubfx r3, r3, #0, #9
8004210: ee07 3a90 vmov s15, r3
8004214: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
8004218: eef8 7ae7 vcvt.f32.s32 s15, s15
800421c: ee77 7aa6 vadd.f32 s15, s15, s13
8004220: ee77 7aa5 vadd.f32 s15, s15, s11
8004224: ee67 7a86 vmul.f32 s15, s15, s12
PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (float_t)1)) ;
8004228: 4a2d ldr r2, [pc, #180] @ (80042e0 <HAL_RCCEx_GetPLL1ClockFreq+0x120>)
800422a: eeb7 6a00 vmov.f32 s12, #112 @ 0x3f800000 1.0
800422e: 6b13 ldr r3, [r2, #48] @ 0x30
8004230: f3c3 2346 ubfx r3, r3, #9, #7
8004234: ee07 3a10 vmov s14, r3
8004238: eeb8 7ac7 vcvt.f32.s32 s14, s14
}
800423c: bc70 pop {r4, r5, r6}
PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (float_t)1)) ;
800423e: ee37 7a06 vadd.f32 s14, s14, s12
8004242: eec7 6a87 vdiv.f32 s13, s15, s14
8004246: eefc 6ae6 vcvt.u32.f32 s13, s13
800424a: edc0 6a00 vstr s13, [r0]
PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ;
800424e: 6b13 ldr r3, [r2, #48] @ 0x30
8004250: f3c3 4306 ubfx r3, r3, #16, #7
8004254: ee07 3a10 vmov s14, r3
8004258: eeb8 7ac7 vcvt.f32.s32 s14, s14
800425c: ee37 7a06 vadd.f32 s14, s14, s12
8004260: eec7 6a87 vdiv.f32 s13, s15, s14
8004264: eefc 6ae6 vcvt.u32.f32 s13, s13
8004268: edc0 6a01 vstr s13, [r0, #4]
PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ;
800426c: 6b13 ldr r3, [r2, #48] @ 0x30
800426e: f3c3 6306 ubfx r3, r3, #24, #7
8004272: ee06 3a90 vmov s13, r3
8004276: eef8 6ae6 vcvt.f32.s32 s13, s13
800427a: ee76 6a86 vadd.f32 s13, s13, s12
800427e: ee87 7aa6 vdiv.f32 s14, s15, s13
8004282: eefc 7ac7 vcvt.u32.f32 s15, s14
8004286: ee17 3a90 vmov r3, s15
800428a: 6083 str r3, [r0, #8]
}
800428c: 4770 bx lr
800428e: bc70 pop {r4, r5, r6}
PLL1_Clocks->PLL1_P_Frequency = 0U;
8004290: e9c0 3300 strd r3, r3, [r0]
PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ;
8004294: 6083 str r3, [r0, #8]
}
8004296: 4770 bx lr
pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
8004298: eddf 7a13 vldr s15, [pc, #76] @ 80042e8 <HAL_RCCEx_GetPLL1ClockFreq+0x128>
800429c: e7b3 b.n 8004206 <HAL_RCCEx_GetPLL1ClockFreq+0x46>
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
800429e: 6813 ldr r3, [r2, #0]
80042a0: 069b lsls r3, r3, #26
80042a2: d5ae bpl.n 8004202 <HAL_RCCEx_GetPLL1ClockFreq+0x42>
hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
80042a4: 6814 ldr r4, [r2, #0]
pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
80042a6: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0
80042aa: 6b13 ldr r3, [r2, #48] @ 0x30
hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
80042ac: 490f ldr r1, [pc, #60] @ (80042ec <HAL_RCCEx_GetPLL1ClockFreq+0x12c>)
80042ae: f3c4 02c1 ubfx r2, r4, #3, #2
pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
80042b2: f3c3 0308 ubfx r3, r3, #0, #9
hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
80042b6: 40d1 lsrs r1, r2
pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
80042b8: ee07 3a90 vmov s15, r3
80042bc: ee06 1a10 vmov s12, r1
80042c0: eef8 7ae7 vcvt.f32.s32 s15, s15
80042c4: eeb8 6ac6 vcvt.f32.s32 s12, s12
80042c8: ee77 6aa6 vadd.f32 s13, s15, s13
80042cc: eec6 7a07 vdiv.f32 s15, s12, s14
80042d0: ee36 7aa5 vadd.f32 s14, s13, s11
80042d4: ee67 7a87 vmul.f32 s15, s15, s14
80042d8: e7a6 b.n 8004228 <HAL_RCCEx_GetPLL1ClockFreq+0x68>
pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
80042da: eddf 7a05 vldr s15, [pc, #20] @ 80042f0 <HAL_RCCEx_GetPLL1ClockFreq+0x130>
80042de: e792 b.n 8004206 <HAL_RCCEx_GetPLL1ClockFreq+0x46>
80042e0: 58024400 .word 0x58024400
80042e4: 4c742400 .word 0x4c742400
80042e8: 4a742400 .word 0x4a742400
80042ec: 03d09000 .word 0x03d09000
80042f0: 4bbebc20 .word 0x4bbebc20
080042f4 <HAL_RCCEx_GetPeriphCLKFreq>:
if (PeriphClk == RCC_PERIPHCLK_SAI1)
80042f4: f5a0 7380 sub.w r3, r0, #256 @ 0x100
80042f8: 430b orrs r3, r1
{
80042fa: b500 push {lr}
80042fc: b085 sub sp, #20
if (PeriphClk == RCC_PERIPHCLK_SAI1)
80042fe: d04c beq.n 800439a <HAL_RCCEx_GetPeriphCLKFreq+0xa6>
else if (PeriphClk == RCC_PERIPHCLK_SAI23)
8004300: f5a0 7300 sub.w r3, r0, #512 @ 0x200
8004304: 430b orrs r3, r1
8004306: d036 beq.n 8004376 <HAL_RCCEx_GetPeriphCLKFreq+0x82>
else if (PeriphClk == RCC_PERIPHCLK_SAI4A)
8004308: f5a0 6380 sub.w r3, r0, #1024 @ 0x400
800430c: 430b orrs r3, r1
800430e: d06c beq.n 80043ea <HAL_RCCEx_GetPeriphCLKFreq+0xf6>
else if (PeriphClk == RCC_PERIPHCLK_SAI4B)
8004310: f5a0 6300 sub.w r3, r0, #2048 @ 0x800
8004314: 430b orrs r3, r1
8004316: d04b beq.n 80043b0 <HAL_RCCEx_GetPeriphCLKFreq+0xbc>
else if (PeriphClk == RCC_PERIPHCLK_SPI123)
8004318: f5a0 5380 sub.w r3, r0, #4096 @ 0x1000
800431c: 430b orrs r3, r1
800431e: f000 80b6 beq.w 800448e <HAL_RCCEx_GetPeriphCLKFreq+0x19a>
else if (PeriphClk == RCC_PERIPHCLK_SPI45)
8004322: f5a0 5300 sub.w r3, r0, #8192 @ 0x2000
8004326: 430b orrs r3, r1
8004328: f000 80ec beq.w 8004504 <HAL_RCCEx_GetPeriphCLKFreq+0x210>
else if (PeriphClk == RCC_PERIPHCLK_ADC)
800432c: f5a0 2300 sub.w r3, r0, #524288 @ 0x80000
8004330: 430b orrs r3, r1
8004332: d069 beq.n 8004408 <HAL_RCCEx_GetPeriphCLKFreq+0x114>
else if (PeriphClk == RCC_PERIPHCLK_SDMMC)
8004334: f5a0 3380 sub.w r3, r0, #65536 @ 0x10000
8004338: 430b orrs r3, r1
800433a: f000 80d6 beq.w 80044ea <HAL_RCCEx_GetPeriphCLKFreq+0x1f6>
else if (PeriphClk == RCC_PERIPHCLK_SPI6)
800433e: f5a0 4380 sub.w r3, r0, #16384 @ 0x4000
8004342: 430b orrs r3, r1
8004344: f000 8109 beq.w 800455a <HAL_RCCEx_GetPeriphCLKFreq+0x266>
else if (PeriphClk == RCC_PERIPHCLK_FDCAN)
8004348: f5a0 4000 sub.w r0, r0, #32768 @ 0x8000
800434c: 4308 orrs r0, r1
800434e: d120 bne.n 8004392 <HAL_RCCEx_GetPeriphCLKFreq+0x9e>
srcclk = __HAL_RCC_GET_FDCAN_SOURCE();
8004350: 4a95 ldr r2, [pc, #596] @ (80045a8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b4>)
8004352: 6d13 ldr r3, [r2, #80] @ 0x50
8004354: f003 5340 and.w r3, r3, #805306368 @ 0x30000000
switch (srcclk)
8004358: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
800435c: f000 80aa beq.w 80044b4 <HAL_RCCEx_GetPeriphCLKFreq+0x1c0>
8004360: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8004364: f000 8116 beq.w 8004594 <HAL_RCCEx_GetPeriphCLKFreq+0x2a0>
8004368: b99b cbnz r3, 8004392 <HAL_RCCEx_GetPeriphCLKFreq+0x9e>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
800436a: 6810 ldr r0, [r2, #0]
800436c: f410 3000 ands.w r0, r0, #131072 @ 0x20000
8004370: d047 beq.n 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
frequency = HSE_VALUE;
8004372: 488e ldr r0, [pc, #568] @ (80045ac <HAL_RCCEx_GetPeriphCLKFreq+0x2b8>)
return frequency;
8004374: e045 b.n 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
saiclocksource = __HAL_RCC_GET_SAI23_SOURCE();
8004376: 4a8c ldr r2, [pc, #560] @ (80045a8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b4>)
8004378: 6d13 ldr r3, [r2, #80] @ 0x50
800437a: f403 73e0 and.w r3, r3, #448 @ 0x1c0
switch (saiclocksource)
800437e: 2b80 cmp r3, #128 @ 0x80
8004380: f000 8093 beq.w 80044aa <HAL_RCCEx_GetPeriphCLKFreq+0x1b6>
8004384: f240 808b bls.w 800449e <HAL_RCCEx_GetPeriphCLKFreq+0x1aa>
8004388: 2bc0 cmp r3, #192 @ 0xc0
800438a: d039 beq.n 8004400 <HAL_RCCEx_GetPeriphCLKFreq+0x10c>
800438c: f5b3 7f80 cmp.w r3, #256 @ 0x100
8004390: d05c beq.n 800444c <HAL_RCCEx_GetPeriphCLKFreq+0x158>
frequency = 0;
8004392: 2000 movs r0, #0
}
8004394: b005 add sp, #20
8004396: f85d fb04 ldr.w pc, [sp], #4
saiclocksource = __HAL_RCC_GET_SAI1_SOURCE();
800439a: 4b83 ldr r3, [pc, #524] @ (80045a8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b4>)
800439c: 6d1b ldr r3, [r3, #80] @ 0x50
800439e: f003 0307 and.w r3, r3, #7
switch (saiclocksource)
80043a2: 2b04 cmp r3, #4
80043a4: d8f5 bhi.n 8004392 <HAL_RCCEx_GetPeriphCLKFreq+0x9e>
80043a6: e8df f003 tbb [pc, r3]
80043aa: 3c68 .short 0x3c68
80043ac: 2b46 .short 0x2b46
80043ae: 50 .byte 0x50
80043af: 00 .byte 0x00
saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE();
80043b0: 4a7d ldr r2, [pc, #500] @ (80045a8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b4>)
80043b2: 6d93 ldr r3, [r2, #88] @ 0x58
80043b4: f003 63e0 and.w r3, r3, #117440512 @ 0x7000000
switch (saiclocksource)
80043b8: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
80043bc: d075 beq.n 80044aa <HAL_RCCEx_GetPeriphCLKFreq+0x1b6>
80043be: d96e bls.n 800449e <HAL_RCCEx_GetPeriphCLKFreq+0x1aa>
80043c0: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000
80043c4: d01c beq.n 8004400 <HAL_RCCEx_GetPeriphCLKFreq+0x10c>
80043c6: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
80043ca: d1e2 bne.n 8004392 <HAL_RCCEx_GetPeriphCLKFreq+0x9e>
ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
80043cc: 6cd3 ldr r3, [r2, #76] @ 0x4c
if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
80043ce: 6812 ldr r2, [r2, #0]
ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
80043d0: f003 5340 and.w r3, r3, #805306368 @ 0x30000000
if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
80043d4: 0752 lsls r2, r2, #29
80043d6: d541 bpl.n 800445c <HAL_RCCEx_GetPeriphCLKFreq+0x168>
80043d8: 2b00 cmp r3, #0
80043da: d13f bne.n 800445c <HAL_RCCEx_GetPeriphCLKFreq+0x168>
frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
80043dc: 4b72 ldr r3, [pc, #456] @ (80045a8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b4>)
80043de: 4874 ldr r0, [pc, #464] @ (80045b0 <HAL_RCCEx_GetPeriphCLKFreq+0x2bc>)
80043e0: 681b ldr r3, [r3, #0]
80043e2: f3c3 03c1 ubfx r3, r3, #3, #2
80043e6: 40d8 lsrs r0, r3
80043e8: e00b b.n 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE();
80043ea: 4a6f ldr r2, [pc, #444] @ (80045a8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b4>)
80043ec: 6d93 ldr r3, [r2, #88] @ 0x58
80043ee: f403 0360 and.w r3, r3, #14680064 @ 0xe00000
switch (saiclocksource)
80043f2: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
80043f6: d058 beq.n 80044aa <HAL_RCCEx_GetPeriphCLKFreq+0x1b6>
80043f8: d951 bls.n 800449e <HAL_RCCEx_GetPeriphCLKFreq+0x1aa>
80043fa: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000
80043fe: d15e bne.n 80044be <HAL_RCCEx_GetPeriphCLKFreq+0x1ca>
frequency = EXTERNAL_CLOCK_VALUE;
8004400: 486c ldr r0, [pc, #432] @ (80045b4 <HAL_RCCEx_GetPeriphCLKFreq+0x2c0>)
}
8004402: b005 add sp, #20
8004404: f85d fb04 ldr.w pc, [sp], #4
srcclk = __HAL_RCC_GET_ADC_SOURCE();
8004408: 4a67 ldr r2, [pc, #412] @ (80045a8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b4>)
800440a: 6d93 ldr r3, [r2, #88] @ 0x58
800440c: f403 3340 and.w r3, r3, #196608 @ 0x30000
switch (srcclk)
8004410: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8004414: f000 80df beq.w 80045d6 <HAL_RCCEx_GetPeriphCLKFreq+0x2e2>
8004418: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
800441c: d0d6 beq.n 80043cc <HAL_RCCEx_GetPeriphCLKFreq+0xd8>
800441e: 2b00 cmp r3, #0
8004420: d1b7 bne.n 8004392 <HAL_RCCEx_GetPeriphCLKFreq+0x9e>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
8004422: 4b61 ldr r3, [pc, #388] @ (80045a8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b4>)
8004424: 6818 ldr r0, [r3, #0]
8004426: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000
800442a: d0ea beq.n 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
800442c: a801 add r0, sp, #4
800442e: f7ff fd93 bl 8003f58 <HAL_RCCEx_GetPLL2ClockFreq>
frequency = pll2_clocks.PLL2_P_Frequency;
8004432: 9801 ldr r0, [sp, #4]
8004434: e7e5 b.n 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
8004436: 4b5c ldr r3, [pc, #368] @ (80045a8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b4>)
8004438: 6818 ldr r0, [r3, #0]
800443a: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000
800443e: d0e0 beq.n 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
8004440: a801 add r0, sp, #4
8004442: f7ff fe23 bl 800408c <HAL_RCCEx_GetPLL3ClockFreq>
frequency = pll3_clocks.PLL3_P_Frequency;
8004446: 9801 ldr r0, [sp, #4]
8004448: e7db b.n 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
800444a: 4a57 ldr r2, [pc, #348] @ (80045a8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b4>)
ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
800444c: 6cd3 ldr r3, [r2, #76] @ 0x4c
if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
800444e: 6811 ldr r1, [r2, #0]
ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
8004450: f003 5340 and.w r3, r3, #805306368 @ 0x30000000
if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
8004454: 0749 lsls r1, r1, #29
8004456: d501 bpl.n 800445c <HAL_RCCEx_GetPeriphCLKFreq+0x168>
8004458: 2b00 cmp r3, #0
800445a: d038 beq.n 80044ce <HAL_RCCEx_GetPeriphCLKFreq+0x1da>
else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
800445c: 4a52 ldr r2, [pc, #328] @ (80045a8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b4>)
800445e: 6812 ldr r2, [r2, #0]
8004460: 05d0 lsls r0, r2, #23
8004462: d502 bpl.n 800446a <HAL_RCCEx_GetPeriphCLKFreq+0x176>
8004464: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
8004468: d067 beq.n 800453a <HAL_RCCEx_GetPeriphCLKFreq+0x246>
else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
800446a: 4a4f ldr r2, [pc, #316] @ (80045a8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b4>)
800446c: 6812 ldr r2, [r2, #0]
800446e: 0391 lsls r1, r2, #14
8004470: d58f bpl.n 8004392 <HAL_RCCEx_GetPeriphCLKFreq+0x9e>
8004472: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8004476: d18c bne.n 8004392 <HAL_RCCEx_GetPeriphCLKFreq+0x9e>
8004478: e77b b.n 8004372 <HAL_RCCEx_GetPeriphCLKFreq+0x7e>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
800447a: 4b4b ldr r3, [pc, #300] @ (80045a8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b4>)
800447c: 6818 ldr r0, [r3, #0]
800447e: f010 7000 ands.w r0, r0, #33554432 @ 0x2000000
8004482: d0be beq.n 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
8004484: a801 add r0, sp, #4
8004486: f7ff fe9b bl 80041c0 <HAL_RCCEx_GetPLL1ClockFreq>
frequency = pll1_clocks.PLL1_Q_Frequency;
800448a: 9802 ldr r0, [sp, #8]
800448c: e7b9 b.n 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
srcclk = __HAL_RCC_GET_SPI123_SOURCE();
800448e: 4a46 ldr r2, [pc, #280] @ (80045a8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b4>)
8004490: 6d13 ldr r3, [r2, #80] @ 0x50
8004492: f403 43e0 and.w r3, r3, #28672 @ 0x7000
switch (srcclk)
8004496: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
800449a: d006 beq.n 80044aa <HAL_RCCEx_GetPeriphCLKFreq+0x1b6>
800449c: d81d bhi.n 80044da <HAL_RCCEx_GetPeriphCLKFreq+0x1e6>
800449e: b14b cbz r3, 80044b4 <HAL_RCCEx_GetPeriphCLKFreq+0x1c0>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
80044a0: 6810 ldr r0, [r2, #0]
80044a2: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000
80044a6: d0ac beq.n 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
80044a8: e7c0 b.n 800442c <HAL_RCCEx_GetPeriphCLKFreq+0x138>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
80044aa: 6810 ldr r0, [r2, #0]
80044ac: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000
80044b0: d0a7 beq.n 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
80044b2: e7c5 b.n 8004440 <HAL_RCCEx_GetPeriphCLKFreq+0x14c>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
80044b4: 6810 ldr r0, [r2, #0]
80044b6: f010 7000 ands.w r0, r0, #33554432 @ 0x2000000
80044ba: d0a2 beq.n 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
80044bc: e7e2 b.n 8004484 <HAL_RCCEx_GetPeriphCLKFreq+0x190>
switch (saiclocksource)
80044be: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
80044c2: d0c3 beq.n 800444c <HAL_RCCEx_GetPeriphCLKFreq+0x158>
80044c4: e765 b.n 8004392 <HAL_RCCEx_GetPeriphCLKFreq+0x9e>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
80044c6: 6810 ldr r0, [r2, #0]
80044c8: f010 0004 ands.w r0, r0, #4
80044cc: d099 beq.n 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
80044ce: 6813 ldr r3, [r2, #0]
80044d0: 4837 ldr r0, [pc, #220] @ (80045b0 <HAL_RCCEx_GetPeriphCLKFreq+0x2bc>)
80044d2: f3c3 03c1 ubfx r3, r3, #3, #2
80044d6: 40d8 lsrs r0, r3
80044d8: e793 b.n 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
switch (srcclk)
80044da: f5b3 5f40 cmp.w r3, #12288 @ 0x3000
80044de: d08f beq.n 8004400 <HAL_RCCEx_GetPeriphCLKFreq+0x10c>
80044e0: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
80044e4: f43f af72 beq.w 80043cc <HAL_RCCEx_GetPeriphCLKFreq+0xd8>
80044e8: e753 b.n 8004392 <HAL_RCCEx_GetPeriphCLKFreq+0x9e>
srcclk = __HAL_RCC_GET_SDMMC_SOURCE();
80044ea: 4b2f ldr r3, [pc, #188] @ (80045a8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b4>)
80044ec: 6cda ldr r2, [r3, #76] @ 0x4c
switch (srcclk)
80044ee: 03d2 lsls r2, r2, #15
80044f0: d5c4 bpl.n 800447c <HAL_RCCEx_GetPeriphCLKFreq+0x188>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
80044f2: 6818 ldr r0, [r3, #0]
80044f4: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000
80044f8: d083 beq.n 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
80044fa: a801 add r0, sp, #4
80044fc: f7ff fd2c bl 8003f58 <HAL_RCCEx_GetPLL2ClockFreq>
frequency = pll2_clocks.PLL2_R_Frequency;
8004500: 9803 ldr r0, [sp, #12]
8004502: e77e b.n 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
srcclk = __HAL_RCC_GET_SPI45_SOURCE();
8004504: 4a28 ldr r2, [pc, #160] @ (80045a8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b4>)
8004506: 6d13 ldr r3, [r2, #80] @ 0x50
8004508: f403 23e0 and.w r3, r3, #458752 @ 0x70000
switch (srcclk)
800450c: f5b3 3f40 cmp.w r3, #196608 @ 0x30000
8004510: d0d9 beq.n 80044c6 <HAL_RCCEx_GetPeriphCLKFreq+0x1d2>
8004512: d814 bhi.n 800453e <HAL_RCCEx_GetPeriphCLKFreq+0x24a>
8004514: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8004518: d03c beq.n 8004594 <HAL_RCCEx_GetPeriphCLKFreq+0x2a0>
800451a: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
800451e: d04f beq.n 80045c0 <HAL_RCCEx_GetPeriphCLKFreq+0x2cc>
8004520: 2b00 cmp r3, #0
8004522: f47f af36 bne.w 8004392 <HAL_RCCEx_GetPeriphCLKFreq+0x9e>
}
8004526: b005 add sp, #20
8004528: f85d eb04 ldr.w lr, [sp], #4
frequency = HAL_RCC_GetPCLK1Freq();
800452c: f7fe bc4e b.w 8002dcc <HAL_RCC_GetPCLK1Freq>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY))
8004530: 6810 ldr r0, [r2, #0]
8004532: f410 7080 ands.w r0, r0, #256 @ 0x100
8004536: f43f af64 beq.w 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
frequency = CSI_VALUE;
800453a: 481f ldr r0, [pc, #124] @ (80045b8 <HAL_RCCEx_GetPeriphCLKFreq+0x2c4>)
800453c: e761 b.n 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
switch (srcclk)
800453e: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
8004542: d0f5 beq.n 8004530 <HAL_RCCEx_GetPeriphCLKFreq+0x23c>
8004544: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8004548: f47f af23 bne.w 8004392 <HAL_RCCEx_GetPeriphCLKFreq+0x9e>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
800454c: 4b16 ldr r3, [pc, #88] @ (80045a8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b4>)
800454e: 6818 ldr r0, [r3, #0]
8004550: f410 3000 ands.w r0, r0, #131072 @ 0x20000
8004554: f43f af55 beq.w 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
8004558: e70b b.n 8004372 <HAL_RCCEx_GetPeriphCLKFreq+0x7e>
srcclk = __HAL_RCC_GET_SPI6_SOURCE();
800455a: 4b13 ldr r3, [pc, #76] @ (80045a8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b4>)
800455c: 6d9b ldr r3, [r3, #88] @ 0x58
800455e: f003 43e0 and.w r3, r3, #1879048192 @ 0x70000000
switch (srcclk)
8004562: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000
8004566: d04e beq.n 8004606 <HAL_RCCEx_GetPeriphCLKFreq+0x312>
8004568: d83f bhi.n 80045ea <HAL_RCCEx_GetPeriphCLKFreq+0x2f6>
800456a: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
800456e: d043 beq.n 80045f8 <HAL_RCCEx_GetPeriphCLKFreq+0x304>
8004570: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8004574: d024 beq.n 80045c0 <HAL_RCCEx_GetPeriphCLKFreq+0x2cc>
8004576: 2b00 cmp r3, #0
8004578: f47f af0b bne.w 8004392 <HAL_RCCEx_GetPeriphCLKFreq+0x9e>
return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU));
800457c: f7fe fbe6 bl 8002d4c <HAL_RCC_GetHCLKFreq>
8004580: 4b09 ldr r3, [pc, #36] @ (80045a8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b4>)
8004582: 4a0e ldr r2, [pc, #56] @ (80045bc <HAL_RCCEx_GetPeriphCLKFreq+0x2c8>)
8004584: 6a1b ldr r3, [r3, #32]
8004586: f3c3 1302 ubfx r3, r3, #4, #3
800458a: 5cd3 ldrb r3, [r2, r3]
800458c: f003 031f and.w r3, r3, #31
8004590: 40d8 lsrs r0, r3
break;
8004592: e736 b.n 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
8004594: 6810 ldr r0, [r2, #0]
8004596: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000
800459a: f43f af32 beq.w 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
800459e: a801 add r0, sp, #4
80045a0: f7ff fcda bl 8003f58 <HAL_RCCEx_GetPLL2ClockFreq>
frequency = pll2_clocks.PLL2_Q_Frequency;
80045a4: 9802 ldr r0, [sp, #8]
80045a6: e72c b.n 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
80045a8: 58024400 .word 0x58024400
80045ac: 017d7840 .word 0x017d7840
80045b0: 03d09000 .word 0x03d09000
80045b4: 00bb8000 .word 0x00bb8000
80045b8: 003d0900 .word 0x003d0900
80045bc: 08005618 .word 0x08005618
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
80045c0: 4b1a ldr r3, [pc, #104] @ (800462c <HAL_RCCEx_GetPeriphCLKFreq+0x338>)
80045c2: 6818 ldr r0, [r3, #0]
80045c4: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000
80045c8: f43f af1b beq.w 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
80045cc: a801 add r0, sp, #4
80045ce: f7ff fd5d bl 800408c <HAL_RCCEx_GetPLL3ClockFreq>
frequency = pll3_clocks.PLL3_Q_Frequency;
80045d2: 9802 ldr r0, [sp, #8]
80045d4: e715 b.n 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
80045d6: 6810 ldr r0, [r2, #0]
80045d8: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000
80045dc: f43f af11 beq.w 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
80045e0: a801 add r0, sp, #4
80045e2: f7ff fd53 bl 800408c <HAL_RCCEx_GetPLL3ClockFreq>
frequency = pll3_clocks.PLL3_R_Frequency;
80045e6: 9803 ldr r0, [sp, #12]
80045e8: e70b b.n 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
switch (srcclk)
80045ea: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80045ee: d016 beq.n 800461e <HAL_RCCEx_GetPeriphCLKFreq+0x32a>
80045f0: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
80045f4: d0aa beq.n 800454c <HAL_RCCEx_GetPeriphCLKFreq+0x258>
80045f6: e6cc b.n 8004392 <HAL_RCCEx_GetPeriphCLKFreq+0x9e>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
80045f8: 4b0c ldr r3, [pc, #48] @ (800462c <HAL_RCCEx_GetPeriphCLKFreq+0x338>)
80045fa: 6818 ldr r0, [r3, #0]
80045fc: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000
8004600: f43f aeff beq.w 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
8004604: e7cb b.n 800459e <HAL_RCCEx_GetPeriphCLKFreq+0x2aa>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
8004606: 4b09 ldr r3, [pc, #36] @ (800462c <HAL_RCCEx_GetPeriphCLKFreq+0x338>)
8004608: 6818 ldr r0, [r3, #0]
800460a: f010 0004 ands.w r0, r0, #4
800460e: f43f aef8 beq.w 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
8004612: 681b ldr r3, [r3, #0]
8004614: 4806 ldr r0, [pc, #24] @ (8004630 <HAL_RCCEx_GetPeriphCLKFreq+0x33c>)
8004616: f3c3 03c1 ubfx r3, r3, #3, #2
800461a: 40d8 lsrs r0, r3
800461c: e6f1 b.n 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY))
800461e: 4b03 ldr r3, [pc, #12] @ (800462c <HAL_RCCEx_GetPeriphCLKFreq+0x338>)
8004620: 6818 ldr r0, [r3, #0]
8004622: f410 7080 ands.w r0, r0, #256 @ 0x100
8004626: f43f aeec beq.w 8004402 <HAL_RCCEx_GetPeriphCLKFreq+0x10e>
800462a: e786 b.n 800453a <HAL_RCCEx_GetPeriphCLKFreq+0x246>
800462c: 58024400 .word 0x58024400
8004630: 03d09000 .word 0x03d09000
08004634 <HAL_TIM_Base_Init>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
/* Check the TIM handle allocation */
if (htim == NULL)
8004634: 2800 cmp r0, #0
8004636: f000 8095 beq.w 8004764 <HAL_TIM_Base_Init+0x130>
{
800463a: b5f8 push {r3, r4, r5, r6, r7, lr}
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
800463c: f890 303d ldrb.w r3, [r0, #61] @ 0x3d
8004640: 4604 mov r4, r0
8004642: f003 02ff and.w r2, r3, #255 @ 0xff
8004646: 2b00 cmp r3, #0
8004648: f000 8087 beq.w 800475a <HAL_TIM_Base_Init+0x126>
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
800464c: 6823 ldr r3, [r4, #0]
htim->State = HAL_TIM_STATE_BUSY;
800464e: 2202 movs r2, #2
{
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8004650: 4945 ldr r1, [pc, #276] @ (8004768 <HAL_TIM_Base_Init+0x134>)
8004652: 4d46 ldr r5, [pc, #280] @ (800476c <HAL_TIM_Base_Init+0x138>)
8004654: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8004658: eba3 0101 sub.w r1, r3, r1
htim->State = HAL_TIM_STATE_BUSY;
800465c: f884 203d strb.w r2, [r4, #61] @ 0x3d
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8004660: eba3 0e05 sub.w lr, r3, r5
tmpcr1 = TIMx->CR1;
8004664: 681a ldr r2, [r3, #0]
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8004666: fab1 f181 clz r1, r1
tmpcr1 &= ~TIM_CR1_CKD;
tmpcr1 |= (uint32_t)Structure->ClockDivision;
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
800466a: 69a0 ldr r0, [r4, #24]
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
800466c: fabe fe8e clz lr, lr
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8004670: 68e7 ldr r7, [r4, #12]
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8004672: ea4f 1151 mov.w r1, r1, lsr #5
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8004676: 6866 ldr r6, [r4, #4]
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8004678: ea4f 1e5e mov.w lr, lr, lsr #5
800467c: d01f beq.n 80046be <HAL_TIM_Base_Init+0x8a>
800467e: b9f1 cbnz r1, 80046be <HAL_TIM_Base_Init+0x8a>
8004680: f8df c0f8 ldr.w ip, [pc, #248] @ 800477c <HAL_TIM_Base_Init+0x148>
8004684: 4563 cmp r3, ip
8004686: d050 beq.n 800472a <HAL_TIM_Base_Init+0xf6>
8004688: f50c 6c80 add.w ip, ip, #1024 @ 0x400
800468c: 4563 cmp r3, ip
800468e: d04c beq.n 800472a <HAL_TIM_Base_Init+0xf6>
8004690: f50c 6c80 add.w ip, ip, #1024 @ 0x400
8004694: 4563 cmp r3, ip
8004696: d012 beq.n 80046be <HAL_TIM_Base_Init+0x8a>
8004698: f1be 0f00 cmp.w lr, #0
800469c: d10f bne.n 80046be <HAL_TIM_Base_Init+0x8a>
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
800469e: 4d34 ldr r5, [pc, #208] @ (8004770 <HAL_TIM_Base_Init+0x13c>)
80046a0: 4934 ldr r1, [pc, #208] @ (8004774 <HAL_TIM_Base_Init+0x140>)
80046a2: 428b cmp r3, r1
80046a4: bf18 it ne
80046a6: 42ab cmpne r3, r5
80046a8: d043 beq.n 8004732 <HAL_TIM_Base_Init+0xfe>
80046aa: f501 6180 add.w r1, r1, #1024 @ 0x400
80046ae: 428b cmp r3, r1
80046b0: d03f beq.n 8004732 <HAL_TIM_Base_Init+0xfe>
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
80046b2: f022 0280 bic.w r2, r2, #128 @ 0x80
TIMx->ARR = (uint32_t)Structure->Period ;
80046b6: 62df str r7, [r3, #44] @ 0x2c
TIMx->PSC = Structure->Prescaler;
80046b8: 629e str r6, [r3, #40] @ 0x28
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
80046ba: 4310 orrs r0, r2
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
80046bc: e014 b.n 80046e8 <HAL_TIM_Base_Init+0xb4>
tmpcr1 |= Structure->CounterMode;
80046be: 68a5 ldr r5, [r4, #8]
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
80046c0: f022 0270 bic.w r2, r2, #112 @ 0x70
tmpcr1 |= (uint32_t)Structure->ClockDivision;
80046c4: f8d4 c010 ldr.w ip, [r4, #16]
tmpcr1 |= Structure->CounterMode;
80046c8: 432a orrs r2, r5
TIMx->ARR = (uint32_t)Structure->Period ;
80046ca: 62df str r7, [r3, #44] @ 0x2c
TIMx->PSC = Structure->Prescaler;
80046cc: 629e str r6, [r3, #40] @ 0x28
tmpcr1 &= ~TIM_CR1_CKD;
80046ce: f422 7240 bic.w r2, r2, #768 @ 0x300
tmpcr1 |= (uint32_t)Structure->ClockDivision;
80046d2: ea42 020c orr.w r2, r2, ip
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
80046d6: f022 0280 bic.w r2, r2, #128 @ 0x80
80046da: 4310 orrs r0, r2
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
80046dc: b911 cbnz r1, 80046e4 <HAL_TIM_Base_Init+0xb0>
80046de: f1be 0f00 cmp.w lr, #0
80046e2: d02f beq.n 8004744 <HAL_TIM_Base_Init+0x110>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
80046e4: 6962 ldr r2, [r4, #20]
80046e6: 631a str r2, [r3, #48] @ 0x30
}
/* Disable Update Event (UEV) with Update Generation (UG)
by changing Update Request Source (URS) to avoid Update flag (UIF) */
SET_BIT(TIMx->CR1, TIM_CR1_URS);
80046e8: 6819 ldr r1, [r3, #0]
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
80046ea: 2201 movs r2, #1
SET_BIT(TIMx->CR1, TIM_CR1_URS);
80046ec: f041 0104 orr.w r1, r1, #4
80046f0: 6019 str r1, [r3, #0]
TIMx->EGR = TIM_EGR_UG;
80046f2: 615a str r2, [r3, #20]
TIMx->CR1 = tmpcr1;
80046f4: 6018 str r0, [r3, #0]
return HAL_OK;
80046f6: 2000 movs r0, #0
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
80046f8: f884 2048 strb.w r2, [r4, #72] @ 0x48
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80046fc: f884 203e strb.w r2, [r4, #62] @ 0x3e
8004700: f884 203f strb.w r2, [r4, #63] @ 0x3f
8004704: f884 2040 strb.w r2, [r4, #64] @ 0x40
8004708: f884 2041 strb.w r2, [r4, #65] @ 0x41
800470c: f884 2042 strb.w r2, [r4, #66] @ 0x42
8004710: f884 2043 strb.w r2, [r4, #67] @ 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8004714: f884 2044 strb.w r2, [r4, #68] @ 0x44
8004718: f884 2045 strb.w r2, [r4, #69] @ 0x45
800471c: f884 2046 strb.w r2, [r4, #70] @ 0x46
8004720: f884 2047 strb.w r2, [r4, #71] @ 0x47
htim->State = HAL_TIM_STATE_READY;
8004724: f884 203d strb.w r2, [r4, #61] @ 0x3d
}
8004728: bdf8 pop {r3, r4, r5, r6, r7, pc}
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
800472a: f022 0270 bic.w r2, r2, #112 @ 0x70
tmpcr1 |= Structure->CounterMode;
800472e: 68a1 ldr r1, [r4, #8]
8004730: 430a orrs r2, r1
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8004732: 6921 ldr r1, [r4, #16]
tmpcr1 &= ~TIM_CR1_CKD;
8004734: f422 7240 bic.w r2, r2, #768 @ 0x300
TIMx->ARR = (uint32_t)Structure->Period ;
8004738: 62df str r7, [r3, #44] @ 0x2c
tmpcr1 |= (uint32_t)Structure->ClockDivision;
800473a: 430a orrs r2, r1
TIMx->PSC = Structure->Prescaler;
800473c: 629e str r6, [r3, #40] @ 0x28
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
800473e: f022 0280 bic.w r2, r2, #128 @ 0x80
8004742: 4310 orrs r0, r2
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8004744: 490c ldr r1, [pc, #48] @ (8004778 <HAL_TIM_Base_Init+0x144>)
8004746: 4a0a ldr r2, [pc, #40] @ (8004770 <HAL_TIM_Base_Init+0x13c>)
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8004748: 4293 cmp r3, r2
800474a: bf18 it ne
800474c: 428b cmpne r3, r1
800474e: d0c9 beq.n 80046e4 <HAL_TIM_Base_Init+0xb0>
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8004750: f502 6280 add.w r2, r2, #1024 @ 0x400
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8004754: 4293 cmp r3, r2
8004756: d0c5 beq.n 80046e4 <HAL_TIM_Base_Init+0xb0>
8004758: e7c6 b.n 80046e8 <HAL_TIM_Base_Init+0xb4>
htim->Lock = HAL_UNLOCKED;
800475a: f880 203c strb.w r2, [r0, #60] @ 0x3c
HAL_TIM_Base_MspInit(htim);
800475e: f7fc f9fd bl 8000b5c <HAL_TIM_Base_MspInit>
8004762: e773 b.n 800464c <HAL_TIM_Base_Init+0x18>
return HAL_ERROR;
8004764: 2001 movs r0, #1
}
8004766: 4770 bx lr
8004768: 40010000 .word 0x40010000
800476c: 40010400 .word 0x40010400
8004770: 40014000 .word 0x40014000
8004774: 40014400 .word 0x40014400
8004778: 40014800 .word 0x40014800
800477c: 40000400 .word 0x40000400
08004780 <HAL_TIM_PeriodElapsedCallback>:
__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
8004780: 4770 bx lr
8004782: bf00 nop
08004784 <HAL_TIM_OC_DelayElapsedCallback>:
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
8004784: 4770 bx lr
8004786: bf00 nop
08004788 <HAL_TIM_IC_CaptureCallback>:
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
8004788: 4770 bx lr
800478a: bf00 nop
0800478c <HAL_TIM_PWM_PulseFinishedCallback>:
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
800478c: 4770 bx lr
800478e: bf00 nop
08004790 <HAL_TIM_TriggerCallback>:
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
8004790: 4770 bx lr
8004792: bf00 nop
08004794 <HAL_TIM_IRQHandler>:
uint32_t itsource = htim->Instance->DIER;
8004794: 6803 ldr r3, [r0, #0]
{
8004796: b570 push {r4, r5, r6, lr}
uint32_t itsource = htim->Instance->DIER;
8004798: 68de ldr r6, [r3, #12]
{
800479a: 4604 mov r4, r0
uint32_t itflag = htim->Instance->SR;
800479c: 691d ldr r5, [r3, #16]
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
800479e: 07aa lsls r2, r5, #30
80047a0: d501 bpl.n 80047a6 <HAL_TIM_IRQHandler+0x12>
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
80047a2: 07b1 lsls r1, r6, #30
80047a4: d452 bmi.n 800484c <HAL_TIM_IRQHandler+0xb8>
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
80047a6: 076b lsls r3, r5, #29
80047a8: d501 bpl.n 80047ae <HAL_TIM_IRQHandler+0x1a>
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
80047aa: 0770 lsls r0, r6, #29
80047ac: d43b bmi.n 8004826 <HAL_TIM_IRQHandler+0x92>
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
80047ae: 0729 lsls r1, r5, #28
80047b0: d501 bpl.n 80047b6 <HAL_TIM_IRQHandler+0x22>
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
80047b2: 0732 lsls r2, r6, #28
80047b4: d425 bmi.n 8004802 <HAL_TIM_IRQHandler+0x6e>
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
80047b6: 06e8 lsls r0, r5, #27
80047b8: d501 bpl.n 80047be <HAL_TIM_IRQHandler+0x2a>
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
80047ba: 06f1 lsls r1, r6, #27
80047bc: d411 bmi.n 80047e2 <HAL_TIM_IRQHandler+0x4e>
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
80047be: 07ea lsls r2, r5, #31
80047c0: d501 bpl.n 80047c6 <HAL_TIM_IRQHandler+0x32>
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
80047c2: 07f3 lsls r3, r6, #31
80047c4: d464 bmi.n 8004890 <HAL_TIM_IRQHandler+0xfc>
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
80047c6: f415 5f02 tst.w r5, #8320 @ 0x2080
80047ca: d04c beq.n 8004866 <HAL_TIM_IRQHandler+0xd2>
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
80047cc: 0630 lsls r0, r6, #24
80047ce: d467 bmi.n 80048a0 <HAL_TIM_IRQHandler+0x10c>
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
80047d0: 0668 lsls r0, r5, #25
80047d2: d501 bpl.n 80047d8 <HAL_TIM_IRQHandler+0x44>
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
80047d4: 0671 lsls r1, r6, #25
80047d6: d46d bmi.n 80048b4 <HAL_TIM_IRQHandler+0x120>
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
80047d8: 06aa lsls r2, r5, #26
80047da: d501 bpl.n 80047e0 <HAL_TIM_IRQHandler+0x4c>
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
80047dc: 06b3 lsls r3, r6, #26
80047de: d44e bmi.n 800487e <HAL_TIM_IRQHandler+0xea>
}
80047e0: bd70 pop {r4, r5, r6, pc}
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
80047e2: 6823 ldr r3, [r4, #0]
80047e4: f06f 0210 mvn.w r2, #16
HAL_TIM_IC_CaptureCallback(htim);
80047e8: 4620 mov r0, r4
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
80047ea: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
80047ec: 2208 movs r2, #8
80047ee: 7722 strb r2, [r4, #28]
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
80047f0: 69db ldr r3, [r3, #28]
80047f2: f413 7f40 tst.w r3, #768 @ 0x300
80047f6: d071 beq.n 80048dc <HAL_TIM_IRQHandler+0x148>
HAL_TIM_IC_CaptureCallback(htim);
80047f8: f7ff ffc6 bl 8004788 <HAL_TIM_IC_CaptureCallback>
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
80047fc: 2300 movs r3, #0
80047fe: 7723 strb r3, [r4, #28]
8004800: e7dd b.n 80047be <HAL_TIM_IRQHandler+0x2a>
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
8004802: 6823 ldr r3, [r4, #0]
8004804: f06f 0208 mvn.w r2, #8
HAL_TIM_IC_CaptureCallback(htim);
8004808: 4620 mov r0, r4
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
800480a: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
800480c: 2204 movs r2, #4
800480e: 7722 strb r2, [r4, #28]
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
8004810: 69db ldr r3, [r3, #28]
8004812: 079b lsls r3, r3, #30
8004814: d15f bne.n 80048d6 <HAL_TIM_IRQHandler+0x142>
HAL_TIM_OC_DelayElapsedCallback(htim);
8004816: f7ff ffb5 bl 8004784 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
800481a: 4620 mov r0, r4
800481c: f7ff ffb6 bl 800478c <HAL_TIM_PWM_PulseFinishedCallback>
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8004820: 2300 movs r3, #0
8004822: 7723 strb r3, [r4, #28]
8004824: e7c7 b.n 80047b6 <HAL_TIM_IRQHandler+0x22>
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
8004826: 6823 ldr r3, [r4, #0]
8004828: f06f 0204 mvn.w r2, #4
HAL_TIM_IC_CaptureCallback(htim);
800482c: 4620 mov r0, r4
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
800482e: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
8004830: 2202 movs r2, #2
8004832: 7722 strb r2, [r4, #28]
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
8004834: 699b ldr r3, [r3, #24]
8004836: f413 7f40 tst.w r3, #768 @ 0x300
800483a: d149 bne.n 80048d0 <HAL_TIM_IRQHandler+0x13c>
HAL_TIM_OC_DelayElapsedCallback(htim);
800483c: f7ff ffa2 bl 8004784 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8004840: 4620 mov r0, r4
8004842: f7ff ffa3 bl 800478c <HAL_TIM_PWM_PulseFinishedCallback>
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8004846: 2300 movs r3, #0
8004848: 7723 strb r3, [r4, #28]
800484a: e7b0 b.n 80047ae <HAL_TIM_IRQHandler+0x1a>
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
800484c: f06f 0202 mvn.w r2, #2
8004850: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8004852: 2201 movs r2, #1
8004854: 7702 strb r2, [r0, #28]
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8004856: 699b ldr r3, [r3, #24]
8004858: 079a lsls r2, r3, #30
800485a: d033 beq.n 80048c4 <HAL_TIM_IRQHandler+0x130>
HAL_TIM_IC_CaptureCallback(htim);
800485c: f7ff ff94 bl 8004788 <HAL_TIM_IC_CaptureCallback>
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8004860: 2300 movs r3, #0
8004862: 7723 strb r3, [r4, #28]
8004864: e79f b.n 80047a6 <HAL_TIM_IRQHandler+0x12>
if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
8004866: 05ea lsls r2, r5, #23
8004868: d5b2 bpl.n 80047d0 <HAL_TIM_IRQHandler+0x3c>
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
800486a: 0633 lsls r3, r6, #24
800486c: d5b0 bpl.n 80047d0 <HAL_TIM_IRQHandler+0x3c>
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
800486e: 6823 ldr r3, [r4, #0]
8004870: f46f 7280 mvn.w r2, #256 @ 0x100
HAL_TIMEx_Break2Callback(htim);
8004874: 4620 mov r0, r4
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
8004876: 611a str r2, [r3, #16]
HAL_TIMEx_Break2Callback(htim);
8004878: f000 f894 bl 80049a4 <HAL_TIMEx_Break2Callback>
800487c: e7a8 b.n 80047d0 <HAL_TIM_IRQHandler+0x3c>
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
800487e: 6823 ldr r3, [r4, #0]
8004880: f06f 0220 mvn.w r2, #32
HAL_TIMEx_CommutCallback(htim);
8004884: 4620 mov r0, r4
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
8004886: 611a str r2, [r3, #16]
}
8004888: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
HAL_TIMEx_CommutCallback(htim);
800488c: f000 b886 b.w 800499c <HAL_TIMEx_CommutCallback>
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
8004890: 6823 ldr r3, [r4, #0]
8004892: f06f 0201 mvn.w r2, #1
HAL_TIM_PeriodElapsedCallback(htim);
8004896: 4620 mov r0, r4
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
8004898: 611a str r2, [r3, #16]
HAL_TIM_PeriodElapsedCallback(htim);
800489a: f7ff ff71 bl 8004780 <HAL_TIM_PeriodElapsedCallback>
800489e: e792 b.n 80047c6 <HAL_TIM_IRQHandler+0x32>
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
80048a0: 6823 ldr r3, [r4, #0]
80048a2: f46f 5202 mvn.w r2, #8320 @ 0x2080
HAL_TIMEx_BreakCallback(htim);
80048a6: 4620 mov r0, r4
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
80048a8: 611a str r2, [r3, #16]
HAL_TIMEx_BreakCallback(htim);
80048aa: f000 f879 bl 80049a0 <HAL_TIMEx_BreakCallback>
if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
80048ae: 05e9 lsls r1, r5, #23
80048b0: d58e bpl.n 80047d0 <HAL_TIM_IRQHandler+0x3c>
80048b2: e7dc b.n 800486e <HAL_TIM_IRQHandler+0xda>
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
80048b4: 6823 ldr r3, [r4, #0]
80048b6: f06f 0240 mvn.w r2, #64 @ 0x40
HAL_TIM_TriggerCallback(htim);
80048ba: 4620 mov r0, r4
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
80048bc: 611a str r2, [r3, #16]
HAL_TIM_TriggerCallback(htim);
80048be: f7ff ff67 bl 8004790 <HAL_TIM_TriggerCallback>
80048c2: e789 b.n 80047d8 <HAL_TIM_IRQHandler+0x44>
HAL_TIM_OC_DelayElapsedCallback(htim);
80048c4: f7ff ff5e bl 8004784 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
80048c8: 4620 mov r0, r4
80048ca: f7ff ff5f bl 800478c <HAL_TIM_PWM_PulseFinishedCallback>
80048ce: e7c7 b.n 8004860 <HAL_TIM_IRQHandler+0xcc>
HAL_TIM_IC_CaptureCallback(htim);
80048d0: f7ff ff5a bl 8004788 <HAL_TIM_IC_CaptureCallback>
80048d4: e7b7 b.n 8004846 <HAL_TIM_IRQHandler+0xb2>
HAL_TIM_IC_CaptureCallback(htim);
80048d6: f7ff ff57 bl 8004788 <HAL_TIM_IC_CaptureCallback>
80048da: e7a1 b.n 8004820 <HAL_TIM_IRQHandler+0x8c>
HAL_TIM_OC_DelayElapsedCallback(htim);
80048dc: f7ff ff52 bl 8004784 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
80048e0: 4620 mov r0, r4
80048e2: f7ff ff53 bl 800478c <HAL_TIM_PWM_PulseFinishedCallback>
80048e6: e789 b.n 80047fc <HAL_TIM_IRQHandler+0x68>
080048e8 <HAL_TIMEx_MasterConfigSynchronization>:
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
80048e8: f890 303c ldrb.w r3, [r0, #60] @ 0x3c
80048ec: 2b01 cmp r3, #1
80048ee: d04b beq.n 8004988 <HAL_TIMEx_MasterConfigSynchronization+0xa0>
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
80048f0: 6803 ldr r3, [r0, #0]
80048f2: 4602 mov r2, r0
htim->State = HAL_TIM_STATE_BUSY;
80048f4: 2002 movs r0, #2
{
80048f6: b430 push {r4, r5}
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
80048f8: 4d24 ldr r5, [pc, #144] @ (800498c <HAL_TIMEx_MasterConfigSynchronization+0xa4>)
htim->State = HAL_TIM_STATE_BUSY;
80048fa: f882 003d strb.w r0, [r2, #61] @ 0x3d
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
80048fe: 42ab cmp r3, r5
tmpcr2 = htim->Instance->CR2;
8004900: 6858 ldr r0, [r3, #4]
tmpsmcr = htim->Instance->SMCR;
8004902: 689c ldr r4, [r3, #8]
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
8004904: d029 beq.n 800495a <HAL_TIMEx_MasterConfigSynchronization+0x72>
8004906: f505 6580 add.w r5, r5, #1024 @ 0x400
800490a: 42ab cmp r3, r5
800490c: d025 beq.n 800495a <HAL_TIMEx_MasterConfigSynchronization+0x72>
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
800490e: 4d20 ldr r5, [pc, #128] @ (8004990 <HAL_TIMEx_MasterConfigSynchronization+0xa8>)
tmpcr2 &= ~TIM_CR2_MMS;
8004910: f020 0070 bic.w r0, r0, #112 @ 0x70
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8004914: 42ab cmp r3, r5
8004916: bf18 it ne
8004918: f1b3 4f80 cmpne.w r3, #1073741824 @ 0x40000000
800491c: f505 6580 add.w r5, r5, #1024 @ 0x400
8004920: bf0c ite eq
8004922: f04f 0c01 moveq.w ip, #1
8004926: f04f 0c00 movne.w ip, #0
800492a: 42ab cmp r3, r5
800492c: bf08 it eq
800492e: f04c 0c01 orreq.w ip, ip, #1
8004932: f505 6580 add.w r5, r5, #1024 @ 0x400
8004936: 42ab cmp r3, r5
8004938: bf08 it eq
800493a: f04c 0c01 orreq.w ip, ip, #1
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
800493e: 680d ldr r5, [r1, #0]
8004940: 4328 orrs r0, r5
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8004942: 4d14 ldr r5, [pc, #80] @ (8004994 <HAL_TIMEx_MasterConfigSynchronization+0xac>)
htim->Instance->CR2 = tmpcr2;
8004944: 6058 str r0, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8004946: 42ab cmp r3, r5
8004948: bf14 ite ne
800494a: 4660 movne r0, ip
800494c: f04c 0001 orreq.w r0, ip, #1
8004950: b960 cbnz r0, 800496c <HAL_TIMEx_MasterConfigSynchronization+0x84>
8004952: 4811 ldr r0, [pc, #68] @ (8004998 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
8004954: 4283 cmp r3, r0
8004956: d009 beq.n 800496c <HAL_TIMEx_MasterConfigSynchronization+0x84>
8004958: e00d b.n 8004976 <HAL_TIMEx_MasterConfigSynchronization+0x8e>
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
800495a: 684d ldr r5, [r1, #4]
tmpcr2 &= ~TIM_CR2_MMS2;
800495c: f420 0070 bic.w r0, r0, #15728640 @ 0xf00000
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
8004960: 4328 orrs r0, r5
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
8004962: 680d ldr r5, [r1, #0]
tmpcr2 &= ~TIM_CR2_MMS;
8004964: f020 0070 bic.w r0, r0, #112 @ 0x70
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
8004968: 4328 orrs r0, r5
htim->Instance->CR2 = tmpcr2;
800496a: 6058 str r0, [r3, #4]
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
800496c: 6889 ldr r1, [r1, #8]
tmpsmcr &= ~TIM_SMCR_MSM;
800496e: f024 0480 bic.w r4, r4, #128 @ 0x80
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8004972: 430c orrs r4, r1
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8004974: 609c str r4, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
8004976: 2300 movs r3, #0
htim->State = HAL_TIM_STATE_READY;
8004978: 2101 movs r1, #1
return HAL_OK;
800497a: 4618 mov r0, r3
htim->State = HAL_TIM_STATE_READY;
800497c: f882 103d strb.w r1, [r2, #61] @ 0x3d
__HAL_UNLOCK(htim);
8004980: f882 303c strb.w r3, [r2, #60] @ 0x3c
}
8004984: bc30 pop {r4, r5}
8004986: 4770 bx lr
__HAL_LOCK(htim);
8004988: 2002 movs r0, #2
}
800498a: 4770 bx lr
800498c: 40010000 .word 0x40010000
8004990: 40000400 .word 0x40000400
8004994: 40001800 .word 0x40001800
8004998: 40014000 .word 0x40014000
0800499c <HAL_TIMEx_CommutCallback>:
/**
* @brief Commutation callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
800499c: 4770 bx lr
800499e: bf00 nop
080049a0 <HAL_TIMEx_BreakCallback>:
/**
* @brief Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
80049a0: 4770 bx lr
80049a2: bf00 nop
080049a4 <HAL_TIMEx_Break2Callback>:
/**
* @brief Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
80049a4: 4770 bx lr
80049a6: bf00 nop
080049a8 <HAL_UART_TxCpltCallback>:
/**
* @brief Tx Transfer completed callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
80049a8: 4770 bx lr
80049aa: bf00 nop
080049ac <HAL_UART_ErrorCallback>:
/**
* @brief UART error callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
80049ac: 4770 bx lr
80049ae: bf00 nop
080049b0 <UART_DMAAbortOnError>:
* (To be called at end of DMA Abort procedure following error occurrence).
* @param hdma DMA handle.
* @retval None
*/
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
80049b0: b508 push {r3, lr}
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
80049b2: 6b80 ldr r0, [r0, #56] @ 0x38
huart->RxXferCount = 0U;
80049b4: 2300 movs r3, #0
80049b6: f8a0 305e strh.w r3, [r0, #94] @ 0x5e
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80049ba: f7ff fff7 bl 80049ac <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
80049be: bd08 pop {r3, pc}
080049c0 <HAL_UARTEx_RxEventCallback>:
}
80049c0: 4770 bx lr
80049c2: bf00 nop
080049c4 <HAL_UART_IRQHandler>:
uint32_t isrflags = READ_REG(huart->Instance->ISR);
80049c4: 6803 ldr r3, [r0, #0]
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
80049c6: f640 0c0f movw ip, #2063 @ 0x80f
uint32_t isrflags = READ_REG(huart->Instance->ISR);
80049ca: 69da ldr r2, [r3, #28]
if (errorflags == 0U)
80049cc: ea12 0f0c tst.w r2, ip
{
80049d0: b570 push {r4, r5, r6, lr}
uint32_t cr1its = READ_REG(huart->Instance->CR1);
80049d2: 681d ldr r5, [r3, #0]
{
80049d4: 4604 mov r4, r0
uint32_t cr3its = READ_REG(huart->Instance->CR3);
80049d6: 6899 ldr r1, [r3, #8]
if (errorflags == 0U)
80049d8: d145 bne.n 8004a66 <HAL_UART_IRQHandler+0xa2>
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
80049da: 0696 lsls r6, r2, #26
80049dc: d507 bpl.n 80049ee <HAL_UART_IRQHandler+0x2a>
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
80049de: f005 0c20 and.w ip, r5, #32
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
80049e2: f001 5680 and.w r6, r1, #268435456 @ 0x10000000
80049e6: ea5c 0c06 orrs.w ip, ip, r6
80049ea: f040 812a bne.w 8004c42 <HAL_UART_IRQHandler+0x27e>
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
80049ee: 6ee0 ldr r0, [r4, #108] @ 0x6c
80049f0: 2801 cmp r0, #1
80049f2: f000 80cd beq.w 8004b90 <HAL_UART_IRQHandler+0x1cc>
if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
80049f6: 02d0 lsls r0, r2, #11
80049f8: d41d bmi.n 8004a36 <HAL_UART_IRQHandler+0x72>
if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
80049fa: 0610 lsls r0, r2, #24
80049fc: d506 bpl.n 8004a0c <HAL_UART_IRQHandler+0x48>
|| ((cr3its & USART_CR3_TXFTIE) != 0U)))
80049fe: f401 0100 and.w r1, r1, #8388608 @ 0x800000
&& (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
8004a02: f005 0080 and.w r0, r5, #128 @ 0x80
|| ((cr3its & USART_CR3_TXFTIE) != 0U)))
8004a06: 4308 orrs r0, r1
8004a08: f040 8122 bne.w 8004c50 <HAL_UART_IRQHandler+0x28c>
if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
8004a0c: 0651 lsls r1, r2, #25
8004a0e: d51c bpl.n 8004a4a <HAL_UART_IRQHandler+0x86>
8004a10: 066e lsls r6, r5, #25
8004a12: d51a bpl.n 8004a4a <HAL_UART_IRQHandler+0x86>
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004a14: e853 2f00 ldrex r2, [r3]
* @retval None
*/
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
/* Disable the UART Transmit Complete Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
8004a18: f022 0240 bic.w r2, r2, #64 @ 0x40
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004a1c: e843 2100 strex r1, r2, [r3]
8004a20: 2900 cmp r1, #0
8004a22: d1f7 bne.n 8004a14 <HAL_UART_IRQHandler+0x50>
/* Tx process is ended, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8004a24: 2220 movs r2, #32
/* Cleat TxISR function pointer */
huart->TxISR = NULL;
8004a26: 2300 movs r3, #0
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Tx complete callback*/
huart->TxCpltCallback(huart);
#else
/*Call legacy weak Tx complete callback*/
HAL_UART_TxCpltCallback(huart);
8004a28: 4620 mov r0, r4
huart->gState = HAL_UART_STATE_READY;
8004a2a: f8c4 2088 str.w r2, [r4, #136] @ 0x88
huart->TxISR = NULL;
8004a2e: 67a3 str r3, [r4, #120] @ 0x78
HAL_UART_TxCpltCallback(huart);
8004a30: f7ff ffba bl 80049a8 <HAL_UART_TxCpltCallback>
}
8004a34: bd70 pop {r4, r5, r6, pc}
if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
8004a36: 024e lsls r6, r1, #9
8004a38: d5df bpl.n 80049fa <HAL_UART_IRQHandler+0x36>
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
8004a3a: f44f 1280 mov.w r2, #1048576 @ 0x100000
HAL_UARTEx_WakeupCallback(huart);
8004a3e: 4620 mov r0, r4
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
8004a40: 621a str r2, [r3, #32]
}
8004a42: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
HAL_UARTEx_WakeupCallback(huart);
8004a46: f000 bd07 b.w 8005458 <HAL_UARTEx_WakeupCallback>
if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
8004a4a: 0210 lsls r0, r2, #8
8004a4c: d502 bpl.n 8004a54 <HAL_UART_IRQHandler+0x90>
8004a4e: 0069 lsls r1, r5, #1
8004a50: f100 813d bmi.w 8004cce <HAL_UART_IRQHandler+0x30a>
if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
8004a54: 01d3 lsls r3, r2, #7
8004a56: d5ed bpl.n 8004a34 <HAL_UART_IRQHandler+0x70>
8004a58: 2d00 cmp r5, #0
8004a5a: daeb bge.n 8004a34 <HAL_UART_IRQHandler+0x70>
HAL_UARTEx_RxFifoFullCallback(huart);
8004a5c: 4620 mov r0, r4
}
8004a5e: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
HAL_UARTEx_RxFifoFullCallback(huart);
8004a62: f000 bcfb b.w 800545c <HAL_UARTEx_RxFifoFullCallback>
&& ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
8004a66: 48b9 ldr r0, [pc, #740] @ (8004d4c <HAL_UART_IRQHandler+0x388>)
8004a68: 4008 ands r0, r1
8004a6a: f040 8125 bne.w 8004cb8 <HAL_UART_IRQHandler+0x2f4>
|| ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
8004a6e: 4eb8 ldr r6, [pc, #736] @ (8004d50 <HAL_UART_IRQHandler+0x38c>)
8004a70: 4235 tst r5, r6
8004a72: d0bc beq.n 80049ee <HAL_UART_IRQHandler+0x2a>
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
8004a74: 07d6 lsls r6, r2, #31
8004a76: d51a bpl.n 8004aae <HAL_UART_IRQHandler+0xea>
8004a78: 05ee lsls r6, r5, #23
8004a7a: f140 8103 bpl.w 8004c84 <HAL_UART_IRQHandler+0x2c0>
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
8004a7e: 2601 movs r6, #1
8004a80: 621e str r6, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_PE;
8004a82: f8d4 6090 ldr.w r6, [r4, #144] @ 0x90
8004a86: f046 0601 orr.w r6, r6, #1
8004a8a: f8c4 6090 str.w r6, [r4, #144] @ 0x90
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8004a8e: 0796 lsls r6, r2, #30
8004a90: f140 80fb bpl.w 8004c8a <HAL_UART_IRQHandler+0x2c6>
8004a94: 07ce lsls r6, r1, #31
8004a96: d50a bpl.n 8004aae <HAL_UART_IRQHandler+0xea>
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
8004a98: 2602 movs r6, #2
8004a9a: 621e str r6, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_FE;
8004a9c: f8d4 6090 ldr.w r6, [r4, #144] @ 0x90
8004aa0: f046 0604 orr.w r6, r6, #4
8004aa4: f8c4 6090 str.w r6, [r4, #144] @ 0x90
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8004aa8: 0756 lsls r6, r2, #29
8004aaa: f100 80f4 bmi.w 8004c96 <HAL_UART_IRQHandler+0x2d2>
if (((isrflags & USART_ISR_ORE) != 0U)
8004aae: 0716 lsls r6, r2, #28
8004ab0: d50b bpl.n 8004aca <HAL_UART_IRQHandler+0x106>
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
8004ab2: f005 0620 and.w r6, r5, #32
8004ab6: 4306 orrs r6, r0
8004ab8: d007 beq.n 8004aca <HAL_UART_IRQHandler+0x106>
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
8004aba: 2008 movs r0, #8
8004abc: 6218 str r0, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_ORE;
8004abe: f8d4 0090 ldr.w r0, [r4, #144] @ 0x90
8004ac2: f040 0008 orr.w r0, r0, #8
8004ac6: f8c4 0090 str.w r0, [r4, #144] @ 0x90
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
8004aca: 0510 lsls r0, r2, #20
8004acc: d50a bpl.n 8004ae4 <HAL_UART_IRQHandler+0x120>
8004ace: 016e lsls r6, r5, #5
8004ad0: d508 bpl.n 8004ae4 <HAL_UART_IRQHandler+0x120>
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
8004ad2: f44f 6000 mov.w r0, #2048 @ 0x800
8004ad6: 6218 str r0, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_RTO;
8004ad8: f8d4 0090 ldr.w r0, [r4, #144] @ 0x90
8004adc: f040 0020 orr.w r0, r0, #32
8004ae0: f8c4 0090 str.w r0, [r4, #144] @ 0x90
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
8004ae4: f8d4 0090 ldr.w r0, [r4, #144] @ 0x90
8004ae8: 2800 cmp r0, #0
8004aea: d0a3 beq.n 8004a34 <HAL_UART_IRQHandler+0x70>
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
8004aec: 0690 lsls r0, r2, #26
8004aee: d506 bpl.n 8004afe <HAL_UART_IRQHandler+0x13a>
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
8004af0: f005 0520 and.w r5, r5, #32
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
8004af4: f001 5180 and.w r1, r1, #268435456 @ 0x10000000
8004af8: 430d orrs r5, r1
8004afa: f040 80d5 bne.w 8004ca8 <HAL_UART_IRQHandler+0x2e4>
errorcode = huart->ErrorCode;
8004afe: f8d4 1090 ldr.w r1, [r4, #144] @ 0x90
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
8004b02: 689a ldr r2, [r3, #8]
((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
8004b04: f001 0128 and.w r1, r1, #40 @ 0x28
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
8004b08: f002 0240 and.w r2, r2, #64 @ 0x40
8004b0c: ea52 0501 orrs.w r5, r2, r1
8004b10: f000 80e2 beq.w 8004cd8 <HAL_UART_IRQHandler+0x314>
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004b14: e853 2f00 ldrex r2, [r3]
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
8004b18: f422 7290 bic.w r2, r2, #288 @ 0x120
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004b1c: e843 2100 strex r1, r2, [r3]
8004b20: 2900 cmp r1, #0
8004b22: d1f7 bne.n 8004b14 <HAL_UART_IRQHandler+0x150>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
8004b24: 488b ldr r0, [pc, #556] @ (8004d54 <HAL_UART_IRQHandler+0x390>)
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004b26: f103 0208 add.w r2, r3, #8
8004b2a: e852 2f00 ldrex r2, [r2]
8004b2e: 4002 ands r2, r0
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004b30: f103 0508 add.w r5, r3, #8
8004b34: e845 2100 strex r1, r2, [r5]
8004b38: 2900 cmp r1, #0
8004b3a: d1f4 bne.n 8004b26 <HAL_UART_IRQHandler+0x162>
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8004b3c: 6ee2 ldr r2, [r4, #108] @ 0x6c
8004b3e: 2a01 cmp r2, #1
8004b40: f000 808e beq.w 8004c60 <HAL_UART_IRQHandler+0x29c>
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8004b44: 2200 movs r2, #0
huart->RxState = HAL_UART_STATE_READY;
8004b46: 2120 movs r1, #32
8004b48: f8c4 108c str.w r1, [r4, #140] @ 0x8c
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8004b4c: 66e2 str r2, [r4, #108] @ 0x6c
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8004b4e: 6899 ldr r1, [r3, #8]
huart->RxISR = NULL;
8004b50: 6762 str r2, [r4, #116] @ 0x74
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8004b52: 064a lsls r2, r1, #25
8004b54: f140 80b7 bpl.w 8004cc6 <HAL_UART_IRQHandler+0x302>
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004b58: f103 0208 add.w r2, r3, #8
8004b5c: e852 2f00 ldrex r2, [r2]
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
8004b60: f022 0240 bic.w r2, r2, #64 @ 0x40
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004b64: f103 0008 add.w r0, r3, #8
8004b68: e840 2100 strex r1, r2, [r0]
8004b6c: 2900 cmp r1, #0
8004b6e: d1f3 bne.n 8004b58 <HAL_UART_IRQHandler+0x194>
if (huart->hdmarx != NULL)
8004b70: f8d4 0080 ldr.w r0, [r4, #128] @ 0x80
8004b74: 2800 cmp r0, #0
8004b76: f000 80a6 beq.w 8004cc6 <HAL_UART_IRQHandler+0x302>
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
8004b7a: 4b77 ldr r3, [pc, #476] @ (8004d58 <HAL_UART_IRQHandler+0x394>)
8004b7c: 6503 str r3, [r0, #80] @ 0x50
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
8004b7e: f7fd f8d5 bl 8001d2c <HAL_DMA_Abort_IT>
8004b82: 2800 cmp r0, #0
8004b84: f43f af56 beq.w 8004a34 <HAL_UART_IRQHandler+0x70>
huart->hdmarx->XferAbortCallback(huart->hdmarx);
8004b88: f8d4 0080 ldr.w r0, [r4, #128] @ 0x80
8004b8c: 6d03 ldr r3, [r0, #80] @ 0x50
8004b8e: e05c b.n 8004c4a <HAL_UART_IRQHandler+0x286>
&& ((isrflags & USART_ISR_IDLE) != 0U)
8004b90: 06d6 lsls r6, r2, #27
8004b92: f57f af30 bpl.w 80049f6 <HAL_UART_IRQHandler+0x32>
&& ((cr1its & USART_ISR_IDLE) != 0U))
8004b96: 06e8 lsls r0, r5, #27
8004b98: f57f af2d bpl.w 80049f6 <HAL_UART_IRQHandler+0x32>
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
8004b9c: 2210 movs r2, #16
&& (nb_remaining_rx_data < huart->RxXferSize))
8004b9e: f8b4 505c ldrh.w r5, [r4, #92] @ 0x5c
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
8004ba2: 621a str r2, [r3, #32]
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8004ba4: 689a ldr r2, [r3, #8]
8004ba6: 0656 lsls r6, r2, #25
8004ba8: f140 809c bpl.w 8004ce4 <HAL_UART_IRQHandler+0x320>
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
8004bac: f8d4 0080 ldr.w r0, [r4, #128] @ 0x80
8004bb0: 6801 ldr r1, [r0, #0]
8004bb2: 6849 ldr r1, [r1, #4]
8004bb4: b289 uxth r1, r1
if ((nb_remaining_rx_data > 0U)
8004bb6: 2900 cmp r1, #0
8004bb8: f000 80d0 beq.w 8004d5c <HAL_UART_IRQHandler+0x398>
&& (nb_remaining_rx_data < huart->RxXferSize))
8004bbc: 42a9 cmp r1, r5
8004bbe: f080 80cd bcs.w 8004d5c <HAL_UART_IRQHandler+0x398>
if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
8004bc2: 69c2 ldr r2, [r0, #28]
huart->RxXferCount = nb_remaining_rx_data;
8004bc4: f8a4 105e strh.w r1, [r4, #94] @ 0x5e
if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
8004bc8: f5b2 7f80 cmp.w r2, #256 @ 0x100
8004bcc: d02f beq.n 8004c2e <HAL_UART_IRQHandler+0x26a>
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004bce: e853 2f00 ldrex r2, [r3]
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
8004bd2: f422 7280 bic.w r2, r2, #256 @ 0x100
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004bd6: e843 2100 strex r1, r2, [r3]
8004bda: 2900 cmp r1, #0
8004bdc: d1f7 bne.n 8004bce <HAL_UART_IRQHandler+0x20a>
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004bde: f103 0208 add.w r2, r3, #8
8004be2: e852 2f00 ldrex r2, [r2]
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8004be6: f022 0201 bic.w r2, r2, #1
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004bea: f103 0508 add.w r5, r3, #8
8004bee: e845 2100 strex r1, r2, [r5]
8004bf2: 2900 cmp r1, #0
8004bf4: d1f3 bne.n 8004bde <HAL_UART_IRQHandler+0x21a>
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004bf6: f103 0208 add.w r2, r3, #8
8004bfa: e852 2f00 ldrex r2, [r2]
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
8004bfe: f022 0240 bic.w r2, r2, #64 @ 0x40
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004c02: f103 0508 add.w r5, r3, #8
8004c06: e845 2100 strex r1, r2, [r5]
8004c0a: 2900 cmp r1, #0
8004c0c: d1f3 bne.n 8004bf6 <HAL_UART_IRQHandler+0x232>
huart->RxState = HAL_UART_STATE_READY;
8004c0e: 2220 movs r2, #32
8004c10: f8c4 208c str.w r2, [r4, #140] @ 0x8c
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8004c14: 66e1 str r1, [r4, #108] @ 0x6c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004c16: e853 2f00 ldrex r2, [r3]
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8004c1a: f022 0210 bic.w r2, r2, #16
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004c1e: e843 2100 strex r1, r2, [r3]
8004c22: 2900 cmp r1, #0
8004c24: d1f7 bne.n 8004c16 <HAL_UART_IRQHandler+0x252>
(void)HAL_DMA_Abort(huart->hdmarx);
8004c26: f7fc fecb bl 80019c0 <HAL_DMA_Abort>
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
8004c2a: f8b4 505c ldrh.w r5, [r4, #92] @ 0x5c
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
8004c2e: 2302 movs r3, #2
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
8004c30: 4620 mov r0, r4
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
8004c32: 6723 str r3, [r4, #112] @ 0x70
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
8004c34: f8b4 105e ldrh.w r1, [r4, #94] @ 0x5e
8004c38: 1a69 subs r1, r5, r1
8004c3a: b289 uxth r1, r1
8004c3c: f7ff fec0 bl 80049c0 <HAL_UARTEx_RxEventCallback>
}
8004c40: bd70 pop {r4, r5, r6, pc}
if (huart->RxISR != NULL)
8004c42: 6f43 ldr r3, [r0, #116] @ 0x74
8004c44: 2b00 cmp r3, #0
8004c46: f43f aef5 beq.w 8004a34 <HAL_UART_IRQHandler+0x70>
}
8004c4a: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
huart->hdmarx->XferAbortCallback(huart->hdmarx);
8004c4e: 4718 bx r3
if (huart->TxISR != NULL)
8004c50: 6fa3 ldr r3, [r4, #120] @ 0x78
8004c52: 2b00 cmp r3, #0
8004c54: f43f aeee beq.w 8004a34 <HAL_UART_IRQHandler+0x70>
huart->TxISR(huart);
8004c58: 4620 mov r0, r4
}
8004c5a: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
huart->TxISR(huart);
8004c5e: 4718 bx r3
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004c60: e853 2f00 ldrex r2, [r3]
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8004c64: f022 0210 bic.w r2, r2, #16
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004c68: e843 2100 strex r1, r2, [r3]
8004c6c: 2900 cmp r1, #0
8004c6e: f43f af69 beq.w 8004b44 <HAL_UART_IRQHandler+0x180>
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004c72: e853 2f00 ldrex r2, [r3]
8004c76: f022 0210 bic.w r2, r2, #16
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004c7a: e843 2100 strex r1, r2, [r3]
8004c7e: 2900 cmp r1, #0
8004c80: d1ee bne.n 8004c60 <HAL_UART_IRQHandler+0x29c>
8004c82: e75f b.n 8004b44 <HAL_UART_IRQHandler+0x180>
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8004c84: 0796 lsls r6, r2, #30
8004c86: f53f af12 bmi.w 8004aae <HAL_UART_IRQHandler+0xea>
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8004c8a: 0756 lsls r6, r2, #29
8004c8c: f57f af0f bpl.w 8004aae <HAL_UART_IRQHandler+0xea>
8004c90: 07ce lsls r6, r1, #31
8004c92: f57f af0c bpl.w 8004aae <HAL_UART_IRQHandler+0xea>
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
8004c96: 2604 movs r6, #4
8004c98: 621e str r6, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_NE;
8004c9a: f8d4 6090 ldr.w r6, [r4, #144] @ 0x90
8004c9e: f046 0602 orr.w r6, r6, #2
8004ca2: f8c4 6090 str.w r6, [r4, #144] @ 0x90
8004ca6: e702 b.n 8004aae <HAL_UART_IRQHandler+0xea>
if (huart->RxISR != NULL)
8004ca8: 6f62 ldr r2, [r4, #116] @ 0x74
8004caa: 2a00 cmp r2, #0
8004cac: f43f af27 beq.w 8004afe <HAL_UART_IRQHandler+0x13a>
huart->RxISR(huart);
8004cb0: 4620 mov r0, r4
8004cb2: 4790 blx r2
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
8004cb4: 6823 ldr r3, [r4, #0]
8004cb6: e722 b.n 8004afe <HAL_UART_IRQHandler+0x13a>
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
8004cb8: 07d6 lsls r6, r2, #31
8004cba: f57f aee8 bpl.w 8004a8e <HAL_UART_IRQHandler+0xca>
8004cbe: 05ee lsls r6, r5, #23
8004cc0: f57f aee5 bpl.w 8004a8e <HAL_UART_IRQHandler+0xca>
8004cc4: e6db b.n 8004a7e <HAL_UART_IRQHandler+0xba>
HAL_UART_ErrorCallback(huart);
8004cc6: 4620 mov r0, r4
8004cc8: f7ff fe70 bl 80049ac <HAL_UART_ErrorCallback>
}
8004ccc: bd70 pop {r4, r5, r6, pc}
HAL_UARTEx_TxFifoEmptyCallback(huart);
8004cce: 4620 mov r0, r4
}
8004cd0: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
HAL_UARTEx_TxFifoEmptyCallback(huart);
8004cd4: f000 bbc4 b.w 8005460 <HAL_UARTEx_TxFifoEmptyCallback>
HAL_UART_ErrorCallback(huart);
8004cd8: 4620 mov r0, r4
8004cda: f7ff fe67 bl 80049ac <HAL_UART_ErrorCallback>
huart->ErrorCode = HAL_UART_ERROR_NONE;
8004cde: f8c4 5090 str.w r5, [r4, #144] @ 0x90
}
8004ce2: bd70 pop {r4, r5, r6, pc}
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
8004ce4: f8b4 105e ldrh.w r1, [r4, #94] @ 0x5e
if ((huart->RxXferCount > 0U)
8004ce8: f8b4 205e ldrh.w r2, [r4, #94] @ 0x5e
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
8004cec: 1a6d subs r5, r5, r1
if ((huart->RxXferCount > 0U)
8004cee: b292 uxth r2, r2
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
8004cf0: b2a9 uxth r1, r5
&& (nb_rx_data > 0U))
8004cf2: 2900 cmp r1, #0
8004cf4: f43f ae9e beq.w 8004a34 <HAL_UART_IRQHandler+0x70>
8004cf8: 2a00 cmp r2, #0
8004cfa: f43f ae9b beq.w 8004a34 <HAL_UART_IRQHandler+0x70>
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004cfe: e853 2f00 ldrex r2, [r3]
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
8004d02: f422 7290 bic.w r2, r2, #288 @ 0x120
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004d06: e843 2000 strex r0, r2, [r3]
8004d0a: 2800 cmp r0, #0
8004d0c: d1f7 bne.n 8004cfe <HAL_UART_IRQHandler+0x33a>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
8004d0e: 4d11 ldr r5, [pc, #68] @ (8004d54 <HAL_UART_IRQHandler+0x390>)
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004d10: f103 0208 add.w r2, r3, #8
8004d14: e852 2f00 ldrex r2, [r2]
8004d18: 402a ands r2, r5
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004d1a: f103 0608 add.w r6, r3, #8
8004d1e: e846 2000 strex r0, r2, [r6]
8004d22: 2800 cmp r0, #0
8004d24: d1f4 bne.n 8004d10 <HAL_UART_IRQHandler+0x34c>
huart->RxState = HAL_UART_STATE_READY;
8004d26: 2220 movs r2, #32
huart->RxISR = NULL;
8004d28: 6760 str r0, [r4, #116] @ 0x74
huart->RxState = HAL_UART_STATE_READY;
8004d2a: f8c4 208c str.w r2, [r4, #140] @ 0x8c
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8004d2e: 66e0 str r0, [r4, #108] @ 0x6c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004d30: e853 2f00 ldrex r2, [r3]
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8004d34: f022 0210 bic.w r2, r2, #16
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004d38: e843 2000 strex r0, r2, [r3]
8004d3c: 2800 cmp r0, #0
8004d3e: d1f7 bne.n 8004d30 <HAL_UART_IRQHandler+0x36c>
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
8004d40: 2302 movs r3, #2
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
8004d42: 4620 mov r0, r4
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
8004d44: 6723 str r3, [r4, #112] @ 0x70
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
8004d46: f7ff fe3b bl 80049c0 <HAL_UARTEx_RxEventCallback>
}
8004d4a: bd70 pop {r4, r5, r6, pc}
8004d4c: 10000001 .word 0x10000001
8004d50: 04000120 .word 0x04000120
8004d54: effffffe .word 0xeffffffe
8004d58: 080049b1 .word 0x080049b1
if (nb_remaining_rx_data == huart->RxXferSize)
8004d5c: 42a9 cmp r1, r5
8004d5e: f47f ae69 bne.w 8004a34 <HAL_UART_IRQHandler+0x70>
if (huart->hdmarx->Init.Mode == DMA_CIRCULAR)
8004d62: 69c3 ldr r3, [r0, #28]
8004d64: f5b3 7f80 cmp.w r3, #256 @ 0x100
8004d68: d0ea beq.n 8004d40 <HAL_UART_IRQHandler+0x37c>
}
8004d6a: bd70 pop {r4, r5, r6, pc}
08004d6c <UART_SetConfig>:
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
8004d6c: 6901 ldr r1, [r0, #16]
8004d6e: 6882 ldr r2, [r0, #8]
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
8004d70: 6803 ldr r3, [r0, #0]
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
8004d72: 430a orrs r2, r1
{
8004d74: b570 push {r4, r5, r6, lr}
8004d76: 4604 mov r4, r0
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
8004d78: 681d ldr r5, [r3, #0]
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
8004d7a: 69c0 ldr r0, [r0, #28]
{
8004d7c: b086 sub sp, #24
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
8004d7e: 6961 ldr r1, [r4, #20]
8004d80: 430a orrs r2, r1
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
8004d82: 49a0 ldr r1, [pc, #640] @ (8005004 <UART_SetConfig+0x298>)
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
8004d84: 4302 orrs r2, r0
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
8004d86: 4029 ands r1, r5
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
8004d88: 6a65 ldr r5, [r4, #36] @ 0x24
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
8004d8a: 430a orrs r2, r1
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8004d8c: 68e1 ldr r1, [r4, #12]
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
8004d8e: 601a str r2, [r3, #0]
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8004d90: 685a ldr r2, [r3, #4]
8004d92: f422 5240 bic.w r2, r2, #12288 @ 0x3000
8004d96: 430a orrs r2, r1
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
8004d98: 69a1 ldr r1, [r4, #24]
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8004d9a: 605a str r2, [r3, #4]
if (!(UART_INSTANCE_LOWPOWER(huart)))
8004d9c: 4a9a ldr r2, [pc, #616] @ (8005008 <UART_SetConfig+0x29c>)
8004d9e: 4293 cmp r3, r2
8004da0: f000 8119 beq.w 8004fd6 <UART_SetConfig+0x26a>
tmpreg |= huart->Init.OneBitSampling;
8004da4: 6a22 ldr r2, [r4, #32]
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
8004da6: 689e ldr r6, [r3, #8]
tmpreg |= huart->Init.OneBitSampling;
8004da8: 4311 orrs r1, r2
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
8004daa: 4a98 ldr r2, [pc, #608] @ (800500c <UART_SetConfig+0x2a0>)
8004dac: 4032 ands r2, r6
8004dae: 4311 orrs r1, r2
8004db0: 6099 str r1, [r3, #8]
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
8004db2: 6ada ldr r2, [r3, #44] @ 0x2c
8004db4: f022 020f bic.w r2, r2, #15
8004db8: 432a orrs r2, r5
8004dba: 62da str r2, [r3, #44] @ 0x2c
UART_GETCLOCKSOURCE(huart, clocksource);
8004dbc: 4a94 ldr r2, [pc, #592] @ (8005010 <UART_SetConfig+0x2a4>)
8004dbe: 4293 cmp r3, r2
8004dc0: d028 beq.n 8004e14 <UART_SetConfig+0xa8>
8004dc2: 4a94 ldr r2, [pc, #592] @ (8005014 <UART_SetConfig+0x2a8>)
8004dc4: 4293 cmp r3, r2
8004dc6: d01a beq.n 8004dfe <UART_SetConfig+0x92>
8004dc8: 4a93 ldr r2, [pc, #588] @ (8005018 <UART_SetConfig+0x2ac>)
8004dca: 4293 cmp r3, r2
8004dcc: d017 beq.n 8004dfe <UART_SetConfig+0x92>
8004dce: 4a93 ldr r2, [pc, #588] @ (800501c <UART_SetConfig+0x2b0>)
8004dd0: 4293 cmp r3, r2
8004dd2: d014 beq.n 8004dfe <UART_SetConfig+0x92>
8004dd4: 4a92 ldr r2, [pc, #584] @ (8005020 <UART_SetConfig+0x2b4>)
8004dd6: 4293 cmp r3, r2
8004dd8: d011 beq.n 8004dfe <UART_SetConfig+0x92>
8004dda: 4a92 ldr r2, [pc, #584] @ (8005024 <UART_SetConfig+0x2b8>)
8004ddc: 4293 cmp r3, r2
8004dde: d019 beq.n 8004e14 <UART_SetConfig+0xa8>
8004de0: 4a91 ldr r2, [pc, #580] @ (8005028 <UART_SetConfig+0x2bc>)
8004de2: 4293 cmp r3, r2
8004de4: d00b beq.n 8004dfe <UART_SetConfig+0x92>
8004de6: 4a91 ldr r2, [pc, #580] @ (800502c <UART_SetConfig+0x2c0>)
8004de8: 4293 cmp r3, r2
8004dea: d008 beq.n 8004dfe <UART_SetConfig+0x92>
ret = HAL_ERROR;
8004dec: 2001 movs r0, #1
huart->RxISR = NULL;
8004dee: 2300 movs r3, #0
huart->NbRxDataToProcess = 1;
8004df0: f04f 1201 mov.w r2, #65537 @ 0x10001
huart->RxISR = NULL;
8004df4: 6763 str r3, [r4, #116] @ 0x74
huart->NbRxDataToProcess = 1;
8004df6: 66a2 str r2, [r4, #104] @ 0x68
huart->TxISR = NULL;
8004df8: 67a3 str r3, [r4, #120] @ 0x78
}
8004dfa: b006 add sp, #24
8004dfc: bd70 pop {r4, r5, r6, pc}
UART_GETCLOCKSOURCE(huart, clocksource);
8004dfe: 4b8c ldr r3, [pc, #560] @ (8005030 <UART_SetConfig+0x2c4>)
8004e00: 6d5b ldr r3, [r3, #84] @ 0x54
8004e02: f003 0307 and.w r3, r3, #7
8004e06: 2b05 cmp r3, #5
8004e08: d8f0 bhi.n 8004dec <UART_SetConfig+0x80>
8004e0a: e8df f003 tbb [pc, r3]
8004e0e: 7e9e .short 0x7e9e
8004e10: 785f9189 .word 0x785f9189
8004e14: 4b86 ldr r3, [pc, #536] @ (8005030 <UART_SetConfig+0x2c4>)
8004e16: 6d5b ldr r3, [r3, #84] @ 0x54
8004e18: f003 0338 and.w r3, r3, #56 @ 0x38
8004e1c: 2b28 cmp r3, #40 @ 0x28
8004e1e: d8e5 bhi.n 8004dec <UART_SetConfig+0x80>
8004e20: a201 add r2, pc, #4 @ (adr r2, 8004e28 <UART_SetConfig+0xbc>)
8004e22: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8004e26: bf00 nop
8004e28: 08004fa5 .word 0x08004fa5
8004e2c: 08004ded .word 0x08004ded
8004e30: 08004ded .word 0x08004ded
8004e34: 08004ded .word 0x08004ded
8004e38: 08004ded .word 0x08004ded
8004e3c: 08004ded .word 0x08004ded
8004e40: 08004ded .word 0x08004ded
8004e44: 08004ded .word 0x08004ded
8004e48: 08004f0b .word 0x08004f0b
8004e4c: 08004ded .word 0x08004ded
8004e50: 08004ded .word 0x08004ded
8004e54: 08004ded .word 0x08004ded
8004e58: 08004ded .word 0x08004ded
8004e5c: 08004ded .word 0x08004ded
8004e60: 08004ded .word 0x08004ded
8004e64: 08004ded .word 0x08004ded
8004e68: 08004f21 .word 0x08004f21
8004e6c: 08004ded .word 0x08004ded
8004e70: 08004ded .word 0x08004ded
8004e74: 08004ded .word 0x08004ded
8004e78: 08004ded .word 0x08004ded
8004e7c: 08004ded .word 0x08004ded
8004e80: 08004ded .word 0x08004ded
8004e84: 08004ded .word 0x08004ded
8004e88: 08004f31 .word 0x08004f31
8004e8c: 08004ded .word 0x08004ded
8004e90: 08004ded .word 0x08004ded
8004e94: 08004ded .word 0x08004ded
8004e98: 08004ded .word 0x08004ded
8004e9c: 08004ded .word 0x08004ded
8004ea0: 08004ded .word 0x08004ded
8004ea4: 08004ded .word 0x08004ded
8004ea8: 08004ecd .word 0x08004ecd
8004eac: 08004ded .word 0x08004ded
8004eb0: 08004ded .word 0x08004ded
8004eb4: 08004ded .word 0x08004ded
8004eb8: 08004ded .word 0x08004ded
8004ebc: 08004ded .word 0x08004ded
8004ec0: 08004ded .word 0x08004ded
8004ec4: 08004ded .word 0x08004ded
8004ec8: 08004eff .word 0x08004eff
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8004ecc: f5b0 4f00 cmp.w r0, #32768 @ 0x8000
pclk = (uint32_t) CSI_VALUE;
8004ed0: 4858 ldr r0, [pc, #352] @ (8005034 <UART_SetConfig+0x2c8>)
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8004ed2: d047 beq.n 8004f64 <UART_SetConfig+0x1f8>
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
8004ed4: 4a58 ldr r2, [pc, #352] @ (8005038 <UART_SetConfig+0x2cc>)
8004ed6: 6863 ldr r3, [r4, #4]
8004ed8: f832 1015 ldrh.w r1, [r2, r5, lsl #1]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8004edc: f64f 72ef movw r2, #65519 @ 0xffef
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
8004ee0: fbb0 f0f1 udiv r0, r0, r1
8004ee4: eb00 0053 add.w r0, r0, r3, lsr #1
8004ee8: fbb0 f0f3 udiv r0, r0, r3
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8004eec: f1a0 0310 sub.w r3, r0, #16
8004ef0: 4293 cmp r3, r2
8004ef2: f63f af7b bhi.w 8004dec <UART_SetConfig+0x80>
huart->Instance->BRR = usartdiv;
8004ef6: 6823 ldr r3, [r4, #0]
8004ef8: 60d8 str r0, [r3, #12]
pclk = (uint32_t) HSI_VALUE;
8004efa: 2000 movs r0, #0
8004efc: e777 b.n 8004dee <UART_SetConfig+0x82>
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8004efe: f5b0 4f00 cmp.w r0, #32768 @ 0x8000
8004f02: d02f beq.n 8004f64 <UART_SetConfig+0x1f8>
pclk = (uint32_t) LSE_VALUE;
8004f04: f44f 4000 mov.w r0, #32768 @ 0x8000
8004f08: e7e4 b.n 8004ed4 <UART_SetConfig+0x168>
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8004f0a: f5b0 4f00 cmp.w r0, #32768 @ 0x8000
8004f0e: d022 beq.n 8004f56 <UART_SetConfig+0x1ea>
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
8004f10: 4668 mov r0, sp
8004f12: f7ff f821 bl 8003f58 <HAL_RCCEx_GetPLL2ClockFreq>
pclk = pll2_clocks.PLL2_Q_Frequency;
8004f16: 9801 ldr r0, [sp, #4]
if (pclk != 0U)
8004f18: 2800 cmp r0, #0
8004f1a: d0ee beq.n 8004efa <UART_SetConfig+0x18e>
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
8004f1c: 6a65 ldr r5, [r4, #36] @ 0x24
8004f1e: e7d9 b.n 8004ed4 <UART_SetConfig+0x168>
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8004f20: f5b0 4f00 cmp.w r0, #32768 @ 0x8000
8004f24: d04f beq.n 8004fc6 <UART_SetConfig+0x25a>
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
8004f26: a803 add r0, sp, #12
8004f28: f7ff f8b0 bl 800408c <HAL_RCCEx_GetPLL3ClockFreq>
pclk = pll3_clocks.PLL3_Q_Frequency;
8004f2c: 9804 ldr r0, [sp, #16]
break;
8004f2e: e7f3 b.n 8004f18 <UART_SetConfig+0x1ac>
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8004f30: f5b0 4f00 cmp.w r0, #32768 @ 0x8000
8004f34: d03c beq.n 8004fb0 <UART_SetConfig+0x244>
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
8004f36: 4b3e ldr r3, [pc, #248] @ (8005030 <UART_SetConfig+0x2c4>)
8004f38: 681a ldr r2, [r3, #0]
8004f3a: 0691 lsls r1, r2, #26
8004f3c: d52d bpl.n 8004f9a <UART_SetConfig+0x22e>
pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
8004f3e: 681b ldr r3, [r3, #0]
8004f40: 483e ldr r0, [pc, #248] @ (800503c <UART_SetConfig+0x2d0>)
8004f42: f3c3 03c1 ubfx r3, r3, #3, #2
8004f46: 40d8 lsrs r0, r3
if (pclk != 0U)
8004f48: e7c4 b.n 8004ed4 <UART_SetConfig+0x168>
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8004f4a: f5b0 4f00 cmp.w r0, #32768 @ 0x8000
8004f4e: d026 beq.n 8004f9e <UART_SetConfig+0x232>
pclk = HAL_RCC_GetPCLK1Freq();
8004f50: f7fd ff3c bl 8002dcc <HAL_RCC_GetPCLK1Freq>
break;
8004f54: e7e0 b.n 8004f18 <UART_SetConfig+0x1ac>
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
8004f56: 4668 mov r0, sp
8004f58: f7fe fffe bl 8003f58 <HAL_RCCEx_GetPLL2ClockFreq>
pclk = pll2_clocks.PLL2_Q_Frequency;
8004f5c: 9801 ldr r0, [sp, #4]
if (pclk != 0U)
8004f5e: 2800 cmp r0, #0
8004f60: d0cb beq.n 8004efa <UART_SetConfig+0x18e>
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
8004f62: 6a65 ldr r5, [r4, #36] @ 0x24
8004f64: 4b34 ldr r3, [pc, #208] @ (8005038 <UART_SetConfig+0x2cc>)
8004f66: 6862 ldr r2, [r4, #4]
8004f68: f833 1015 ldrh.w r1, [r3, r5, lsl #1]
8004f6c: 0853 lsrs r3, r2, #1
8004f6e: fbb0 f0f1 udiv r0, r0, r1
8004f72: eb03 0340 add.w r3, r3, r0, lsl #1
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8004f76: f64f 71ef movw r1, #65519 @ 0xffef
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
8004f7a: fbb3 f3f2 udiv r3, r3, r2
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8004f7e: f1a3 0210 sub.w r2, r3, #16
8004f82: 428a cmp r2, r1
8004f84: f63f af32 bhi.w 8004dec <UART_SetConfig+0x80>
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
8004f88: f023 020f bic.w r2, r3, #15
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
8004f8c: f3c3 0342 ubfx r3, r3, #1, #3
huart->Instance->BRR = brrtemp;
8004f90: 6821 ldr r1, [r4, #0]
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
8004f92: b292 uxth r2, r2
huart->Instance->BRR = brrtemp;
8004f94: 4313 orrs r3, r2
8004f96: 60cb str r3, [r1, #12]
8004f98: e7af b.n 8004efa <UART_SetConfig+0x18e>
pclk = (uint32_t) HSI_VALUE;
8004f9a: 4828 ldr r0, [pc, #160] @ (800503c <UART_SetConfig+0x2d0>)
8004f9c: e79a b.n 8004ed4 <UART_SetConfig+0x168>
pclk = HAL_RCC_GetPCLK1Freq();
8004f9e: f7fd ff15 bl 8002dcc <HAL_RCC_GetPCLK1Freq>
break;
8004fa2: e7dc b.n 8004f5e <UART_SetConfig+0x1f2>
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8004fa4: f5b0 4f00 cmp.w r0, #32768 @ 0x8000
8004fa8: d012 beq.n 8004fd0 <UART_SetConfig+0x264>
pclk = HAL_RCC_GetPCLK2Freq();
8004faa: f7fd ff57 bl 8002e5c <HAL_RCC_GetPCLK2Freq>
break;
8004fae: e7b3 b.n 8004f18 <UART_SetConfig+0x1ac>
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
8004fb0: 4b1f ldr r3, [pc, #124] @ (8005030 <UART_SetConfig+0x2c4>)
8004fb2: 681a ldr r2, [r3, #0]
8004fb4: 0690 lsls r0, r2, #26
8004fb6: f140 808b bpl.w 80050d0 <UART_SetConfig+0x364>
pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
8004fba: 681b ldr r3, [r3, #0]
8004fbc: 481f ldr r0, [pc, #124] @ (800503c <UART_SetConfig+0x2d0>)
8004fbe: f3c3 03c1 ubfx r3, r3, #3, #2
8004fc2: 40d8 lsrs r0, r3
if (pclk != 0U)
8004fc4: e7ce b.n 8004f64 <UART_SetConfig+0x1f8>
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
8004fc6: a803 add r0, sp, #12
8004fc8: f7ff f860 bl 800408c <HAL_RCCEx_GetPLL3ClockFreq>
pclk = pll3_clocks.PLL3_Q_Frequency;
8004fcc: 9804 ldr r0, [sp, #16]
break;
8004fce: e7c6 b.n 8004f5e <UART_SetConfig+0x1f2>
pclk = HAL_RCC_GetPCLK2Freq();
8004fd0: f7fd ff44 bl 8002e5c <HAL_RCC_GetPCLK2Freq>
break;
8004fd4: e7c3 b.n 8004f5e <UART_SetConfig+0x1f2>
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
8004fd6: 6898 ldr r0, [r3, #8]
8004fd8: 4a0c ldr r2, [pc, #48] @ (800500c <UART_SetConfig+0x2a0>)
8004fda: 4002 ands r2, r0
8004fdc: 430a orrs r2, r1
UART_GETCLOCKSOURCE(huart, clocksource);
8004fde: 4914 ldr r1, [pc, #80] @ (8005030 <UART_SetConfig+0x2c4>)
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
8004fe0: 609a str r2, [r3, #8]
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
8004fe2: 6ada ldr r2, [r3, #44] @ 0x2c
8004fe4: f022 020f bic.w r2, r2, #15
8004fe8: 432a orrs r2, r5
8004fea: 62da str r2, [r3, #44] @ 0x2c
UART_GETCLOCKSOURCE(huart, clocksource);
8004fec: 6d8b ldr r3, [r1, #88] @ 0x58
8004fee: f003 0307 and.w r3, r3, #7
8004ff2: 2b05 cmp r3, #5
8004ff4: f63f aefa bhi.w 8004dec <UART_SetConfig+0x80>
8004ff8: e8df f003 tbb [pc, r3]
8004ffc: 224e575c .word 0x224e575c
8005000: 5f62 .short 0x5f62
8005002: bf00 nop
8005004: cfff69f3 .word 0xcfff69f3
8005008: 58000c00 .word 0x58000c00
800500c: 11fff4ff .word 0x11fff4ff
8005010: 40011000 .word 0x40011000
8005014: 40004400 .word 0x40004400
8005018: 40004800 .word 0x40004800
800501c: 40004c00 .word 0x40004c00
8005020: 40005000 .word 0x40005000
8005024: 40011400 .word 0x40011400
8005028: 40007800 .word 0x40007800
800502c: 40007c00 .word 0x40007c00
8005030: 58024400 .word 0x58024400
8005034: 003d0900 .word 0x003d0900
8005038: 08005628 .word 0x08005628
800503c: 03d09000 .word 0x03d09000
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
8005040: 4b24 ldr r3, [pc, #144] @ (80050d4 <UART_SetConfig+0x368>)
8005042: 681a ldr r2, [r3, #0]
8005044: 0692 lsls r2, r2, #26
8005046: d43d bmi.n 80050c4 <UART_SetConfig+0x358>
pclk = (uint32_t) HSI_VALUE;
8005048: 4823 ldr r0, [pc, #140] @ (80050d8 <UART_SetConfig+0x36c>)
lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
800504a: 4b24 ldr r3, [pc, #144] @ (80050dc <UART_SetConfig+0x370>)
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
800504c: 6866 ldr r6, [r4, #4]
lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
800504e: f833 2015 ldrh.w r2, [r3, r5, lsl #1]
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
8005052: eb06 0146 add.w r1, r6, r6, lsl #1
lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
8005056: fbb0 f3f2 udiv r3, r0, r2
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
800505a: 4299 cmp r1, r3
800505c: f63f aec6 bhi.w 8004dec <UART_SetConfig+0x80>
8005060: ebb3 3f06 cmp.w r3, r6, lsl #12
8005064: f63f aec2 bhi.w 8004dec <UART_SetConfig+0x80>
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
8005068: 2300 movs r3, #0
800506a: 4619 mov r1, r3
800506c: f7fb f934 bl 80002d8 <__aeabi_uldivmod>
8005070: 4632 mov r2, r6
8005072: 0209 lsls r1, r1, #8
8005074: 0203 lsls r3, r0, #8
8005076: ea41 6110 orr.w r1, r1, r0, lsr #24
800507a: 0870 lsrs r0, r6, #1
800507c: 1818 adds r0, r3, r0
800507e: f04f 0300 mov.w r3, #0
8005082: f141 0100 adc.w r1, r1, #0
8005086: f7fb f927 bl 80002d8 <__aeabi_uldivmod>
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
800508a: 4b15 ldr r3, [pc, #84] @ (80050e0 <UART_SetConfig+0x374>)
800508c: f5a0 7240 sub.w r2, r0, #768 @ 0x300
8005090: 429a cmp r2, r3
8005092: f63f aeab bhi.w 8004dec <UART_SetConfig+0x80>
8005096: e72e b.n 8004ef6 <UART_SetConfig+0x18a>
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
8005098: a803 add r0, sp, #12
800509a: f7fe fff7 bl 800408c <HAL_RCCEx_GetPLL3ClockFreq>
pclk = pll3_clocks.PLL3_Q_Frequency;
800509e: 9804 ldr r0, [sp, #16]
if (pclk != 0U)
80050a0: 2800 cmp r0, #0
80050a2: f43f af2a beq.w 8004efa <UART_SetConfig+0x18e>
lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
80050a6: 6a65 ldr r5, [r4, #36] @ 0x24
80050a8: e7cf b.n 800504a <UART_SetConfig+0x2de>
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
80050aa: 4668 mov r0, sp
80050ac: f7fe ff54 bl 8003f58 <HAL_RCCEx_GetPLL2ClockFreq>
pclk = pll2_clocks.PLL2_Q_Frequency;
80050b0: 9801 ldr r0, [sp, #4]
break;
80050b2: e7f5 b.n 80050a0 <UART_SetConfig+0x334>
pclk = HAL_RCCEx_GetD3PCLK1Freq();
80050b4: f7fe ff3e bl 8003f34 <HAL_RCCEx_GetD3PCLK1Freq>
break;
80050b8: e7f2 b.n 80050a0 <UART_SetConfig+0x334>
pclk = (uint32_t) LSE_VALUE;
80050ba: f44f 4000 mov.w r0, #32768 @ 0x8000
80050be: e7c4 b.n 800504a <UART_SetConfig+0x2de>
pclk = (uint32_t) CSI_VALUE;
80050c0: 4808 ldr r0, [pc, #32] @ (80050e4 <UART_SetConfig+0x378>)
80050c2: e7c2 b.n 800504a <UART_SetConfig+0x2de>
pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
80050c4: 681b ldr r3, [r3, #0]
80050c6: 4804 ldr r0, [pc, #16] @ (80050d8 <UART_SetConfig+0x36c>)
80050c8: f3c3 03c1 ubfx r3, r3, #3, #2
80050cc: 40d8 lsrs r0, r3
if (pclk != 0U)
80050ce: e7bc b.n 800504a <UART_SetConfig+0x2de>
pclk = (uint32_t) HSI_VALUE;
80050d0: 4801 ldr r0, [pc, #4] @ (80050d8 <UART_SetConfig+0x36c>)
80050d2: e747 b.n 8004f64 <UART_SetConfig+0x1f8>
80050d4: 58024400 .word 0x58024400
80050d8: 03d09000 .word 0x03d09000
80050dc: 08005628 .word 0x08005628
80050e0: 000ffcff .word 0x000ffcff
80050e4: 003d0900 .word 0x003d0900
080050e8 <UART_AdvFeatureConfig>:
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
80050e8: 6a83 ldr r3, [r0, #40] @ 0x28
80050ea: 071a lsls r2, r3, #28
{
80050ec: b410 push {r4}
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
80050ee: d506 bpl.n 80050fe <UART_AdvFeatureConfig+0x16>
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
80050f0: 6801 ldr r1, [r0, #0]
80050f2: 6b84 ldr r4, [r0, #56] @ 0x38
80050f4: 684a ldr r2, [r1, #4]
80050f6: f422 4200 bic.w r2, r2, #32768 @ 0x8000
80050fa: 4322 orrs r2, r4
80050fc: 604a str r2, [r1, #4]
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
80050fe: 07dc lsls r4, r3, #31
8005100: d506 bpl.n 8005110 <UART_AdvFeatureConfig+0x28>
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
8005102: 6801 ldr r1, [r0, #0]
8005104: 6ac4 ldr r4, [r0, #44] @ 0x2c
8005106: 684a ldr r2, [r1, #4]
8005108: f422 3200 bic.w r2, r2, #131072 @ 0x20000
800510c: 4322 orrs r2, r4
800510e: 604a str r2, [r1, #4]
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
8005110: 0799 lsls r1, r3, #30
8005112: d506 bpl.n 8005122 <UART_AdvFeatureConfig+0x3a>
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
8005114: 6801 ldr r1, [r0, #0]
8005116: 6b04 ldr r4, [r0, #48] @ 0x30
8005118: 684a ldr r2, [r1, #4]
800511a: f422 3280 bic.w r2, r2, #65536 @ 0x10000
800511e: 4322 orrs r2, r4
8005120: 604a str r2, [r1, #4]
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
8005122: 075a lsls r2, r3, #29
8005124: d506 bpl.n 8005134 <UART_AdvFeatureConfig+0x4c>
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
8005126: 6801 ldr r1, [r0, #0]
8005128: 6b44 ldr r4, [r0, #52] @ 0x34
800512a: 684a ldr r2, [r1, #4]
800512c: f422 2280 bic.w r2, r2, #262144 @ 0x40000
8005130: 4322 orrs r2, r4
8005132: 604a str r2, [r1, #4]
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
8005134: 06dc lsls r4, r3, #27
8005136: d506 bpl.n 8005146 <UART_AdvFeatureConfig+0x5e>
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
8005138: 6801 ldr r1, [r0, #0]
800513a: 6bc4 ldr r4, [r0, #60] @ 0x3c
800513c: 688a ldr r2, [r1, #8]
800513e: f422 5280 bic.w r2, r2, #4096 @ 0x1000
8005142: 4322 orrs r2, r4
8005144: 608a str r2, [r1, #8]
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
8005146: 0699 lsls r1, r3, #26
8005148: d506 bpl.n 8005158 <UART_AdvFeatureConfig+0x70>
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
800514a: 6801 ldr r1, [r0, #0]
800514c: 6c04 ldr r4, [r0, #64] @ 0x40
800514e: 688a ldr r2, [r1, #8]
8005150: f422 5200 bic.w r2, r2, #8192 @ 0x2000
8005154: 4322 orrs r2, r4
8005156: 608a str r2, [r1, #8]
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
8005158: 065a lsls r2, r3, #25
800515a: d50a bpl.n 8005172 <UART_AdvFeatureConfig+0x8a>
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
800515c: 6801 ldr r1, [r0, #0]
800515e: 6c44 ldr r4, [r0, #68] @ 0x44
8005160: 684a ldr r2, [r1, #4]
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
8005162: f5b4 1f80 cmp.w r4, #1048576 @ 0x100000
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
8005166: f422 1280 bic.w r2, r2, #1048576 @ 0x100000
800516a: ea42 0204 orr.w r2, r2, r4
800516e: 604a str r2, [r1, #4]
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
8005170: d00b beq.n 800518a <UART_AdvFeatureConfig+0xa2>
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
8005172: 061b lsls r3, r3, #24
8005174: d506 bpl.n 8005184 <UART_AdvFeatureConfig+0x9c>
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
8005176: 6802 ldr r2, [r0, #0]
8005178: 6cc1 ldr r1, [r0, #76] @ 0x4c
800517a: 6853 ldr r3, [r2, #4]
800517c: f423 2300 bic.w r3, r3, #524288 @ 0x80000
8005180: 430b orrs r3, r1
8005182: 6053 str r3, [r2, #4]
}
8005184: f85d 4b04 ldr.w r4, [sp], #4
8005188: 4770 bx lr
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
800518a: 684a ldr r2, [r1, #4]
800518c: 6c84 ldr r4, [r0, #72] @ 0x48
800518e: f422 02c0 bic.w r2, r2, #6291456 @ 0x600000
8005192: 4322 orrs r2, r4
8005194: 604a str r2, [r1, #4]
8005196: e7ec b.n 8005172 <UART_AdvFeatureConfig+0x8a>
08005198 <UART_CheckIdleState>:
{
8005198: b538 push {r3, r4, r5, lr}
huart->ErrorCode = HAL_UART_ERROR_NONE;
800519a: 2300 movs r3, #0
{
800519c: 4604 mov r4, r0
huart->ErrorCode = HAL_UART_ERROR_NONE;
800519e: f8c0 3090 str.w r3, [r0, #144] @ 0x90
tickstart = HAL_GetTick();
80051a2: f7fb fe19 bl 8000dd8 <HAL_GetTick>
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
80051a6: 6822 ldr r2, [r4, #0]
tickstart = HAL_GetTick();
80051a8: 4605 mov r5, r0
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
80051aa: 6813 ldr r3, [r2, #0]
80051ac: 071b lsls r3, r3, #28
80051ae: d40f bmi.n 80051d0 <UART_CheckIdleState+0x38>
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
80051b0: 6813 ldr r3, [r2, #0]
80051b2: 0759 lsls r1, r3, #29
80051b4: d431 bmi.n 800521a <UART_CheckIdleState+0x82>
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80051b6: 2300 movs r3, #0
huart->gState = HAL_UART_STATE_READY;
80051b8: 2220 movs r2, #32
return HAL_OK;
80051ba: 4618 mov r0, r3
huart->gState = HAL_UART_STATE_READY;
80051bc: f8c4 2088 str.w r2, [r4, #136] @ 0x88
huart->RxState = HAL_UART_STATE_READY;
80051c0: f8c4 208c str.w r2, [r4, #140] @ 0x8c
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80051c4: 66e3 str r3, [r4, #108] @ 0x6c
huart->RxEventType = HAL_UART_RXEVENT_TC;
80051c6: 6723 str r3, [r4, #112] @ 0x70
__HAL_UNLOCK(huart);
80051c8: 2300 movs r3, #0
80051ca: f884 3084 strb.w r3, [r4, #132] @ 0x84
}
80051ce: bd38 pop {r3, r4, r5, pc}
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
80051d0: 69d3 ldr r3, [r2, #28]
80051d2: 0298 lsls r0, r3, #10
80051d4: d4ec bmi.n 80051b0 <UART_CheckIdleState+0x18>
80051d6: e00c b.n 80051f2 <UART_CheckIdleState+0x5a>
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
80051d8: 6819 ldr r1, [r3, #0]
80051da: 461a mov r2, r3
80051dc: 0749 lsls r1, r1, #29
80051de: d505 bpl.n 80051ec <UART_CheckIdleState+0x54>
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
80051e0: 69d9 ldr r1, [r3, #28]
80051e2: 0708 lsls r0, r1, #28
80051e4: d44a bmi.n 800527c <UART_CheckIdleState+0xe4>
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
80051e6: 69d9 ldr r1, [r3, #28]
80051e8: 0509 lsls r1, r1, #20
80051ea: d475 bmi.n 80052d8 <UART_CheckIdleState+0x140>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
80051ec: 69db ldr r3, [r3, #28]
80051ee: 0298 lsls r0, r3, #10
80051f0: d4de bmi.n 80051b0 <UART_CheckIdleState+0x18>
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
80051f2: f7fb fdf1 bl 8000dd8 <HAL_GetTick>
80051f6: 1b43 subs r3, r0, r5
80051f8: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
80051fc: 6823 ldr r3, [r4, #0]
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
80051fe: d3eb bcc.n 80051d8 <UART_CheckIdleState+0x40>
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005200: e853 2f00 ldrex r2, [r3]
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
8005204: f022 0280 bic.w r2, r2, #128 @ 0x80
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005208: e843 2100 strex r1, r2, [r3]
800520c: 2900 cmp r1, #0
800520e: d1f7 bne.n 8005200 <UART_CheckIdleState+0x68>
huart->gState = HAL_UART_STATE_READY;
8005210: 2320 movs r3, #32
8005212: f8c4 3088 str.w r3, [r4, #136] @ 0x88
return HAL_TIMEOUT;
8005216: 2003 movs r0, #3
8005218: e7d6 b.n 80051c8 <UART_CheckIdleState+0x30>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
800521a: 69d3 ldr r3, [r2, #28]
800521c: 025b lsls r3, r3, #9
800521e: d4ca bmi.n 80051b6 <UART_CheckIdleState+0x1e>
8005220: e00d b.n 800523e <UART_CheckIdleState+0xa6>
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
8005222: 681a ldr r2, [r3, #0]
8005224: 0750 lsls r0, r2, #29
8005226: d507 bpl.n 8005238 <UART_CheckIdleState+0xa0>
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
8005228: 69da ldr r2, [r3, #28]
800522a: 0711 lsls r1, r2, #28
800522c: f100 8082 bmi.w 8005334 <UART_CheckIdleState+0x19c>
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
8005230: 69da ldr r2, [r3, #28]
8005232: 0512 lsls r2, r2, #20
8005234: f100 80ac bmi.w 8005390 <UART_CheckIdleState+0x1f8>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8005238: 69db ldr r3, [r3, #28]
800523a: 025b lsls r3, r3, #9
800523c: d4bb bmi.n 80051b6 <UART_CheckIdleState+0x1e>
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
800523e: f7fb fdcb bl 8000dd8 <HAL_GetTick>
8005242: 1b43 subs r3, r0, r5
8005244: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
8005248: 6823 ldr r3, [r4, #0]
800524a: d3ea bcc.n 8005222 <UART_CheckIdleState+0x8a>
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800524c: e853 2f00 ldrex r2, [r3]
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
8005250: f422 7290 bic.w r2, r2, #288 @ 0x120
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005254: e843 2100 strex r1, r2, [r3]
8005258: 2900 cmp r1, #0
800525a: d1f7 bne.n 800524c <UART_CheckIdleState+0xb4>
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800525c: f103 0208 add.w r2, r3, #8
8005260: e852 2f00 ldrex r2, [r2]
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8005264: f022 0201 bic.w r2, r2, #1
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005268: f103 0008 add.w r0, r3, #8
800526c: e840 2100 strex r1, r2, [r0]
8005270: 2900 cmp r1, #0
8005272: d1f3 bne.n 800525c <UART_CheckIdleState+0xc4>
huart->RxState = HAL_UART_STATE_READY;
8005274: 2320 movs r3, #32
8005276: f8c4 308c str.w r3, [r4, #140] @ 0x8c
return HAL_TIMEOUT;
800527a: e7cc b.n 8005216 <UART_CheckIdleState+0x7e>
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
800527c: 2208 movs r2, #8
800527e: 621a str r2, [r3, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005280: e853 2f00 ldrex r2, [r3]
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
8005284: f422 7290 bic.w r2, r2, #288 @ 0x120
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005288: e843 2100 strex r1, r2, [r3]
800528c: 2900 cmp r1, #0
800528e: d1f7 bne.n 8005280 <UART_CheckIdleState+0xe8>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
8005290: 4856 ldr r0, [pc, #344] @ (80053ec <UART_CheckIdleState+0x254>)
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005292: f103 0208 add.w r2, r3, #8
8005296: e852 2f00 ldrex r2, [r2]
800529a: 4002 ands r2, r0
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800529c: f103 0508 add.w r5, r3, #8
80052a0: e845 2100 strex r1, r2, [r5]
80052a4: 2900 cmp r1, #0
80052a6: d1f4 bne.n 8005292 <UART_CheckIdleState+0xfa>
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
80052a8: 6ee2 ldr r2, [r4, #108] @ 0x6c
80052aa: 2a01 cmp r2, #1
80052ac: d00b beq.n 80052c6 <UART_CheckIdleState+0x12e>
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80052ae: 2200 movs r2, #0
huart->RxState = HAL_UART_STATE_READY;
80052b0: 2020 movs r0, #32
huart->ErrorCode = HAL_UART_ERROR_ORE;
80052b2: 2108 movs r1, #8
huart->RxState = HAL_UART_STATE_READY;
80052b4: f8c4 008c str.w r0, [r4, #140] @ 0x8c
huart->RxISR = NULL;
80052b8: 6762 str r2, [r4, #116] @ 0x74
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80052ba: 66e2 str r2, [r4, #108] @ 0x6c
__HAL_UNLOCK(huart);
80052bc: f884 2084 strb.w r2, [r4, #132] @ 0x84
huart->ErrorCode = HAL_UART_ERROR_ORE;
80052c0: f8c4 1090 str.w r1, [r4, #144] @ 0x90
return HAL_ERROR;
80052c4: e79c b.n 8005200 <UART_CheckIdleState+0x68>
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80052c6: e853 2f00 ldrex r2, [r3]
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
80052ca: f022 0210 bic.w r2, r2, #16
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80052ce: e843 2100 strex r1, r2, [r3]
80052d2: 2900 cmp r1, #0
80052d4: d1f7 bne.n 80052c6 <UART_CheckIdleState+0x12e>
80052d6: e7ea b.n 80052ae <UART_CheckIdleState+0x116>
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
80052d8: f44f 6200 mov.w r2, #2048 @ 0x800
80052dc: 621a str r2, [r3, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80052de: e853 2f00 ldrex r2, [r3]
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
80052e2: f422 7290 bic.w r2, r2, #288 @ 0x120
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80052e6: e843 2100 strex r1, r2, [r3]
80052ea: 2900 cmp r1, #0
80052ec: d1f7 bne.n 80052de <UART_CheckIdleState+0x146>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
80052ee: 483f ldr r0, [pc, #252] @ (80053ec <UART_CheckIdleState+0x254>)
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80052f0: f103 0208 add.w r2, r3, #8
80052f4: e852 2f00 ldrex r2, [r2]
80052f8: 4002 ands r2, r0
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80052fa: f103 0508 add.w r5, r3, #8
80052fe: e845 2100 strex r1, r2, [r5]
8005302: 2900 cmp r1, #0
8005304: d1f4 bne.n 80052f0 <UART_CheckIdleState+0x158>
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8005306: 6ee2 ldr r2, [r4, #108] @ 0x6c
8005308: 2a01 cmp r2, #1
800530a: d00a beq.n 8005322 <UART_CheckIdleState+0x18a>
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
800530c: 2200 movs r2, #0
huart->RxState = HAL_UART_STATE_READY;
800530e: 2120 movs r1, #32
huart->RxISR = NULL;
8005310: 6762 str r2, [r4, #116] @ 0x74
huart->RxState = HAL_UART_STATE_READY;
8005312: f8c4 108c str.w r1, [r4, #140] @ 0x8c
__HAL_UNLOCK(huart);
8005316: f884 2084 strb.w r2, [r4, #132] @ 0x84
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
800531a: 66e2 str r2, [r4, #108] @ 0x6c
huart->ErrorCode = HAL_UART_ERROR_RTO;
800531c: f8c4 1090 str.w r1, [r4, #144] @ 0x90
return HAL_TIMEOUT;
8005320: e76e b.n 8005200 <UART_CheckIdleState+0x68>
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005322: e853 2f00 ldrex r2, [r3]
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8005326: f022 0210 bic.w r2, r2, #16
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800532a: e843 2100 strex r1, r2, [r3]
800532e: 2900 cmp r1, #0
8005330: d1f7 bne.n 8005322 <UART_CheckIdleState+0x18a>
8005332: e7eb b.n 800530c <UART_CheckIdleState+0x174>
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
8005334: 2208 movs r2, #8
8005336: 621a str r2, [r3, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005338: e853 2f00 ldrex r2, [r3]
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
800533c: f422 7290 bic.w r2, r2, #288 @ 0x120
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005340: e843 2100 strex r1, r2, [r3]
8005344: 2900 cmp r1, #0
8005346: d1f7 bne.n 8005338 <UART_CheckIdleState+0x1a0>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
8005348: 4828 ldr r0, [pc, #160] @ (80053ec <UART_CheckIdleState+0x254>)
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800534a: f103 0208 add.w r2, r3, #8
800534e: e852 2f00 ldrex r2, [r2]
8005352: 4002 ands r2, r0
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005354: f103 0508 add.w r5, r3, #8
8005358: e845 2100 strex r1, r2, [r5]
800535c: 2900 cmp r1, #0
800535e: d1f4 bne.n 800534a <UART_CheckIdleState+0x1b2>
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8005360: 6ee2 ldr r2, [r4, #108] @ 0x6c
8005362: 2a01 cmp r2, #1
8005364: d00b beq.n 800537e <UART_CheckIdleState+0x1e6>
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8005366: 2200 movs r2, #0
huart->RxState = HAL_UART_STATE_READY;
8005368: 2020 movs r0, #32
huart->ErrorCode = HAL_UART_ERROR_ORE;
800536a: 2108 movs r1, #8
huart->RxState = HAL_UART_STATE_READY;
800536c: f8c4 008c str.w r0, [r4, #140] @ 0x8c
huart->RxISR = NULL;
8005370: 6762 str r2, [r4, #116] @ 0x74
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8005372: 66e2 str r2, [r4, #108] @ 0x6c
__HAL_UNLOCK(huart);
8005374: f884 2084 strb.w r2, [r4, #132] @ 0x84
huart->ErrorCode = HAL_UART_ERROR_ORE;
8005378: f8c4 1090 str.w r1, [r4, #144] @ 0x90
return HAL_ERROR;
800537c: e766 b.n 800524c <UART_CheckIdleState+0xb4>
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800537e: e853 2f00 ldrex r2, [r3]
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8005382: f022 0210 bic.w r2, r2, #16
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8005386: e843 2100 strex r1, r2, [r3]
800538a: 2900 cmp r1, #0
800538c: d1f7 bne.n 800537e <UART_CheckIdleState+0x1e6>
800538e: e7ea b.n 8005366 <UART_CheckIdleState+0x1ce>
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
8005390: f44f 6200 mov.w r2, #2048 @ 0x800
8005394: 621a str r2, [r3, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005396: e853 2f00 ldrex r2, [r3]
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
800539a: f422 7290 bic.w r2, r2, #288 @ 0x120
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800539e: e843 2100 strex r1, r2, [r3]
80053a2: 2900 cmp r1, #0
80053a4: d1f7 bne.n 8005396 <UART_CheckIdleState+0x1fe>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
80053a6: 4811 ldr r0, [pc, #68] @ (80053ec <UART_CheckIdleState+0x254>)
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80053a8: f103 0208 add.w r2, r3, #8
80053ac: e852 2f00 ldrex r2, [r2]
80053b0: 4002 ands r2, r0
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80053b2: f103 0508 add.w r5, r3, #8
80053b6: e845 2100 strex r1, r2, [r5]
80053ba: 2900 cmp r1, #0
80053bc: d1f4 bne.n 80053a8 <UART_CheckIdleState+0x210>
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
80053be: 6ee2 ldr r2, [r4, #108] @ 0x6c
80053c0: 2a01 cmp r2, #1
80053c2: d00a beq.n 80053da <UART_CheckIdleState+0x242>
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80053c4: 2200 movs r2, #0
huart->RxState = HAL_UART_STATE_READY;
80053c6: 2120 movs r1, #32
huart->RxISR = NULL;
80053c8: 6762 str r2, [r4, #116] @ 0x74
huart->RxState = HAL_UART_STATE_READY;
80053ca: f8c4 108c str.w r1, [r4, #140] @ 0x8c
__HAL_UNLOCK(huart);
80053ce: f884 2084 strb.w r2, [r4, #132] @ 0x84
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80053d2: 66e2 str r2, [r4, #108] @ 0x6c
huart->ErrorCode = HAL_UART_ERROR_RTO;
80053d4: f8c4 1090 str.w r1, [r4, #144] @ 0x90
return HAL_TIMEOUT;
80053d8: e738 b.n 800524c <UART_CheckIdleState+0xb4>
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80053da: e853 2f00 ldrex r2, [r3]
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
80053de: f022 0210 bic.w r2, r2, #16
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80053e2: e843 2100 strex r1, r2, [r3]
80053e6: 2900 cmp r1, #0
80053e8: d1f7 bne.n 80053da <UART_CheckIdleState+0x242>
80053ea: e7eb b.n 80053c4 <UART_CheckIdleState+0x22c>
80053ec: effffffe .word 0xeffffffe
080053f0 <HAL_UART_Init>:
if (huart == NULL)
80053f0: b380 cbz r0, 8005454 <HAL_UART_Init+0x64>
if (huart->gState == HAL_UART_STATE_RESET)
80053f2: f8d0 3088 ldr.w r3, [r0, #136] @ 0x88
{
80053f6: b510 push {r4, lr}
80053f8: 4604 mov r4, r0
if (huart->gState == HAL_UART_STATE_RESET)
80053fa: b333 cbz r3, 800544a <HAL_UART_Init+0x5a>
__HAL_UART_DISABLE(huart);
80053fc: 6822 ldr r2, [r4, #0]
huart->gState = HAL_UART_STATE_BUSY;
80053fe: 2324 movs r3, #36 @ 0x24
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
8005400: 6aa1 ldr r1, [r4, #40] @ 0x28
huart->gState = HAL_UART_STATE_BUSY;
8005402: f8c4 3088 str.w r3, [r4, #136] @ 0x88
__HAL_UART_DISABLE(huart);
8005406: 6813 ldr r3, [r2, #0]
8005408: f023 0301 bic.w r3, r3, #1
800540c: 6013 str r3, [r2, #0]
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
800540e: b9c1 cbnz r1, 8005442 <HAL_UART_Init+0x52>
if (UART_SetConfig(huart) == HAL_ERROR)
8005410: 4620 mov r0, r4
8005412: f7ff fcab bl 8004d6c <UART_SetConfig>
8005416: 2801 cmp r0, #1
8005418: d011 beq.n 800543e <HAL_UART_Init+0x4e>
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
800541a: 6823 ldr r3, [r4, #0]
return (UART_CheckIdleState(huart));
800541c: 4620 mov r0, r4
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
800541e: 685a ldr r2, [r3, #4]
8005420: f422 4290 bic.w r2, r2, #18432 @ 0x4800
8005424: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8005426: 689a ldr r2, [r3, #8]
8005428: f022 022a bic.w r2, r2, #42 @ 0x2a
800542c: 609a str r2, [r3, #8]
__HAL_UART_ENABLE(huart);
800542e: 681a ldr r2, [r3, #0]
8005430: f042 0201 orr.w r2, r2, #1
}
8005434: e8bd 4010 ldmia.w sp!, {r4, lr}
__HAL_UART_ENABLE(huart);
8005438: 601a str r2, [r3, #0]
return (UART_CheckIdleState(huart));
800543a: f7ff bead b.w 8005198 <UART_CheckIdleState>
}
800543e: 2001 movs r0, #1
8005440: bd10 pop {r4, pc}
UART_AdvFeatureConfig(huart);
8005442: 4620 mov r0, r4
8005444: f7ff fe50 bl 80050e8 <UART_AdvFeatureConfig>
8005448: e7e2 b.n 8005410 <HAL_UART_Init+0x20>
huart->Lock = HAL_UNLOCKED;
800544a: f880 3084 strb.w r3, [r0, #132] @ 0x84
HAL_UART_MspInit(huart);
800544e: f7fb fbef bl 8000c30 <HAL_UART_MspInit>
8005452: e7d3 b.n 80053fc <HAL_UART_Init+0xc>
}
8005454: 2001 movs r0, #1
8005456: 4770 bx lr
08005458 <HAL_UARTEx_WakeupCallback>:
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_WakeupCallback can be implemented in the user file.
*/
}
8005458: 4770 bx lr
800545a: bf00 nop
0800545c <HAL_UARTEx_RxFifoFullCallback>:
/**
* @brief UART RX Fifo full callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
800545c: 4770 bx lr
800545e: bf00 nop
08005460 <HAL_UARTEx_TxFifoEmptyCallback>:
/**
* @brief UART TX Fifo empty callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
8005460: 4770 bx lr
8005462: bf00 nop
08005464 <HAL_UARTEx_DisableFifoMode>:
/* Check parameters */
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
/* Process Locked */
__HAL_LOCK(huart);
8005464: f890 2084 ldrb.w r2, [r0, #132] @ 0x84
8005468: 2a01 cmp r2, #1
800546a: d017 beq.n 800549c <HAL_UARTEx_DisableFifoMode+0x38>
huart->gState = HAL_UART_STATE_BUSY;
/* Save actual UART configuration */
tmpcr1 = READ_REG(huart->Instance->CR1);
800546c: 6802 ldr r2, [r0, #0]
800546e: 4603 mov r3, r0
huart->gState = HAL_UART_STATE_BUSY;
8005470: 2024 movs r0, #36 @ 0x24
/* Disable UART */
__HAL_UART_DISABLE(huart);
/* Disable FIFO mode */
CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
huart->FifoMode = UART_FIFOMODE_DISABLE;
8005472: 2100 movs r1, #0
{
8005474: b430 push {r4, r5}
huart->gState = HAL_UART_STATE_BUSY;
8005476: f8c3 0088 str.w r0, [r3, #136] @ 0x88
/* Restore UART configuration */
WRITE_REG(huart->Instance->CR1, tmpcr1);
huart->gState = HAL_UART_STATE_READY;
800547a: 2520 movs r5, #32
tmpcr1 = READ_REG(huart->Instance->CR1);
800547c: 6810 ldr r0, [r2, #0]
__HAL_UART_DISABLE(huart);
800547e: 6814 ldr r4, [r2, #0]
CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
8005480: f020 5000 bic.w r0, r0, #536870912 @ 0x20000000
__HAL_UART_DISABLE(huart);
8005484: f024 0401 bic.w r4, r4, #1
8005488: 6014 str r4, [r2, #0]
huart->FifoMode = UART_FIFOMODE_DISABLE;
800548a: 6659 str r1, [r3, #100] @ 0x64
WRITE_REG(huart->Instance->CR1, tmpcr1);
800548c: 6010 str r0, [r2, #0]
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
800548e: 4608 mov r0, r1
huart->gState = HAL_UART_STATE_READY;
8005490: f8c3 5088 str.w r5, [r3, #136] @ 0x88
__HAL_UNLOCK(huart);
8005494: f883 1084 strb.w r1, [r3, #132] @ 0x84
}
8005498: bc30 pop {r4, r5}
800549a: 4770 bx lr
__HAL_LOCK(huart);
800549c: 2002 movs r0, #2
}
800549e: 4770 bx lr
080054a0 <HAL_UARTEx_SetTxFifoThreshold>:
/* Check parameters */
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
/* Process Locked */
__HAL_LOCK(huart);
80054a0: f890 2084 ldrb.w r2, [r0, #132] @ 0x84
80054a4: 2a01 cmp r2, #1
80054a6: d037 beq.n 8005518 <HAL_UARTEx_SetTxFifoThreshold+0x78>
huart->gState = HAL_UART_STATE_BUSY;
/* Save actual UART configuration */
tmpcr1 = READ_REG(huart->Instance->CR1);
80054a8: 6802 ldr r2, [r0, #0]
80054aa: 4603 mov r3, r0
huart->gState = HAL_UART_STATE_BUSY;
80054ac: 2024 movs r0, #36 @ 0x24
{
80054ae: b530 push {r4, r5, lr}
huart->gState = HAL_UART_STATE_BUSY;
80054b0: f8c3 0088 str.w r0, [r3, #136] @ 0x88
tmpcr1 = READ_REG(huart->Instance->CR1);
80054b4: 6814 ldr r4, [r2, #0]
/* Disable UART */
__HAL_UART_DISABLE(huart);
80054b6: 6810 ldr r0, [r2, #0]
80054b8: f020 0001 bic.w r0, r0, #1
80054bc: 6010 str r0, [r2, #0]
/* Update TX threshold configuration */
MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
80054be: 6890 ldr r0, [r2, #8]
80054c0: f020 4060 bic.w r0, r0, #3758096384 @ 0xe0000000
80054c4: 4301 orrs r1, r0
uint8_t rx_fifo_threshold;
uint8_t tx_fifo_threshold;
static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
if (huart->FifoMode == UART_FIFOMODE_DISABLE)
80054c6: 6e58 ldr r0, [r3, #100] @ 0x64
MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
80054c8: 6091 str r1, [r2, #8]
if (huart->FifoMode == UART_FIFOMODE_DISABLE)
80054ca: b310 cbz r0, 8005512 <HAL_UARTEx_SetTxFifoThreshold+0x72>
}
else
{
rx_fifo_depth = RX_FIFO_DEPTH;
tx_fifo_depth = TX_FIFO_DEPTH;
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
80054cc: 6891 ldr r1, [r2, #8]
tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
80054ce: 6890 ldr r0, [r2, #8]
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
(uint16_t)denominator[tx_fifo_threshold];
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
80054d0: f3c1 6c42 ubfx ip, r1, #25, #3
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
80054d4: 4911 ldr r1, [pc, #68] @ (800551c <HAL_UARTEx_SetTxFifoThreshold+0x7c>)
tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
80054d6: ea4f 7e50 mov.w lr, r0, lsr #29
(uint16_t)denominator[tx_fifo_threshold];
80054da: 4d11 ldr r5, [pc, #68] @ (8005520 <HAL_UARTEx_SetTxFifoThreshold+0x80>)
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
80054dc: f811 000e ldrb.w r0, [r1, lr]
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
80054e0: f811 100c ldrb.w r1, [r1, ip]
(uint16_t)denominator[tx_fifo_threshold];
80054e4: f815 e00e ldrb.w lr, [r5, lr]
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
80054e8: 0100 lsls r0, r0, #4
(uint16_t)denominator[rx_fifo_threshold];
80054ea: f815 500c ldrb.w r5, [r5, ip]
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
80054ee: 0109 lsls r1, r1, #4
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
80054f0: fbb0 f0fe udiv r0, r0, lr
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
80054f4: fbb1 f1f5 udiv r1, r1, r5
80054f8: f8a3 1068 strh.w r1, [r3, #104] @ 0x68
huart->gState = HAL_UART_STATE_READY;
80054fc: 2520 movs r5, #32
__HAL_UNLOCK(huart);
80054fe: 2100 movs r1, #0
8005500: f8a3 006a strh.w r0, [r3, #106] @ 0x6a
WRITE_REG(huart->Instance->CR1, tmpcr1);
8005504: 6014 str r4, [r2, #0]
return HAL_OK;
8005506: 4608 mov r0, r1
huart->gState = HAL_UART_STATE_READY;
8005508: f8c3 5088 str.w r5, [r3, #136] @ 0x88
__HAL_UNLOCK(huart);
800550c: f883 1084 strb.w r1, [r3, #132] @ 0x84
}
8005510: bd30 pop {r4, r5, pc}
huart->NbRxDataToProcess = 1U;
8005512: 2101 movs r1, #1
huart->NbTxDataToProcess = 1U;
8005514: 4608 mov r0, r1
8005516: e7ef b.n 80054f8 <HAL_UARTEx_SetTxFifoThreshold+0x58>
__HAL_LOCK(huart);
8005518: 2002 movs r0, #2
}
800551a: 4770 bx lr
800551c: 08005648 .word 0x08005648
8005520: 08005640 .word 0x08005640
08005524 <HAL_UARTEx_SetRxFifoThreshold>:
__HAL_LOCK(huart);
8005524: f890 2084 ldrb.w r2, [r0, #132] @ 0x84
8005528: 2a01 cmp r2, #1
800552a: d037 beq.n 800559c <HAL_UARTEx_SetRxFifoThreshold+0x78>
tmpcr1 = READ_REG(huart->Instance->CR1);
800552c: 6802 ldr r2, [r0, #0]
800552e: 4603 mov r3, r0
huart->gState = HAL_UART_STATE_BUSY;
8005530: 2024 movs r0, #36 @ 0x24
{
8005532: b530 push {r4, r5, lr}
huart->gState = HAL_UART_STATE_BUSY;
8005534: f8c3 0088 str.w r0, [r3, #136] @ 0x88
tmpcr1 = READ_REG(huart->Instance->CR1);
8005538: 6814 ldr r4, [r2, #0]
__HAL_UART_DISABLE(huart);
800553a: 6810 ldr r0, [r2, #0]
800553c: f020 0001 bic.w r0, r0, #1
8005540: 6010 str r0, [r2, #0]
MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
8005542: 6890 ldr r0, [r2, #8]
8005544: f020 6060 bic.w r0, r0, #234881024 @ 0xe000000
8005548: 4301 orrs r1, r0
if (huart->FifoMode == UART_FIFOMODE_DISABLE)
800554a: 6e58 ldr r0, [r3, #100] @ 0x64
MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
800554c: 6091 str r1, [r2, #8]
if (huart->FifoMode == UART_FIFOMODE_DISABLE)
800554e: b310 cbz r0, 8005596 <HAL_UARTEx_SetRxFifoThreshold+0x72>
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
8005550: 6891 ldr r1, [r2, #8]
tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
8005552: 6890 ldr r0, [r2, #8]
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
8005554: f3c1 6c42 ubfx ip, r1, #25, #3
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
8005558: 4911 ldr r1, [pc, #68] @ (80055a0 <HAL_UARTEx_SetRxFifoThreshold+0x7c>)
tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
800555a: ea4f 7e50 mov.w lr, r0, lsr #29
(uint16_t)denominator[tx_fifo_threshold];
800555e: 4d11 ldr r5, [pc, #68] @ (80055a4 <HAL_UARTEx_SetRxFifoThreshold+0x80>)
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
8005560: f811 000e ldrb.w r0, [r1, lr]
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
8005564: f811 100c ldrb.w r1, [r1, ip]
(uint16_t)denominator[tx_fifo_threshold];
8005568: f815 e00e ldrb.w lr, [r5, lr]
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
800556c: 0100 lsls r0, r0, #4
(uint16_t)denominator[rx_fifo_threshold];
800556e: f815 500c ldrb.w r5, [r5, ip]
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
8005572: 0109 lsls r1, r1, #4
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
8005574: fbb0 f0fe udiv r0, r0, lr
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
8005578: fbb1 f1f5 udiv r1, r1, r5
800557c: f8a3 1068 strh.w r1, [r3, #104] @ 0x68
huart->gState = HAL_UART_STATE_READY;
8005580: 2520 movs r5, #32
__HAL_UNLOCK(huart);
8005582: 2100 movs r1, #0
8005584: f8a3 006a strh.w r0, [r3, #106] @ 0x6a
WRITE_REG(huart->Instance->CR1, tmpcr1);
8005588: 6014 str r4, [r2, #0]
return HAL_OK;
800558a: 4608 mov r0, r1
huart->gState = HAL_UART_STATE_READY;
800558c: f8c3 5088 str.w r5, [r3, #136] @ 0x88
__HAL_UNLOCK(huart);
8005590: f883 1084 strb.w r1, [r3, #132] @ 0x84
}
8005594: bd30 pop {r4, r5, pc}
huart->NbRxDataToProcess = 1U;
8005596: 2101 movs r1, #1
huart->NbTxDataToProcess = 1U;
8005598: 4608 mov r0, r1
800559a: e7ef b.n 800557c <HAL_UARTEx_SetRxFifoThreshold+0x58>
__HAL_LOCK(huart);
800559c: 2002 movs r0, #2
}
800559e: 4770 bx lr
80055a0: 08005648 .word 0x08005648
80055a4: 08005640 .word 0x08005640
080055a8 <memset>:
80055a8: 4402 add r2, r0
80055aa: 4603 mov r3, r0
80055ac: 4293 cmp r3, r2
80055ae: d100 bne.n 80055b2 <memset+0xa>
80055b0: 4770 bx lr
80055b2: f803 1b01 strb.w r1, [r3], #1
80055b6: e7f9 b.n 80055ac <memset+0x4>
080055b8 <__libc_init_array>:
80055b8: b570 push {r4, r5, r6, lr}
80055ba: 4d0d ldr r5, [pc, #52] @ (80055f0 <__libc_init_array+0x38>)
80055bc: 4c0d ldr r4, [pc, #52] @ (80055f4 <__libc_init_array+0x3c>)
80055be: 1b64 subs r4, r4, r5
80055c0: 10a4 asrs r4, r4, #2
80055c2: 2600 movs r6, #0
80055c4: 42a6 cmp r6, r4
80055c6: d109 bne.n 80055dc <__libc_init_array+0x24>
80055c8: 4d0b ldr r5, [pc, #44] @ (80055f8 <__libc_init_array+0x40>)
80055ca: 4c0c ldr r4, [pc, #48] @ (80055fc <__libc_init_array+0x44>)
80055cc: f000 f818 bl 8005600 <_init>
80055d0: 1b64 subs r4, r4, r5
80055d2: 10a4 asrs r4, r4, #2
80055d4: 2600 movs r6, #0
80055d6: 42a6 cmp r6, r4
80055d8: d105 bne.n 80055e6 <__libc_init_array+0x2e>
80055da: bd70 pop {r4, r5, r6, pc}
80055dc: f855 3b04 ldr.w r3, [r5], #4
80055e0: 4798 blx r3
80055e2: 3601 adds r6, #1
80055e4: e7ee b.n 80055c4 <__libc_init_array+0xc>
80055e6: f855 3b04 ldr.w r3, [r5], #4
80055ea: 4798 blx r3
80055ec: 3601 adds r6, #1
80055ee: e7f2 b.n 80055d6 <__libc_init_array+0x1e>
80055f0: 08005658 .word 0x08005658
80055f4: 08005658 .word 0x08005658
80055f8: 08005658 .word 0x08005658
80055fc: 0800565c .word 0x0800565c
08005600 <_init>:
8005600: b5f8 push {r3, r4, r5, r6, r7, lr}
8005602: bf00 nop
8005604: bcf8 pop {r3, r4, r5, r6, r7}
8005606: bc08 pop {r3}
8005608: 469e mov lr, r3
800560a: 4770 bx lr
0800560c <_fini>:
800560c: b5f8 push {r3, r4, r5, r6, r7, lr}
800560e: bf00 nop
8005610: bcf8 pop {r3, r4, r5, r6, r7}
8005612: bc08 pop {r3}
8005614: 469e mov lr, r3
8005616: 4770 bx lr
Reference in a new issue View git blame Copy permalink