Exp01.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000298 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000a81c 08000298 08000298 00001298 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000040 0800aab4 0800aab4 0000bab4 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM 00000008 0800aaf4 0800aaf4 0000baf4 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 4 .init_array 00000004 0800aafc 0800aafc 0000bafc 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .fini_array 00000004 0800ab00 0800ab00 0000bb00 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 6 .data 00000010 24000000 0800ab04 0000c000 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .bss 00000378 24000010 0800ab14 0000c010 2**2 ALLOC 8 ._user_heap_stack 00000600 24000388 0800ab14 0000c388 2**0 ALLOC 9 .ARM.attributes 0000002e 00000000 00000000 0000c010 2**0 CONTENTS, READONLY 10 .debug_info 0001abee 00000000 00000000 0000c03e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 11 .debug_abbrev 000032c9 00000000 00000000 00026c2c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 12 .debug_aranges 000013b0 00000000 00000000 00029ef8 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_rnglists 00000f45 00000000 00000000 0002b2a8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_macro 0003b498 00000000 00000000 0002c1ed 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_line 0001c404 00000000 00000000 00067685 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_str 00177ca2 00000000 00000000 00083a89 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .comment 00000043 00000000 00000000 001fb72b 2**0 CONTENTS, READONLY 18 .debug_frame 00005230 00000000 00000000 001fb770 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_line_str 00000080 00000000 00000000 002009a0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 08000298 <__do_global_dtors_aux>: 8000298: b510 push {r4, lr} 800029a: 4c05 ldr r4, [pc, #20] @ (80002b0 <__do_global_dtors_aux+0x18>) 800029c: 7823 ldrb r3, [r4, #0] 800029e: b933 cbnz r3, 80002ae <__do_global_dtors_aux+0x16> 80002a0: 4b04 ldr r3, [pc, #16] @ (80002b4 <__do_global_dtors_aux+0x1c>) 80002a2: b113 cbz r3, 80002aa <__do_global_dtors_aux+0x12> 80002a4: 4804 ldr r0, [pc, #16] @ (80002b8 <__do_global_dtors_aux+0x20>) 80002a6: f3af 8000 nop.w 80002aa: 2301 movs r3, #1 80002ac: 7023 strb r3, [r4, #0] 80002ae: bd10 pop {r4, pc} 80002b0: 24000010 .word 0x24000010 80002b4: 00000000 .word 0x00000000 80002b8: 0800aa9c .word 0x0800aa9c 080002bc : 80002bc: b508 push {r3, lr} 80002be: 4b03 ldr r3, [pc, #12] @ (80002cc ) 80002c0: b11b cbz r3, 80002ca 80002c2: 4903 ldr r1, [pc, #12] @ (80002d0 ) 80002c4: 4803 ldr r0, [pc, #12] @ (80002d4 ) 80002c6: f3af 8000 nop.w 80002ca: bd08 pop {r3, pc} 80002cc: 00000000 .word 0x00000000 80002d0: 24000014 .word 0x24000014 80002d4: 0800aa9c .word 0x0800aa9c 080002d8 <__aeabi_uldivmod>: 80002d8: b953 cbnz r3, 80002f0 <__aeabi_uldivmod+0x18> 80002da: b94a cbnz r2, 80002f0 <__aeabi_uldivmod+0x18> 80002dc: 2900 cmp r1, #0 80002de: bf08 it eq 80002e0: 2800 cmpeq r0, #0 80002e2: bf1c itt ne 80002e4: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 80002e8: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 80002ec: f000 b988 b.w 8000600 <__aeabi_idiv0> 80002f0: f1ad 0c08 sub.w ip, sp, #8 80002f4: e96d ce04 strd ip, lr, [sp, #-16]! 80002f8: f000 f806 bl 8000308 <__udivmoddi4> 80002fc: f8dd e004 ldr.w lr, [sp, #4] 8000300: e9dd 2302 ldrd r2, r3, [sp, #8] 8000304: b004 add sp, #16 8000306: 4770 bx lr 08000308 <__udivmoddi4>: 8000308: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 800030c: 9d08 ldr r5, [sp, #32] 800030e: 468e mov lr, r1 8000310: 4604 mov r4, r0 8000312: 4688 mov r8, r1 8000314: 2b00 cmp r3, #0 8000316: d14a bne.n 80003ae <__udivmoddi4+0xa6> 8000318: 428a cmp r2, r1 800031a: 4617 mov r7, r2 800031c: d962 bls.n 80003e4 <__udivmoddi4+0xdc> 800031e: fab2 f682 clz r6, r2 8000322: b14e cbz r6, 8000338 <__udivmoddi4+0x30> 8000324: f1c6 0320 rsb r3, r6, #32 8000328: fa01 f806 lsl.w r8, r1, r6 800032c: fa20 f303 lsr.w r3, r0, r3 8000330: 40b7 lsls r7, r6 8000332: ea43 0808 orr.w r8, r3, r8 8000336: 40b4 lsls r4, r6 8000338: ea4f 4e17 mov.w lr, r7, lsr #16 800033c: fa1f fc87 uxth.w ip, r7 8000340: fbb8 f1fe udiv r1, r8, lr 8000344: 0c23 lsrs r3, r4, #16 8000346: fb0e 8811 mls r8, lr, r1, r8 800034a: ea43 4308 orr.w r3, r3, r8, lsl #16 800034e: fb01 f20c mul.w r2, r1, ip 8000352: 429a cmp r2, r3 8000354: d909 bls.n 800036a <__udivmoddi4+0x62> 8000356: 18fb adds r3, r7, r3 8000358: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff 800035c: f080 80ea bcs.w 8000534 <__udivmoddi4+0x22c> 8000360: 429a cmp r2, r3 8000362: f240 80e7 bls.w 8000534 <__udivmoddi4+0x22c> 8000366: 3902 subs r1, #2 8000368: 443b add r3, r7 800036a: 1a9a subs r2, r3, r2 800036c: b2a3 uxth r3, r4 800036e: fbb2 f0fe udiv r0, r2, lr 8000372: fb0e 2210 mls r2, lr, r0, r2 8000376: ea43 4302 orr.w r3, r3, r2, lsl #16 800037a: fb00 fc0c mul.w ip, r0, ip 800037e: 459c cmp ip, r3 8000380: d909 bls.n 8000396 <__udivmoddi4+0x8e> 8000382: 18fb adds r3, r7, r3 8000384: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff 8000388: f080 80d6 bcs.w 8000538 <__udivmoddi4+0x230> 800038c: 459c cmp ip, r3 800038e: f240 80d3 bls.w 8000538 <__udivmoddi4+0x230> 8000392: 443b add r3, r7 8000394: 3802 subs r0, #2 8000396: ea40 4001 orr.w r0, r0, r1, lsl #16 800039a: eba3 030c sub.w r3, r3, ip 800039e: 2100 movs r1, #0 80003a0: b11d cbz r5, 80003aa <__udivmoddi4+0xa2> 80003a2: 40f3 lsrs r3, r6 80003a4: 2200 movs r2, #0 80003a6: e9c5 3200 strd r3, r2, [r5] 80003aa: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80003ae: 428b cmp r3, r1 80003b0: d905 bls.n 80003be <__udivmoddi4+0xb6> 80003b2: b10d cbz r5, 80003b8 <__udivmoddi4+0xb0> 80003b4: e9c5 0100 strd r0, r1, [r5] 80003b8: 2100 movs r1, #0 80003ba: 4608 mov r0, r1 80003bc: e7f5 b.n 80003aa <__udivmoddi4+0xa2> 80003be: fab3 f183 clz r1, r3 80003c2: 2900 cmp r1, #0 80003c4: d146 bne.n 8000454 <__udivmoddi4+0x14c> 80003c6: 4573 cmp r3, lr 80003c8: d302 bcc.n 80003d0 <__udivmoddi4+0xc8> 80003ca: 4282 cmp r2, r0 80003cc: f200 8105 bhi.w 80005da <__udivmoddi4+0x2d2> 80003d0: 1a84 subs r4, r0, r2 80003d2: eb6e 0203 sbc.w r2, lr, r3 80003d6: 2001 movs r0, #1 80003d8: 4690 mov r8, r2 80003da: 2d00 cmp r5, #0 80003dc: d0e5 beq.n 80003aa <__udivmoddi4+0xa2> 80003de: e9c5 4800 strd r4, r8, [r5] 80003e2: e7e2 b.n 80003aa <__udivmoddi4+0xa2> 80003e4: 2a00 cmp r2, #0 80003e6: f000 8090 beq.w 800050a <__udivmoddi4+0x202> 80003ea: fab2 f682 clz r6, r2 80003ee: 2e00 cmp r6, #0 80003f0: f040 80a4 bne.w 800053c <__udivmoddi4+0x234> 80003f4: 1a8a subs r2, r1, r2 80003f6: 0c03 lsrs r3, r0, #16 80003f8: ea4f 4e17 mov.w lr, r7, lsr #16 80003fc: b280 uxth r0, r0 80003fe: b2bc uxth r4, r7 8000400: 2101 movs r1, #1 8000402: fbb2 fcfe udiv ip, r2, lr 8000406: fb0e 221c mls r2, lr, ip, r2 800040a: ea43 4302 orr.w r3, r3, r2, lsl #16 800040e: fb04 f20c mul.w r2, r4, ip 8000412: 429a cmp r2, r3 8000414: d907 bls.n 8000426 <__udivmoddi4+0x11e> 8000416: 18fb adds r3, r7, r3 8000418: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff 800041c: d202 bcs.n 8000424 <__udivmoddi4+0x11c> 800041e: 429a cmp r2, r3 8000420: f200 80e0 bhi.w 80005e4 <__udivmoddi4+0x2dc> 8000424: 46c4 mov ip, r8 8000426: 1a9b subs r3, r3, r2 8000428: fbb3 f2fe udiv r2, r3, lr 800042c: fb0e 3312 mls r3, lr, r2, r3 8000430: ea40 4303 orr.w r3, r0, r3, lsl #16 8000434: fb02 f404 mul.w r4, r2, r4 8000438: 429c cmp r4, r3 800043a: d907 bls.n 800044c <__udivmoddi4+0x144> 800043c: 18fb adds r3, r7, r3 800043e: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff 8000442: d202 bcs.n 800044a <__udivmoddi4+0x142> 8000444: 429c cmp r4, r3 8000446: f200 80ca bhi.w 80005de <__udivmoddi4+0x2d6> 800044a: 4602 mov r2, r0 800044c: 1b1b subs r3, r3, r4 800044e: ea42 400c orr.w r0, r2, ip, lsl #16 8000452: e7a5 b.n 80003a0 <__udivmoddi4+0x98> 8000454: f1c1 0620 rsb r6, r1, #32 8000458: 408b lsls r3, r1 800045a: fa22 f706 lsr.w r7, r2, r6 800045e: 431f orrs r7, r3 8000460: fa0e f401 lsl.w r4, lr, r1 8000464: fa20 f306 lsr.w r3, r0, r6 8000468: fa2e fe06 lsr.w lr, lr, r6 800046c: ea4f 4917 mov.w r9, r7, lsr #16 8000470: 4323 orrs r3, r4 8000472: fa00 f801 lsl.w r8, r0, r1 8000476: fa1f fc87 uxth.w ip, r7 800047a: fbbe f0f9 udiv r0, lr, r9 800047e: 0c1c lsrs r4, r3, #16 8000480: fb09 ee10 mls lr, r9, r0, lr 8000484: ea44 440e orr.w r4, r4, lr, lsl #16 8000488: fb00 fe0c mul.w lr, r0, ip 800048c: 45a6 cmp lr, r4 800048e: fa02 f201 lsl.w r2, r2, r1 8000492: d909 bls.n 80004a8 <__udivmoddi4+0x1a0> 8000494: 193c adds r4, r7, r4 8000496: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff 800049a: f080 809c bcs.w 80005d6 <__udivmoddi4+0x2ce> 800049e: 45a6 cmp lr, r4 80004a0: f240 8099 bls.w 80005d6 <__udivmoddi4+0x2ce> 80004a4: 3802 subs r0, #2 80004a6: 443c add r4, r7 80004a8: eba4 040e sub.w r4, r4, lr 80004ac: fa1f fe83 uxth.w lr, r3 80004b0: fbb4 f3f9 udiv r3, r4, r9 80004b4: fb09 4413 mls r4, r9, r3, r4 80004b8: ea4e 4404 orr.w r4, lr, r4, lsl #16 80004bc: fb03 fc0c mul.w ip, r3, ip 80004c0: 45a4 cmp ip, r4 80004c2: d908 bls.n 80004d6 <__udivmoddi4+0x1ce> 80004c4: 193c adds r4, r7, r4 80004c6: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff 80004ca: f080 8082 bcs.w 80005d2 <__udivmoddi4+0x2ca> 80004ce: 45a4 cmp ip, r4 80004d0: d97f bls.n 80005d2 <__udivmoddi4+0x2ca> 80004d2: 3b02 subs r3, #2 80004d4: 443c add r4, r7 80004d6: ea43 4000 orr.w r0, r3, r0, lsl #16 80004da: eba4 040c sub.w r4, r4, ip 80004de: fba0 ec02 umull lr, ip, r0, r2 80004e2: 4564 cmp r4, ip 80004e4: 4673 mov r3, lr 80004e6: 46e1 mov r9, ip 80004e8: d362 bcc.n 80005b0 <__udivmoddi4+0x2a8> 80004ea: d05f beq.n 80005ac <__udivmoddi4+0x2a4> 80004ec: b15d cbz r5, 8000506 <__udivmoddi4+0x1fe> 80004ee: ebb8 0203 subs.w r2, r8, r3 80004f2: eb64 0409 sbc.w r4, r4, r9 80004f6: fa04 f606 lsl.w r6, r4, r6 80004fa: fa22 f301 lsr.w r3, r2, r1 80004fe: 431e orrs r6, r3 8000500: 40cc lsrs r4, r1 8000502: e9c5 6400 strd r6, r4, [r5] 8000506: 2100 movs r1, #0 8000508: e74f b.n 80003aa <__udivmoddi4+0xa2> 800050a: fbb1 fcf2 udiv ip, r1, r2 800050e: 0c01 lsrs r1, r0, #16 8000510: ea41 410e orr.w r1, r1, lr, lsl #16 8000514: b280 uxth r0, r0 8000516: ea40 4201 orr.w r2, r0, r1, lsl #16 800051a: 463b mov r3, r7 800051c: 4638 mov r0, r7 800051e: 463c mov r4, r7 8000520: 46b8 mov r8, r7 8000522: 46be mov lr, r7 8000524: 2620 movs r6, #32 8000526: fbb1 f1f7 udiv r1, r1, r7 800052a: eba2 0208 sub.w r2, r2, r8 800052e: ea41 410c orr.w r1, r1, ip, lsl #16 8000532: e766 b.n 8000402 <__udivmoddi4+0xfa> 8000534: 4601 mov r1, r0 8000536: e718 b.n 800036a <__udivmoddi4+0x62> 8000538: 4610 mov r0, r2 800053a: e72c b.n 8000396 <__udivmoddi4+0x8e> 800053c: f1c6 0220 rsb r2, r6, #32 8000540: fa2e f302 lsr.w r3, lr, r2 8000544: 40b7 lsls r7, r6 8000546: 40b1 lsls r1, r6 8000548: fa20 f202 lsr.w r2, r0, r2 800054c: ea4f 4e17 mov.w lr, r7, lsr #16 8000550: 430a orrs r2, r1 8000552: fbb3 f8fe udiv r8, r3, lr 8000556: b2bc uxth r4, r7 8000558: fb0e 3318 mls r3, lr, r8, r3 800055c: 0c11 lsrs r1, r2, #16 800055e: ea41 4103 orr.w r1, r1, r3, lsl #16 8000562: fb08 f904 mul.w r9, r8, r4 8000566: 40b0 lsls r0, r6 8000568: 4589 cmp r9, r1 800056a: ea4f 4310 mov.w r3, r0, lsr #16 800056e: b280 uxth r0, r0 8000570: d93e bls.n 80005f0 <__udivmoddi4+0x2e8> 8000572: 1879 adds r1, r7, r1 8000574: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff 8000578: d201 bcs.n 800057e <__udivmoddi4+0x276> 800057a: 4589 cmp r9, r1 800057c: d81f bhi.n 80005be <__udivmoddi4+0x2b6> 800057e: eba1 0109 sub.w r1, r1, r9 8000582: fbb1 f9fe udiv r9, r1, lr 8000586: fb09 f804 mul.w r8, r9, r4 800058a: fb0e 1119 mls r1, lr, r9, r1 800058e: b292 uxth r2, r2 8000590: ea42 4201 orr.w r2, r2, r1, lsl #16 8000594: 4542 cmp r2, r8 8000596: d229 bcs.n 80005ec <__udivmoddi4+0x2e4> 8000598: 18ba adds r2, r7, r2 800059a: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff 800059e: d2c4 bcs.n 800052a <__udivmoddi4+0x222> 80005a0: 4542 cmp r2, r8 80005a2: d2c2 bcs.n 800052a <__udivmoddi4+0x222> 80005a4: f1a9 0102 sub.w r1, r9, #2 80005a8: 443a add r2, r7 80005aa: e7be b.n 800052a <__udivmoddi4+0x222> 80005ac: 45f0 cmp r8, lr 80005ae: d29d bcs.n 80004ec <__udivmoddi4+0x1e4> 80005b0: ebbe 0302 subs.w r3, lr, r2 80005b4: eb6c 0c07 sbc.w ip, ip, r7 80005b8: 3801 subs r0, #1 80005ba: 46e1 mov r9, ip 80005bc: e796 b.n 80004ec <__udivmoddi4+0x1e4> 80005be: eba7 0909 sub.w r9, r7, r9 80005c2: 4449 add r1, r9 80005c4: f1a8 0c02 sub.w ip, r8, #2 80005c8: fbb1 f9fe udiv r9, r1, lr 80005cc: fb09 f804 mul.w r8, r9, r4 80005d0: e7db b.n 800058a <__udivmoddi4+0x282> 80005d2: 4673 mov r3, lr 80005d4: e77f b.n 80004d6 <__udivmoddi4+0x1ce> 80005d6: 4650 mov r0, sl 80005d8: e766 b.n 80004a8 <__udivmoddi4+0x1a0> 80005da: 4608 mov r0, r1 80005dc: e6fd b.n 80003da <__udivmoddi4+0xd2> 80005de: 443b add r3, r7 80005e0: 3a02 subs r2, #2 80005e2: e733 b.n 800044c <__udivmoddi4+0x144> 80005e4: f1ac 0c02 sub.w ip, ip, #2 80005e8: 443b add r3, r7 80005ea: e71c b.n 8000426 <__udivmoddi4+0x11e> 80005ec: 4649 mov r1, r9 80005ee: e79c b.n 800052a <__udivmoddi4+0x222> 80005f0: eba1 0109 sub.w r1, r1, r9 80005f4: 46c4 mov ip, r8 80005f6: fbb1 f9fe udiv r9, r1, lr 80005fa: fb09 f804 mul.w r8, r9, r4 80005fe: e7c4 b.n 800058a <__udivmoddi4+0x282> 08000600 <__aeabi_idiv0>: 8000600: 4770 bx lr 8000602: bf00 nop 08000604 : #define READ_CH 1 // definisci il vettore per i risultati delle misure void ADC_calibrate(){ 8000604: b480 push {r7} 8000606: af00 add r7, sp, #0 // calibrazione // ADC3->CR |= ADC_CR_ADCALDIF; // SOLO per misure differenziali (defualt=0) // esegui anche calibrazione linearità (oltre che offest) ADC3->CR |= ADC_CR_ADCALLIN; 8000608: 4b08 ldr r3, [pc, #32] @ (800062c ) 800060a: 689b ldr r3, [r3, #8] 800060c: 4a07 ldr r2, [pc, #28] @ (800062c ) 800060e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8000612: 6093 str r3, [r2, #8] // inizia la calibrazione ADC3->CR |= ADC_CR_ADCAL; 8000614: 4b05 ldr r3, [pc, #20] @ (800062c ) 8000616: 689b ldr r3, [r3, #8] 8000618: 4a04 ldr r2, [pc, #16] @ (800062c ) 800061a: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 800061e: 6093 str r3, [r2, #8] } 8000620: bf00 nop 8000622: 46bd mov sp, r7 8000624: f85d 7b04 ldr.w r7, [sp], #4 8000628: 4770 bx lr 800062a: bf00 nop 800062c: 58026000 .word 0x58026000 08000630 : void DMA_init(){ 8000630: b480 push {r7} 8000632: af00 add r7, sp, #0 // DMA per USART (DMA1 stream3) DMA1_Stream3->M0AR = (uint32_t) &results; 8000634: 4b19 ldr r3, [pc, #100] @ (800069c ) 8000636: 4a1a ldr r2, [pc, #104] @ (80006a0 ) 8000638: 60da str r2, [r3, #12] DMA1_Stream3->PAR = (uint32_t) &(USART3->TDR); 800063a: 4b18 ldr r3, [pc, #96] @ (800069c ) 800063c: 4a19 ldr r2, [pc, #100] @ (80006a4 ) 800063e: 609a str r2, [r3, #8] DMA1_Stream3->NDTR = (uint16_t) (N_MEAS+1)*2; // send signle bytes 8000640: 4b16 ldr r3, [pc, #88] @ (800069c ) 8000642: 22ca movs r2, #202 @ 0xca 8000644: 605a str r2, [r3, #4] DMA1->LIFCR = 0xffffffff; 8000646: 4b18 ldr r3, [pc, #96] @ (80006a8 ) 8000648: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800064c: 609a str r2, [r3, #8] DMA1->HIFCR = 0xffffffff; 800064e: 4b16 ldr r3, [pc, #88] @ (80006a8 ) 8000650: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8000654: 60da str r2, [r3, #12] DMA1_Stream3->CR |= DMA_SxCR_TCIE; 8000656: 4b11 ldr r3, [pc, #68] @ (800069c ) 8000658: 681b ldr r3, [r3, #0] 800065a: 4a10 ldr r2, [pc, #64] @ (800069c ) 800065c: f043 0310 orr.w r3, r3, #16 8000660: 6013 str r3, [r2, #0] // DMA per ADC (DMA2 stream0) DMA2_Stream0->M0AR = (uint32_t) &results; 8000662: 4b12 ldr r3, [pc, #72] @ (80006ac ) 8000664: 4a0e ldr r2, [pc, #56] @ (80006a0 ) 8000666: 60da str r2, [r3, #12] DMA2_Stream0->PAR = (uint32_t) &(ADC3->DR); 8000668: 4b10 ldr r3, [pc, #64] @ (80006ac ) 800066a: 4a11 ldr r2, [pc, #68] @ (80006b0 ) 800066c: 609a str r2, [r3, #8] DMA2_Stream0->NDTR = (uint16_t) N_MEAS; 800066e: 4b0f ldr r3, [pc, #60] @ (80006ac ) 8000670: 2264 movs r2, #100 @ 0x64 8000672: 605a str r2, [r3, #4] DMA2->LIFCR = 0xffffffff; 8000674: 4b0f ldr r3, [pc, #60] @ (80006b4 ) 8000676: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800067a: 609a str r2, [r3, #8] DMA2->HIFCR = 0xffffffff; 800067c: 4b0d ldr r3, [pc, #52] @ (80006b4 ) 800067e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8000682: 60da str r2, [r3, #12] DMA2_Stream0->CR |= DMA_SxCR_TCIE; 8000684: 4b09 ldr r3, [pc, #36] @ (80006ac ) 8000686: 681b ldr r3, [r3, #0] 8000688: 4a08 ldr r2, [pc, #32] @ (80006ac ) 800068a: f043 0310 orr.w r3, r3, #16 800068e: 6013 str r3, [r2, #0] } 8000690: bf00 nop 8000692: 46bd mov sp, r7 8000694: f85d 7b04 ldr.w r7, [sp], #4 8000698: 4770 bx lr 800069a: bf00 nop 800069c: 40020058 .word 0x40020058 80006a0: 2400010c .word 0x2400010c 80006a4: 40004828 .word 0x40004828 80006a8: 40020000 .word 0x40020000 80006ac: 40020410 .word 0x40020410 80006b0: 58026040 .word 0x58026040 80006b4: 40020400 .word 0x40020400 080006b8 : void ADC_READ_init(){ 80006b8: b480 push {r7} 80006ba: af00 add r7, sp, #0 // TIM6 conf. TIM6 -> PSC = 6000; // set single timer ticks to 0.25us (240MHz/30 = 4MHz) - 240MHz is APB1 clock freq. 80006bc: 4b21 ldr r3, [pc, #132] @ (8000744 ) 80006be: f241 7270 movw r2, #6000 @ 0x1770 80006c2: 629a str r2, [r3, #40] @ 0x28 TIM6 -> CNT = 0; 80006c4: 4b1f ldr r3, [pc, #124] @ (8000744 ) 80006c6: 2200 movs r2, #0 80006c8: 625a str r2, [r3, #36] @ 0x24 TIM6 -> ARR = 4; // 1/4 us 80006ca: 4b1e ldr r3, [pc, #120] @ (8000744 ) 80006cc: 2204 movs r2, #4 80006ce: 62da str r2, [r3, #44] @ 0x2c // configura canali da leggere in modalità sequenziale ADC3->SQR1 = 0; 80006d0: 4b1d ldr r3, [pc, #116] @ (8000748 ) 80006d2: 2200 movs r2, #0 80006d4: 631a str r2, [r3, #48] @ 0x30 ADC3->SQR1 |= (READ_CH << ADC_SQR1_SQ1_Pos); 80006d6: 4b1c ldr r3, [pc, #112] @ (8000748 ) 80006d8: 6b1b ldr r3, [r3, #48] @ 0x30 80006da: 4a1b ldr r2, [pc, #108] @ (8000748 ) 80006dc: f043 0340 orr.w r3, r3, #64 @ 0x40 80006e0: 6313 str r3, [r2, #48] @ 0x30 // imposta una sola misura (lui misura L+1 canali dove L è il valore impostato in questo reg.) ADC3->SQR1 |= (0 << ADC_SQR1_L_Pos); 80006e2: 4b19 ldr r3, [pc, #100] @ (8000748 ) 80006e4: 4a18 ldr r2, [pc, #96] @ (8000748 ) 80006e6: 6b1b ldr r3, [r3, #48] @ 0x30 80006e8: 6313 str r3, [r2, #48] @ 0x30 // abilita i canali da utilizzare nel multiplexer ADC3->PCSEL |= ADC_PCSEL_PCSEL_1; 80006ea: 4b17 ldr r3, [pc, #92] @ (8000748 ) 80006ec: 69db ldr r3, [r3, #28] 80006ee: 4a16 ldr r2, [pc, #88] @ (8000748 ) 80006f0: f043 0302 orr.w r3, r3, #2 80006f4: 61d3 str r3, [r2, #28] // imposta il tempo di lettura (bigger, better) ADC3->SMPR1 |= (0 << ADC_SMPR1_SMP1_Pos); 80006f6: 4b14 ldr r3, [pc, #80] @ (8000748 ) 80006f8: 4a13 ldr r2, [pc, #76] @ (8000748 ) 80006fa: 695b ldr r3, [r3, #20] 80006fc: 6153 str r3, [r2, #20] // abilita interrupt per fine misura [e messa in funzione (ADRDY abilitato)] ADC3->IER |= ADC_IER_EOSIE; 80006fe: 4b12 ldr r3, [pc, #72] @ (8000748 ) 8000700: 685b ldr r3, [r3, #4] 8000702: 4a11 ldr r2, [pc, #68] @ (8000748 ) 8000704: f043 0308 orr.w r3, r3, #8 8000708: 6053 str r3, [r2, #4] // cont. mode //ADC3->CFGR |= ADC_CFGR_CONT; // abilita DMA sull'ADC ADC3->CFGR |= ADC_CFGR_DMNGT; 800070a: 4b0f ldr r3, [pc, #60] @ (8000748 ) 800070c: 68db ldr r3, [r3, #12] 800070e: 4a0e ldr r2, [pc, #56] @ (8000748 ) 8000710: f043 0303 orr.w r3, r3, #3 8000714: 60d3 str r3, [r2, #12] // ignora overrun //ADC3->CFGR |= ADC_CFGR_OVRMOD; // abilita ADC vera e propria ADC3->ISR |= ADC_ISR_ADRDY; 8000716: 4b0c ldr r3, [pc, #48] @ (8000748 ) 8000718: 681b ldr r3, [r3, #0] 800071a: 4a0b ldr r2, [pc, #44] @ (8000748 ) 800071c: f043 0301 orr.w r3, r3, #1 8000720: 6013 str r3, [r2, #0] ADC3->CR |= ADC_CR_ADEN; 8000722: 4b09 ldr r3, [pc, #36] @ (8000748 ) 8000724: 689b ldr r3, [r3, #8] 8000726: 4a08 ldr r2, [pc, #32] @ (8000748 ) 8000728: f043 0301 orr.w r3, r3, #1 800072c: 6093 str r3, [r2, #8] DMA2_Stream0->CR |= DMA_SxCR_EN; 800072e: 4b07 ldr r3, [pc, #28] @ (800074c ) 8000730: 681b ldr r3, [r3, #0] 8000732: 4a06 ldr r2, [pc, #24] @ (800074c ) 8000734: f043 0301 orr.w r3, r3, #1 8000738: 6013 str r3, [r2, #0] } 800073a: bf00 nop 800073c: 46bd mov sp, r7 800073e: f85d 7b04 ldr.w r7, [sp], #4 8000742: 4770 bx lr 8000744: 40001000 .word 0x40001000 8000748: 58026000 .word 0x58026000 800074c: 40020410 .word 0x40020410 08000750 : uint8_t* to_send; // pointer to a single byte of data vector (i can only send byte by byte) uint16_t length; // lenght of the message to send (in bytes) uint8_t not_ready_msg[] = "NA"; //Zona definizione di funzioni void USART_init(void){ 8000750: b480 push {r7} 8000752: af00 add r7, sp, #0 // abilita rx/tx su USART3 USART3->CR1 |= USART_CR1_RE; 8000754: 4b0e ldr r3, [pc, #56] @ (8000790 ) 8000756: 681b ldr r3, [r3, #0] 8000758: 4a0d ldr r2, [pc, #52] @ (8000790 ) 800075a: f043 0304 orr.w r3, r3, #4 800075e: 6013 str r3, [r2, #0] USART3->CR1 |= USART_CR1_TE; 8000760: 4b0b ldr r3, [pc, #44] @ (8000790 ) 8000762: 681b ldr r3, [r3, #0] 8000764: 4a0a ldr r2, [pc, #40] @ (8000790 ) 8000766: f043 0308 orr.w r3, r3, #8 800076a: 6013 str r3, [r2, #0] // abilita rx/tx interrupts su USART3 USART3->CR1 |= USART_CR1_RXNEIE; 800076c: 4b08 ldr r3, [pc, #32] @ (8000790 ) 800076e: 681b ldr r3, [r3, #0] 8000770: 4a07 ldr r2, [pc, #28] @ (8000790 ) 8000772: f043 0320 orr.w r3, r3, #32 8000776: 6013 str r3, [r2, #0] //USART3->CR1 |= USART_CR1_TCIE; // abilita DMA USART3->CR3 |= USART_CR3_DMAT; 8000778: 4b05 ldr r3, [pc, #20] @ (8000790 ) 800077a: 689b ldr r3, [r3, #8] 800077c: 4a04 ldr r2, [pc, #16] @ (8000790 ) 800077e: f043 0380 orr.w r3, r3, #128 @ 0x80 8000782: 6093 str r3, [r2, #8] } 8000784: bf00 nop 8000786: 46bd mov sp, r7 8000788: f85d 7b04 ldr.w r7, [sp], #4 800078c: 4770 bx lr 800078e: bf00 nop 8000790: 40004800 .word 0x40004800 08000794 : void ESPE_USART_interrupt(void){ 8000794: b480 push {r7} 8000796: af00 add r7, sp, #0 indx = 0; } } */ // logica ricezione if( USART3->ISR & USART_ISR_RXNE_RXFNE){ 8000798: 4b22 ldr r3, [pc, #136] @ (8000824 ) 800079a: 69db ldr r3, [r3, #28] 800079c: f003 0320 and.w r3, r3, #32 80007a0: 2b00 cmp r3, #0 80007a2: d027 beq.n 80007f4 rcv = USART3->RDR; 80007a4: 4b1f ldr r3, [pc, #124] @ (8000824 ) 80007a6: 6a5b ldr r3, [r3, #36] @ 0x24 80007a8: b2da uxtb r2, r3 80007aa: 4b1f ldr r3, [pc, #124] @ (8000828 ) 80007ac: 701a strb r2, [r3, #0] if(rcv == SEND_CHAR){ 80007ae: 4b1e ldr r3, [pc, #120] @ (8000828 ) 80007b0: 781b ldrb r3, [r3, #0] 80007b2: 2b73 cmp r3, #115 @ 0x73 80007b4: d106 bne.n 80007c4 DMA1_Stream3->CR |= DMA_SxCR_EN; 80007b6: 4b1d ldr r3, [pc, #116] @ (800082c ) 80007b8: 681b ldr r3, [r3, #0] 80007ba: 4a1c ldr r2, [pc, #112] @ (800082c ) 80007bc: f043 0301 orr.w r3, r3, #1 80007c0: 6013 str r3, [r2, #0] 80007c2: e017 b.n 80007f4 //KS = 1; //indx ++; //USART3->TDR = to_send[0]; }else if(rcv == ACQUIRE_CHAR){ 80007c4: 4b18 ldr r3, [pc, #96] @ (8000828 ) 80007c6: 781b ldrb r3, [r3, #0] 80007c8: 2b61 cmp r3, #97 @ 0x61 80007ca: d10f bne.n 80007ec // riporta indice DMA a 100 DMA2_Stream0->NDTR = (uint16_t) N_MEAS; 80007cc: 4b18 ldr r3, [pc, #96] @ (8000830 ) 80007ce: 2264 movs r2, #100 @ 0x64 80007d0: 605a str r2, [r3, #4] // inizia la misura di ADC e fai partire timer ADC3-> CR |= ADC_CR_ADSTART; 80007d2: 4b18 ldr r3, [pc, #96] @ (8000834 ) 80007d4: 689b ldr r3, [r3, #8] 80007d6: 4a17 ldr r2, [pc, #92] @ (8000834 ) 80007d8: f043 0304 orr.w r3, r3, #4 80007dc: 6093 str r3, [r2, #8] TIM6-> CR1 |= TIM_CR1_CEN; 80007de: 4b16 ldr r3, [pc, #88] @ (8000838 ) 80007e0: 681b ldr r3, [r3, #0] 80007e2: 4a15 ldr r2, [pc, #84] @ (8000838 ) 80007e4: f043 0301 orr.w r3, r3, #1 80007e8: 6013 str r3, [r2, #0] 80007ea: e003 b.n 80007f4 }else{ USART3->TDR = rcv; 80007ec: 4b0e ldr r3, [pc, #56] @ (8000828 ) 80007ee: 781a ldrb r2, [r3, #0] 80007f0: 4b0c ldr r3, [pc, #48] @ (8000824 ) 80007f2: 629a str r2, [r3, #40] @ 0x28 //KS = 0; } } //Per ovviare a dimenticanze azzeriamo all'uscita i flag della ricezione e trasmissione in ogni caso USART3->ICR |= USART_ICR_ORECF; //Cancella l'overrun. Capita quando si entra in debug 80007f4: 4b0b ldr r3, [pc, #44] @ (8000824 ) 80007f6: 6a1b ldr r3, [r3, #32] 80007f8: 4a0a ldr r2, [pc, #40] @ (8000824 ) 80007fa: f043 0308 orr.w r3, r3, #8 80007fe: 6213 str r3, [r2, #32] USART3->ICR |= USART_ICR_TCCF ; //Azzeramento flag interrupt trasmissione 8000800: 4b08 ldr r3, [pc, #32] @ (8000824 ) 8000802: 6a1b ldr r3, [r3, #32] 8000804: 4a07 ldr r2, [pc, #28] @ (8000824 ) 8000806: f043 0340 orr.w r3, r3, #64 @ 0x40 800080a: 6213 str r3, [r2, #32] USART3->RQR |= USART_RQR_RXFRQ; //Azzeramento flag interrupt ricezione 800080c: 4b05 ldr r3, [pc, #20] @ (8000824 ) 800080e: 699b ldr r3, [r3, #24] 8000810: 4a04 ldr r2, [pc, #16] @ (8000824 ) 8000812: f043 0308 orr.w r3, r3, #8 8000816: 6193 str r3, [r2, #24] } 8000818: bf00 nop 800081a: 46bd mov sp, r7 800081c: f85d 7b04 ldr.w r7, [sp], #4 8000820: 4770 bx lr 8000822: bf00 nop 8000824: 40004800 .word 0x40004800 8000828: 2400002c .word 0x2400002c 800082c: 40020058 .word 0x40020058 8000830: 40020410 .word 0x40020410 8000834: 58026000 .word 0x58026000 8000838: 40001000 .word 0x40001000 0800083c : #include "gpio.h" char stato = 0; char dir = 0; void SEMAPHORE_init(void){ 800083c: b480 push {r7} 800083e: af00 add r7, sp, #0 TIM7 -> ARR = ON_time; 8000840: 4b0f ldr r3, [pc, #60] @ (8000880 ) 8000842: f44f 62fa mov.w r2, #2000 @ 0x7d0 8000846: 62da str r2, [r3, #44] @ 0x2c TIM7 -> PSC = 24000; // set single timer ticks to 100us (240MHz/24000 = 10kHz) - 240MHz is APB1 clock freq. 8000848: 4b0d ldr r3, [pc, #52] @ (8000880 ) 800084a: f645 52c0 movw r2, #24000 @ 0x5dc0 800084e: 629a str r2, [r3, #40] @ 0x28 TIM7 -> CR1 |= TIM_CR1_CEN; 8000850: 4b0b ldr r3, [pc, #44] @ (8000880 ) 8000852: 681b ldr r3, [r3, #0] 8000854: 4a0a ldr r2, [pc, #40] @ (8000880 ) 8000856: f043 0301 orr.w r3, r3, #1 800085a: 6013 str r3, [r2, #0] TIM7 -> CNT = 0; 800085c: 4b08 ldr r3, [pc, #32] @ (8000880 ) 800085e: 2200 movs r2, #0 8000860: 625a str r2, [r3, #36] @ 0x24 TIM7 -> DIER |= TIM_DIER_UIE; 8000862: 4b07 ldr r3, [pc, #28] @ (8000880 ) 8000864: 68db ldr r3, [r3, #12] 8000866: 4a06 ldr r2, [pc, #24] @ (8000880 ) 8000868: f043 0301 orr.w r3, r3, #1 800086c: 60d3 str r3, [r2, #12] //inizia con UNO acceso GPIOB -> BSRR = on_0; 800086e: 4b05 ldr r3, [pc, #20] @ (8000884 ) 8000870: 2201 movs r2, #1 8000872: 619a str r2, [r3, #24] } 8000874: bf00 nop 8000876: 46bd mov sp, r7 8000878: f85d 7b04 ldr.w r7, [sp], #4 800087c: 4770 bx lr 800087e: bf00 nop 8000880: 40001400 .word 0x40001400 8000884: 58020400 .word 0x58020400 08000888 : void SEMAPHORE_TIM7_interrupt(void){ 8000888: b480 push {r7} 800088a: af00 add r7, sp, #0 // spegni tutto GPIOB -> BSRR = off_0; 800088c: 4b28 ldr r3, [pc, #160] @ (8000930 ) 800088e: f44f 3280 mov.w r2, #65536 @ 0x10000 8000892: 619a str r2, [r3, #24] GPIOE -> BSRR = off_1; 8000894: 4b27 ldr r3, [pc, #156] @ (8000934 ) 8000896: f44f 3200 mov.w r2, #131072 @ 0x20000 800089a: 619a str r2, [r3, #24] GPIOB -> BSRR = off_2; 800089c: 4b24 ldr r3, [pc, #144] @ (8000930 ) 800089e: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 80008a2: 619a str r2, [r3, #24] TIM7->SR = 0; 80008a4: 4b24 ldr r3, [pc, #144] @ (8000938 ) 80008a6: 2200 movs r2, #0 80008a8: 611a str r2, [r3, #16] switch(stato){ 80008aa: 4b24 ldr r3, [pc, #144] @ (800093c ) 80008ac: 781b ldrb r3, [r3, #0] 80008ae: 2b02 cmp r3, #2 80008b0: d02e beq.n 8000910 80008b2: 2b02 cmp r3, #2 80008b4: dc37 bgt.n 8000926 80008b6: 2b00 cmp r3, #0 80008b8: d002 beq.n 80008c0 80008ba: 2b01 cmp r3, #1 80008bc: d00b beq.n 80008d6 GPIOE -> BSRR = on_1; stato = 1; TIM7 -> ARR = ON_time; break; } } 80008be: e032 b.n 8000926 GPIOE -> BSRR = on_1; 80008c0: 4b1c ldr r3, [pc, #112] @ (8000934 ) 80008c2: 2202 movs r2, #2 80008c4: 619a str r2, [r3, #24] stato = 1; 80008c6: 4b1d ldr r3, [pc, #116] @ (800093c ) 80008c8: 2201 movs r2, #1 80008ca: 701a strb r2, [r3, #0] TIM7 -> ARR = ON_time; 80008cc: 4b1a ldr r3, [pc, #104] @ (8000938 ) 80008ce: f44f 62fa mov.w r2, #2000 @ 0x7d0 80008d2: 62da str r2, [r3, #44] @ 0x2c break; 80008d4: e027 b.n 8000926 if(!dir){ 80008d6: 4b1a ldr r3, [pc, #104] @ (8000940 ) 80008d8: 781b ldrb r3, [r3, #0] 80008da: 2b00 cmp r3, #0 80008dc: d10a bne.n 80008f4 GPIOB -> BSRR = on_2; 80008de: 4b14 ldr r3, [pc, #80] @ (8000930 ) 80008e0: f44f 4280 mov.w r2, #16384 @ 0x4000 80008e4: 619a str r2, [r3, #24] stato = 2; 80008e6: 4b15 ldr r3, [pc, #84] @ (800093c ) 80008e8: 2202 movs r2, #2 80008ea: 701a strb r2, [r3, #0] dir = 1; 80008ec: 4b14 ldr r3, [pc, #80] @ (8000940 ) 80008ee: 2201 movs r2, #1 80008f0: 701a strb r2, [r3, #0] 80008f2: e008 b.n 8000906 GPIOB -> BSRR = on_0; 80008f4: 4b0e ldr r3, [pc, #56] @ (8000930 ) 80008f6: 2201 movs r2, #1 80008f8: 619a str r2, [r3, #24] stato = 0; 80008fa: 4b10 ldr r3, [pc, #64] @ (800093c ) 80008fc: 2200 movs r2, #0 80008fe: 701a strb r2, [r3, #0] dir = 0; 8000900: 4b0f ldr r3, [pc, #60] @ (8000940 ) 8000902: 2200 movs r2, #0 8000904: 701a strb r2, [r3, #0] TIM7 -> ARR = OFF_time; 8000906: 4b0c ldr r3, [pc, #48] @ (8000938 ) 8000908: f241 3288 movw r2, #5000 @ 0x1388 800090c: 62da str r2, [r3, #44] @ 0x2c break; 800090e: e00a b.n 8000926 GPIOE -> BSRR = on_1; 8000910: 4b08 ldr r3, [pc, #32] @ (8000934 ) 8000912: 2202 movs r2, #2 8000914: 619a str r2, [r3, #24] stato = 1; 8000916: 4b09 ldr r3, [pc, #36] @ (800093c ) 8000918: 2201 movs r2, #1 800091a: 701a strb r2, [r3, #0] TIM7 -> ARR = ON_time; 800091c: 4b06 ldr r3, [pc, #24] @ (8000938 ) 800091e: f44f 62fa mov.w r2, #2000 @ 0x7d0 8000922: 62da str r2, [r3, #44] @ 0x2c break; 8000924: bf00 nop } 8000926: bf00 nop 8000928: 46bd mov sp, r7 800092a: f85d 7b04 ldr.w r7, [sp], #4 800092e: 4770 bx lr 8000930: 58020400 .word 0x58020400 8000934: 58021000 .word 0x58021000 8000938: 40001400 .word 0x40001400 800093c: 2400002d .word 0x2400002d 8000940: 2400002e .word 0x2400002e 08000944 : ADC_HandleTypeDef hadc3; DMA_HandleTypeDef hdma_adc3; /* ADC3 init function */ void MX_ADC3_Init(void) { 8000944: b580 push {r7, lr} 8000946: b088 sub sp, #32 8000948: af00 add r7, sp, #0 /* USER CODE BEGIN ADC3_Init 0 */ /* USER CODE END ADC3_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 800094a: 1d3b adds r3, r7, #4 800094c: 2200 movs r2, #0 800094e: 601a str r2, [r3, #0] 8000950: 605a str r2, [r3, #4] 8000952: 609a str r2, [r3, #8] 8000954: 60da str r2, [r3, #12] 8000956: 611a str r2, [r3, #16] 8000958: 615a str r2, [r3, #20] 800095a: 619a str r2, [r3, #24] /* USER CODE END ADC3_Init 1 */ /** Common config */ hadc3.Instance = ADC3; 800095c: 4b2c ldr r3, [pc, #176] @ (8000a10 ) 800095e: 4a2d ldr r2, [pc, #180] @ (8000a14 ) 8000960: 601a str r2, [r3, #0] hadc3.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV2; 8000962: 4b2b ldr r3, [pc, #172] @ (8000a10 ) 8000964: f44f 2280 mov.w r2, #262144 @ 0x40000 8000968: 605a str r2, [r3, #4] hadc3.Init.Resolution = ADC_RESOLUTION_16B; 800096a: 4b29 ldr r3, [pc, #164] @ (8000a10 ) 800096c: 2200 movs r2, #0 800096e: 609a str r2, [r3, #8] hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE; 8000970: 4b27 ldr r3, [pc, #156] @ (8000a10 ) 8000972: 2200 movs r2, #0 8000974: 60da str r2, [r3, #12] hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 8000976: 4b26 ldr r3, [pc, #152] @ (8000a10 ) 8000978: 2204 movs r2, #4 800097a: 611a str r2, [r3, #16] hadc3.Init.LowPowerAutoWait = DISABLE; 800097c: 4b24 ldr r3, [pc, #144] @ (8000a10 ) 800097e: 2200 movs r2, #0 8000980: 751a strb r2, [r3, #20] hadc3.Init.ContinuousConvMode = DISABLE; 8000982: 4b23 ldr r3, [pc, #140] @ (8000a10 ) 8000984: 2200 movs r2, #0 8000986: 755a strb r2, [r3, #21] hadc3.Init.NbrOfConversion = 1; 8000988: 4b21 ldr r3, [pc, #132] @ (8000a10 ) 800098a: 2201 movs r2, #1 800098c: 619a str r2, [r3, #24] hadc3.Init.DiscontinuousConvMode = DISABLE; 800098e: 4b20 ldr r3, [pc, #128] @ (8000a10 ) 8000990: 2200 movs r2, #0 8000992: 771a strb r2, [r3, #28] hadc3.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T6_TRGO; 8000994: 4b1e ldr r3, [pc, #120] @ (8000a10 ) 8000996: f44f 62b4 mov.w r2, #1440 @ 0x5a0 800099a: 625a str r2, [r3, #36] @ 0x24 hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 800099c: 4b1c ldr r3, [pc, #112] @ (8000a10 ) 800099e: f44f 6280 mov.w r2, #1024 @ 0x400 80009a2: 629a str r2, [r3, #40] @ 0x28 hadc3.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR; 80009a4: 4b1a ldr r3, [pc, #104] @ (8000a10 ) 80009a6: 2200 movs r2, #0 80009a8: 62da str r2, [r3, #44] @ 0x2c hadc3.Init.Overrun = ADC_OVR_DATA_PRESERVED; 80009aa: 4b19 ldr r3, [pc, #100] @ (8000a10 ) 80009ac: 2200 movs r2, #0 80009ae: 631a str r2, [r3, #48] @ 0x30 hadc3.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 80009b0: 4b17 ldr r3, [pc, #92] @ (8000a10 ) 80009b2: 2200 movs r2, #0 80009b4: 635a str r2, [r3, #52] @ 0x34 hadc3.Init.OversamplingMode = DISABLE; 80009b6: 4b16 ldr r3, [pc, #88] @ (8000a10 ) 80009b8: 2200 movs r2, #0 80009ba: f883 2038 strb.w r2, [r3, #56] @ 0x38 hadc3.Init.Oversampling.Ratio = 1; 80009be: 4b14 ldr r3, [pc, #80] @ (8000a10 ) 80009c0: 2201 movs r2, #1 80009c2: 63da str r2, [r3, #60] @ 0x3c if (HAL_ADC_Init(&hadc3) != HAL_OK) 80009c4: 4812 ldr r0, [pc, #72] @ (8000a10 ) 80009c6: f001 f879 bl 8001abc 80009ca: 4603 mov r3, r0 80009cc: 2b00 cmp r3, #0 80009ce: d001 beq.n 80009d4 { Error_Handler(); 80009d0: f000 fa0c bl 8000dec } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; 80009d4: 4b10 ldr r3, [pc, #64] @ (8000a18 ) 80009d6: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 80009d8: 2306 movs r3, #6 80009da: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 80009dc: 2300 movs r3, #0 80009de: 60fb str r3, [r7, #12] sConfig.SingleDiff = ADC_SINGLE_ENDED; 80009e0: f240 73ff movw r3, #2047 @ 0x7ff 80009e4: 613b str r3, [r7, #16] sConfig.OffsetNumber = ADC_OFFSET_NONE; 80009e6: 2304 movs r3, #4 80009e8: 617b str r3, [r7, #20] sConfig.Offset = 0; 80009ea: 2300 movs r3, #0 80009ec: 61bb str r3, [r7, #24] sConfig.OffsetSignedSaturation = DISABLE; 80009ee: 2300 movs r3, #0 80009f0: 777b strb r3, [r7, #29] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 80009f2: 1d3b adds r3, r7, #4 80009f4: 4619 mov r1, r3 80009f6: 4806 ldr r0, [pc, #24] @ (8000a10 ) 80009f8: f001 fa02 bl 8001e00 80009fc: 4603 mov r3, r0 80009fe: 2b00 cmp r3, #0 8000a00: d001 beq.n 8000a06 { Error_Handler(); 8000a02: f000 f9f3 bl 8000dec } /* USER CODE BEGIN ADC3_Init 2 */ /* USER CODE END ADC3_Init 2 */ } 8000a06: bf00 nop 8000a08: 3720 adds r7, #32 8000a0a: 46bd mov sp, r7 8000a0c: bd80 pop {r7, pc} 8000a0e: bf00 nop 8000a10: 24000030 .word 0x24000030 8000a14: 58026000 .word 0x58026000 8000a18: 04300002 .word 0x04300002 08000a1c : void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) { 8000a1c: b580 push {r7, lr} 8000a1e: b084 sub sp, #16 8000a20: af00 add r7, sp, #0 8000a22: 6078 str r0, [r7, #4] if(adcHandle->Instance==ADC3) 8000a24: 687b ldr r3, [r7, #4] 8000a26: 681b ldr r3, [r3, #0] 8000a28: 4a31 ldr r2, [pc, #196] @ (8000af0 ) 8000a2a: 4293 cmp r3, r2 8000a2c: d15c bne.n 8000ae8 { /* USER CODE BEGIN ADC3_MspInit 0 */ /* USER CODE END ADC3_MspInit 0 */ /* ADC3 clock enable */ __HAL_RCC_ADC3_CLK_ENABLE(); 8000a2e: 4b31 ldr r3, [pc, #196] @ (8000af4 ) 8000a30: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000a34: 4a2f ldr r2, [pc, #188] @ (8000af4 ) 8000a36: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8000a3a: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8000a3e: 4b2d ldr r3, [pc, #180] @ (8000af4 ) 8000a40: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000a44: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8000a48: 60fb str r3, [r7, #12] 8000a4a: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOC_CLK_ENABLE(); 8000a4c: 4b29 ldr r3, [pc, #164] @ (8000af4 ) 8000a4e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000a52: 4a28 ldr r2, [pc, #160] @ (8000af4 ) 8000a54: f043 0304 orr.w r3, r3, #4 8000a58: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8000a5c: 4b25 ldr r3, [pc, #148] @ (8000af4 ) 8000a5e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000a62: f003 0304 and.w r3, r3, #4 8000a66: 60bb str r3, [r7, #8] 8000a68: 68bb ldr r3, [r7, #8] /**ADC3 GPIO Configuration PC3_C ------> ADC3_INP1 */ HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC3, SYSCFG_SWITCH_PC3_OPEN); 8000a6a: f04f 6100 mov.w r1, #134217728 @ 0x8000000 8000a6e: f04f 6000 mov.w r0, #134217728 @ 0x8000000 8000a72: f000 fe4f bl 8001714 /* ADC3 DMA Init */ /* ADC3 Init */ hdma_adc3.Instance = DMA2_Stream0; 8000a76: 4b20 ldr r3, [pc, #128] @ (8000af8 ) 8000a78: 4a20 ldr r2, [pc, #128] @ (8000afc ) 8000a7a: 601a str r2, [r3, #0] hdma_adc3.Init.Request = DMA_REQUEST_ADC3; 8000a7c: 4b1e ldr r3, [pc, #120] @ (8000af8 ) 8000a7e: 2273 movs r2, #115 @ 0x73 8000a80: 605a str r2, [r3, #4] hdma_adc3.Init.Direction = DMA_PERIPH_TO_MEMORY; 8000a82: 4b1d ldr r3, [pc, #116] @ (8000af8 ) 8000a84: 2200 movs r2, #0 8000a86: 609a str r2, [r3, #8] hdma_adc3.Init.PeriphInc = DMA_PINC_DISABLE; 8000a88: 4b1b ldr r3, [pc, #108] @ (8000af8 ) 8000a8a: 2200 movs r2, #0 8000a8c: 60da str r2, [r3, #12] hdma_adc3.Init.MemInc = DMA_MINC_ENABLE; 8000a8e: 4b1a ldr r3, [pc, #104] @ (8000af8 ) 8000a90: f44f 6280 mov.w r2, #1024 @ 0x400 8000a94: 611a str r2, [r3, #16] hdma_adc3.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8000a96: 4b18 ldr r3, [pc, #96] @ (8000af8 ) 8000a98: f44f 6200 mov.w r2, #2048 @ 0x800 8000a9c: 615a str r2, [r3, #20] hdma_adc3.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8000a9e: 4b16 ldr r3, [pc, #88] @ (8000af8 ) 8000aa0: f44f 5200 mov.w r2, #8192 @ 0x2000 8000aa4: 619a str r2, [r3, #24] hdma_adc3.Init.Mode = DMA_CIRCULAR; 8000aa6: 4b14 ldr r3, [pc, #80] @ (8000af8 ) 8000aa8: f44f 7280 mov.w r2, #256 @ 0x100 8000aac: 61da str r2, [r3, #28] hdma_adc3.Init.Priority = DMA_PRIORITY_MEDIUM; 8000aae: 4b12 ldr r3, [pc, #72] @ (8000af8 ) 8000ab0: f44f 3280 mov.w r2, #65536 @ 0x10000 8000ab4: 621a str r2, [r3, #32] hdma_adc3.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8000ab6: 4b10 ldr r3, [pc, #64] @ (8000af8 ) 8000ab8: 2200 movs r2, #0 8000aba: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc3) != HAL_OK) 8000abc: 480e ldr r0, [pc, #56] @ (8000af8 ) 8000abe: f001 feab bl 8002818 8000ac2: 4603 mov r3, r0 8000ac4: 2b00 cmp r3, #0 8000ac6: d001 beq.n 8000acc { Error_Handler(); 8000ac8: f000 f990 bl 8000dec } __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc3); 8000acc: 687b ldr r3, [r7, #4] 8000ace: 4a0a ldr r2, [pc, #40] @ (8000af8 ) 8000ad0: 64da str r2, [r3, #76] @ 0x4c 8000ad2: 4a09 ldr r2, [pc, #36] @ (8000af8 ) 8000ad4: 687b ldr r3, [r7, #4] 8000ad6: 6393 str r3, [r2, #56] @ 0x38 /* ADC3 interrupt Init */ HAL_NVIC_SetPriority(ADC3_IRQn, 0, 0); 8000ad8: 2200 movs r2, #0 8000ada: 2100 movs r1, #0 8000adc: 207f movs r0, #127 @ 0x7f 8000ade: f001 fe66 bl 80027ae HAL_NVIC_EnableIRQ(ADC3_IRQn); 8000ae2: 207f movs r0, #127 @ 0x7f 8000ae4: f001 fe7d bl 80027e2 /* USER CODE BEGIN ADC3_MspInit 1 */ /* USER CODE END ADC3_MspInit 1 */ } } 8000ae8: bf00 nop 8000aea: 3710 adds r7, #16 8000aec: 46bd mov sp, r7 8000aee: bd80 pop {r7, pc} 8000af0: 58026000 .word 0x58026000 8000af4: 58024400 .word 0x58024400 8000af8: 24000094 .word 0x24000094 8000afc: 40020410 .word 0x40020410 08000b00 : /** * Enable DMA controller clock */ void MX_DMA_Init(void) { 8000b00: b580 push {r7, lr} 8000b02: b082 sub sp, #8 8000b04: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA2_CLK_ENABLE(); 8000b06: 4b19 ldr r3, [pc, #100] @ (8000b6c ) 8000b08: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8000b0c: 4a17 ldr r2, [pc, #92] @ (8000b6c ) 8000b0e: f043 0302 orr.w r3, r3, #2 8000b12: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 8000b16: 4b15 ldr r3, [pc, #84] @ (8000b6c ) 8000b18: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8000b1c: f003 0302 and.w r3, r3, #2 8000b20: 607b str r3, [r7, #4] 8000b22: 687b ldr r3, [r7, #4] __HAL_RCC_DMA1_CLK_ENABLE(); 8000b24: 4b11 ldr r3, [pc, #68] @ (8000b6c ) 8000b26: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8000b2a: 4a10 ldr r2, [pc, #64] @ (8000b6c ) 8000b2c: f043 0301 orr.w r3, r3, #1 8000b30: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 8000b34: 4b0d ldr r3, [pc, #52] @ (8000b6c ) 8000b36: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8000b3a: f003 0301 and.w r3, r3, #1 8000b3e: 603b str r3, [r7, #0] 8000b40: 683b ldr r3, [r7, #0] /* DMA interrupt init */ /* DMA1_Stream3_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream3_IRQn, 0, 0); 8000b42: 2200 movs r2, #0 8000b44: 2100 movs r1, #0 8000b46: 200e movs r0, #14 8000b48: f001 fe31 bl 80027ae HAL_NVIC_EnableIRQ(DMA1_Stream3_IRQn); 8000b4c: 200e movs r0, #14 8000b4e: f001 fe48 bl 80027e2 /* DMA2_Stream0_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 0, 0); 8000b52: 2200 movs r2, #0 8000b54: 2100 movs r1, #0 8000b56: 2038 movs r0, #56 @ 0x38 8000b58: f001 fe29 bl 80027ae HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); 8000b5c: 2038 movs r0, #56 @ 0x38 8000b5e: f001 fe40 bl 80027e2 } 8000b62: bf00 nop 8000b64: 3708 adds r7, #8 8000b66: 46bd mov sp, r7 8000b68: bd80 pop {r7, pc} 8000b6a: bf00 nop 8000b6c: 58024400 .word 0x58024400 08000b70 : PG11 ------> ETH_TX_EN PG13 ------> ETH_TXD0 PB3 (JTDO/TRACESWO) ------> DEBUG_JTDO-SWO */ void MX_GPIO_Init(void) { 8000b70: b580 push {r7, lr} 8000b72: b08c sub sp, #48 @ 0x30 8000b74: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000b76: f107 031c add.w r3, r7, #28 8000b7a: 2200 movs r2, #0 8000b7c: 601a str r2, [r3, #0] 8000b7e: 605a str r2, [r3, #4] 8000b80: 609a str r2, [r3, #8] 8000b82: 60da str r2, [r3, #12] 8000b84: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 8000b86: 4b92 ldr r3, [pc, #584] @ (8000dd0 ) 8000b88: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000b8c: 4a90 ldr r2, [pc, #576] @ (8000dd0 ) 8000b8e: f043 0304 orr.w r3, r3, #4 8000b92: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8000b96: 4b8e ldr r3, [pc, #568] @ (8000dd0 ) 8000b98: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000b9c: f003 0304 and.w r3, r3, #4 8000ba0: 61bb str r3, [r7, #24] 8000ba2: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOH_CLK_ENABLE(); 8000ba4: 4b8a ldr r3, [pc, #552] @ (8000dd0 ) 8000ba6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000baa: 4a89 ldr r2, [pc, #548] @ (8000dd0 ) 8000bac: f043 0380 orr.w r3, r3, #128 @ 0x80 8000bb0: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8000bb4: 4b86 ldr r3, [pc, #536] @ (8000dd0 ) 8000bb6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000bba: f003 0380 and.w r3, r3, #128 @ 0x80 8000bbe: 617b str r3, [r7, #20] 8000bc0: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000bc2: 4b83 ldr r3, [pc, #524] @ (8000dd0 ) 8000bc4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000bc8: 4a81 ldr r2, [pc, #516] @ (8000dd0 ) 8000bca: f043 0301 orr.w r3, r3, #1 8000bce: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8000bd2: 4b7f ldr r3, [pc, #508] @ (8000dd0 ) 8000bd4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000bd8: f003 0301 and.w r3, r3, #1 8000bdc: 613b str r3, [r7, #16] 8000bde: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000be0: 4b7b ldr r3, [pc, #492] @ (8000dd0 ) 8000be2: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000be6: 4a7a ldr r2, [pc, #488] @ (8000dd0 ) 8000be8: f043 0302 orr.w r3, r3, #2 8000bec: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8000bf0: 4b77 ldr r3, [pc, #476] @ (8000dd0 ) 8000bf2: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000bf6: f003 0302 and.w r3, r3, #2 8000bfa: 60fb str r3, [r7, #12] 8000bfc: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOD_CLK_ENABLE(); 8000bfe: 4b74 ldr r3, [pc, #464] @ (8000dd0 ) 8000c00: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000c04: 4a72 ldr r2, [pc, #456] @ (8000dd0 ) 8000c06: f043 0308 orr.w r3, r3, #8 8000c0a: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8000c0e: 4b70 ldr r3, [pc, #448] @ (8000dd0 ) 8000c10: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000c14: f003 0308 and.w r3, r3, #8 8000c18: 60bb str r3, [r7, #8] 8000c1a: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOG_CLK_ENABLE(); 8000c1c: 4b6c ldr r3, [pc, #432] @ (8000dd0 ) 8000c1e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000c22: 4a6b ldr r2, [pc, #428] @ (8000dd0 ) 8000c24: f043 0340 orr.w r3, r3, #64 @ 0x40 8000c28: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8000c2c: 4b68 ldr r3, [pc, #416] @ (8000dd0 ) 8000c2e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000c32: f003 0340 and.w r3, r3, #64 @ 0x40 8000c36: 607b str r3, [r7, #4] 8000c38: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOE_CLK_ENABLE(); 8000c3a: 4b65 ldr r3, [pc, #404] @ (8000dd0 ) 8000c3c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000c40: 4a63 ldr r2, [pc, #396] @ (8000dd0 ) 8000c42: f043 0310 orr.w r3, r3, #16 8000c46: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8000c4a: 4b61 ldr r3, [pc, #388] @ (8000dd0 ) 8000c4c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000c50: f003 0310 and.w r3, r3, #16 8000c54: 603b str r3, [r7, #0] 8000c56: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, LD1_Pin|LD3_Pin, GPIO_PIN_RESET); 8000c58: 2200 movs r2, #0 8000c5a: f244 0101 movw r1, #16385 @ 0x4001 8000c5e: 485d ldr r0, [pc, #372] @ (8000dd4 ) 8000c60: f004 f9b0 bl 8004fc4 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(USB_OTG_FS_PWR_EN_GPIO_Port, USB_OTG_FS_PWR_EN_Pin, GPIO_PIN_RESET); 8000c64: 2200 movs r2, #0 8000c66: f44f 6180 mov.w r1, #1024 @ 0x400 8000c6a: 485b ldr r0, [pc, #364] @ (8000dd8 ) 8000c6c: f004 f9aa bl 8004fc4 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET); 8000c70: 2200 movs r2, #0 8000c72: 2102 movs r1, #2 8000c74: 4859 ldr r0, [pc, #356] @ (8000ddc ) 8000c76: f004 f9a5 bl 8004fc4 /*Configure GPIO pin : B1_Pin */ GPIO_InitStruct.Pin = B1_Pin; 8000c7a: f44f 5300 mov.w r3, #8192 @ 0x2000 8000c7e: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000c80: 2300 movs r3, #0 8000c82: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000c84: 2300 movs r3, #0 8000c86: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); 8000c88: f107 031c add.w r3, r7, #28 8000c8c: 4619 mov r1, r3 8000c8e: 4854 ldr r0, [pc, #336] @ (8000de0 ) 8000c90: f003 ffe8 bl 8004c64 /*Configure GPIO pins : PC1 PC4 PC5 */ GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; 8000c94: 2332 movs r3, #50 @ 0x32 8000c96: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000c98: 2302 movs r3, #2 8000c9a: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000c9c: 2300 movs r3, #0 8000c9e: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000ca0: 2300 movs r3, #0 8000ca2: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Alternate = GPIO_AF11_ETH; 8000ca4: 230b movs r3, #11 8000ca6: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8000ca8: f107 031c add.w r3, r7, #28 8000cac: 4619 mov r1, r3 8000cae: 484c ldr r0, [pc, #304] @ (8000de0 ) 8000cb0: f003 ffd8 bl 8004c64 /*Configure GPIO pins : PA1 PA2 PA7 */ GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7; 8000cb4: 2386 movs r3, #134 @ 0x86 8000cb6: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000cb8: 2302 movs r3, #2 8000cba: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000cbc: 2300 movs r3, #0 8000cbe: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000cc0: 2300 movs r3, #0 8000cc2: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Alternate = GPIO_AF11_ETH; 8000cc4: 230b movs r3, #11 8000cc6: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000cc8: f107 031c add.w r3, r7, #28 8000ccc: 4619 mov r1, r3 8000cce: 4845 ldr r0, [pc, #276] @ (8000de4 ) 8000cd0: f003 ffc8 bl 8004c64 /*Configure GPIO pins : LD1_Pin LD3_Pin */ GPIO_InitStruct.Pin = LD1_Pin|LD3_Pin; 8000cd4: f244 0301 movw r3, #16385 @ 0x4001 8000cd8: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000cda: 2301 movs r3, #1 8000cdc: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000cde: 2300 movs r3, #0 8000ce0: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000ce2: 2300 movs r3, #0 8000ce4: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000ce6: f107 031c add.w r3, r7, #28 8000cea: 4619 mov r1, r3 8000cec: 4839 ldr r0, [pc, #228] @ (8000dd4 ) 8000cee: f003 ffb9 bl 8004c64 /*Configure GPIO pin : PB13 */ GPIO_InitStruct.Pin = GPIO_PIN_13; 8000cf2: f44f 5300 mov.w r3, #8192 @ 0x2000 8000cf6: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000cf8: 2302 movs r3, #2 8000cfa: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000cfc: 2300 movs r3, #0 8000cfe: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000d00: 2300 movs r3, #0 8000d02: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Alternate = GPIO_AF11_ETH; 8000d04: 230b movs r3, #11 8000d06: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000d08: f107 031c add.w r3, r7, #28 8000d0c: 4619 mov r1, r3 8000d0e: 4831 ldr r0, [pc, #196] @ (8000dd4 ) 8000d10: f003 ffa8 bl 8004c64 /*Configure GPIO pin : USB_OTG_FS_PWR_EN_Pin */ GPIO_InitStruct.Pin = USB_OTG_FS_PWR_EN_Pin; 8000d14: f44f 6380 mov.w r3, #1024 @ 0x400 8000d18: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000d1a: 2301 movs r3, #1 8000d1c: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000d1e: 2300 movs r3, #0 8000d20: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000d22: 2300 movs r3, #0 8000d24: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(USB_OTG_FS_PWR_EN_GPIO_Port, &GPIO_InitStruct); 8000d26: f107 031c add.w r3, r7, #28 8000d2a: 4619 mov r1, r3 8000d2c: 482a ldr r0, [pc, #168] @ (8000dd8 ) 8000d2e: f003 ff99 bl 8004c64 /*Configure GPIO pin : PD11 */ GPIO_InitStruct.Pin = GPIO_PIN_11; 8000d32: f44f 6300 mov.w r3, #2048 @ 0x800 8000d36: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; 8000d38: f44f 1388 mov.w r3, #1114112 @ 0x110000 8000d3c: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000d3e: 2300 movs r3, #0 8000d40: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8000d42: f107 031c add.w r3, r7, #28 8000d46: 4619 mov r1, r3 8000d48: 4823 ldr r0, [pc, #140] @ (8000dd8 ) 8000d4a: f003 ff8b bl 8004c64 /*Configure GPIO pin : USB_OTG_FS_OVCR_Pin */ GPIO_InitStruct.Pin = USB_OTG_FS_OVCR_Pin; 8000d4e: 2380 movs r3, #128 @ 0x80 8000d50: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; 8000d52: f44f 1388 mov.w r3, #1114112 @ 0x110000 8000d56: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000d58: 2300 movs r3, #0 8000d5a: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(USB_OTG_FS_OVCR_GPIO_Port, &GPIO_InitStruct); 8000d5c: f107 031c add.w r3, r7, #28 8000d60: 4619 mov r1, r3 8000d62: 4821 ldr r0, [pc, #132] @ (8000de8 ) 8000d64: f003 ff7e bl 8004c64 /*Configure GPIO pins : PA8 PA11 PA12 */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_11|GPIO_PIN_12; 8000d68: f44f 53c8 mov.w r3, #6400 @ 0x1900 8000d6c: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000d6e: 2302 movs r3, #2 8000d70: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000d72: 2300 movs r3, #0 8000d74: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000d76: 2300 movs r3, #0 8000d78: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS; 8000d7a: 230a movs r3, #10 8000d7c: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000d7e: f107 031c add.w r3, r7, #28 8000d82: 4619 mov r1, r3 8000d84: 4817 ldr r0, [pc, #92] @ (8000de4 ) 8000d86: f003 ff6d bl 8004c64 /*Configure GPIO pins : PG11 PG13 */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_13; 8000d8a: f44f 5320 mov.w r3, #10240 @ 0x2800 8000d8e: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000d90: 2302 movs r3, #2 8000d92: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000d94: 2300 movs r3, #0 8000d96: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000d98: 2300 movs r3, #0 8000d9a: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Alternate = GPIO_AF11_ETH; 8000d9c: 230b movs r3, #11 8000d9e: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 8000da0: f107 031c add.w r3, r7, #28 8000da4: 4619 mov r1, r3 8000da6: 4810 ldr r0, [pc, #64] @ (8000de8 ) 8000da8: f003 ff5c bl 8004c64 /*Configure GPIO pin : LD2_Pin */ GPIO_InitStruct.Pin = LD2_Pin; 8000dac: 2302 movs r3, #2 8000dae: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000db0: 2301 movs r3, #1 8000db2: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000db4: 2300 movs r3, #0 8000db6: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000db8: 2300 movs r3, #0 8000dba: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct); 8000dbc: f107 031c add.w r3, r7, #28 8000dc0: 4619 mov r1, r3 8000dc2: 4806 ldr r0, [pc, #24] @ (8000ddc ) 8000dc4: f003 ff4e bl 8004c64 } 8000dc8: bf00 nop 8000dca: 3730 adds r7, #48 @ 0x30 8000dcc: 46bd mov sp, r7 8000dce: bd80 pop {r7, pc} 8000dd0: 58024400 .word 0x58024400 8000dd4: 58020400 .word 0x58020400 8000dd8: 58020c00 .word 0x58020c00 8000ddc: 58021000 .word 0x58021000 8000de0: 58020800 .word 0x58020800 8000de4: 58020000 .word 0x58020000 8000de8: 58021800 .word 0x58021800 08000dec : \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000dec: b672 cpsid i void Error_Handler(void) { /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000dee: e7fe b.n 8000dee 08000df0 : { 8000df0: b500 push {lr} 8000df2: b09d sub sp, #116 @ 0x74 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000df4: 224c movs r2, #76 @ 0x4c 8000df6: 2100 movs r1, #0 8000df8: a809 add r0, sp, #36 @ 0x24 8000dfa: f009 fe23 bl 800aa44 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000dfe: 2220 movs r2, #32 8000e00: 2100 movs r1, #0 8000e02: a801 add r0, sp, #4 8000e04: f009 fe1e bl 800aa44 HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); 8000e08: 2002 movs r0, #2 8000e0a: f004 f8f5 bl 8004ff8 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); 8000e0e: 2300 movs r3, #0 8000e10: 9300 str r3, [sp, #0] 8000e12: 4b26 ldr r3, [pc, #152] @ (8000eac ) 8000e14: 699a ldr r2, [r3, #24] 8000e16: f442 4240 orr.w r2, r2, #49152 @ 0xc000 8000e1a: 619a str r2, [r3, #24] 8000e1c: 699b ldr r3, [r3, #24] 8000e1e: f403 4340 and.w r3, r3, #49152 @ 0xc000 8000e22: 9300 str r3, [sp, #0] 8000e24: 4b22 ldr r3, [pc, #136] @ (8000eb0 ) 8000e26: 6ada ldr r2, [r3, #44] @ 0x2c 8000e28: f042 0201 orr.w r2, r2, #1 8000e2c: 62da str r2, [r3, #44] @ 0x2c 8000e2e: 6adb ldr r3, [r3, #44] @ 0x2c 8000e30: f003 0301 and.w r3, r3, #1 8000e34: 9300 str r3, [sp, #0] 8000e36: 9b00 ldr r3, [sp, #0] while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 8000e38: 4b1c ldr r3, [pc, #112] @ (8000eac ) 8000e3a: 699b ldr r3, [r3, #24] 8000e3c: f413 5f00 tst.w r3, #8192 @ 0x2000 8000e40: d0fa beq.n 8000e38 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8000e42: 2201 movs r2, #1 8000e44: 9209 str r2, [sp, #36] @ 0x24 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; 8000e46: f44f 23a0 mov.w r3, #327680 @ 0x50000 8000e4a: 930a str r3, [sp, #40] @ 0x28 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000e4c: 2302 movs r3, #2 8000e4e: 9312 str r3, [sp, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8000e50: 9313 str r3, [sp, #76] @ 0x4c RCC_OscInitStruct.PLL.PLLM = 1; 8000e52: 9214 str r2, [sp, #80] @ 0x50 RCC_OscInitStruct.PLL.PLLN = 120; 8000e54: 2278 movs r2, #120 @ 0x78 8000e56: 9215 str r2, [sp, #84] @ 0x54 RCC_OscInitStruct.PLL.PLLP = 2; 8000e58: 9316 str r3, [sp, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLQ = 4; 8000e5a: 2204 movs r2, #4 8000e5c: 9217 str r2, [sp, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLR = 2; 8000e5e: 9318 str r3, [sp, #96] @ 0x60 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; 8000e60: 230c movs r3, #12 8000e62: 9319 str r3, [sp, #100] @ 0x64 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 8000e64: 2300 movs r3, #0 8000e66: 931a str r3, [sp, #104] @ 0x68 RCC_OscInitStruct.PLL.PLLFRACN = 0; 8000e68: 931b str r3, [sp, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000e6a: a809 add r0, sp, #36 @ 0x24 8000e6c: f004 f8fe bl 800506c 8000e70: b9b8 cbnz r0, 8000ea2 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000e72: 233f movs r3, #63 @ 0x3f 8000e74: 9301 str r3, [sp, #4] RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000e76: 2303 movs r3, #3 8000e78: 9302 str r3, [sp, #8] RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 8000e7a: 2300 movs r3, #0 8000e7c: 9303 str r3, [sp, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; 8000e7e: 2308 movs r3, #8 8000e80: 9304 str r3, [sp, #16] RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 8000e82: 2340 movs r3, #64 @ 0x40 8000e84: 9305 str r3, [sp, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 8000e86: 9306 str r3, [sp, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 8000e88: f44f 6280 mov.w r2, #1024 @ 0x400 8000e8c: 9207 str r2, [sp, #28] RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 8000e8e: 9308 str r3, [sp, #32] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) 8000e90: 2104 movs r1, #4 8000e92: eb0d 0001 add.w r0, sp, r1 8000e96: f004 fd43 bl 8005920 8000e9a: b920 cbnz r0, 8000ea6 } 8000e9c: b01d add sp, #116 @ 0x74 8000e9e: f85d fb04 ldr.w pc, [sp], #4 Error_Handler(); 8000ea2: f7ff ffa3 bl 8000dec Error_Handler(); 8000ea6: f7ff ffa1 bl 8000dec 8000eaa: bf00 nop 8000eac: 58024800 .word 0x58024800 8000eb0: 58000400 .word 0x58000400 08000eb4 : { 8000eb4: b500 push {lr} 8000eb6: b0b1 sub sp, #196 @ 0xc4 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8000eb8: 22c0 movs r2, #192 @ 0xc0 8000eba: 2100 movs r1, #0 8000ebc: 4668 mov r0, sp 8000ebe: f009 fdc1 bl 800aa44 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC|RCC_PERIPHCLK_USART3; 8000ec2: 4a0c ldr r2, [pc, #48] @ (8000ef4 ) 8000ec4: 2300 movs r3, #0 8000ec6: e9cd 2300 strd r2, r3, [sp] PeriphClkInitStruct.PLL2.PLL2M = 8; 8000eca: 2308 movs r3, #8 8000ecc: 9302 str r3, [sp, #8] PeriphClkInitStruct.PLL2.PLL2N = 150; 8000ece: 2396 movs r3, #150 @ 0x96 8000ed0: 9303 str r3, [sp, #12] PeriphClkInitStruct.PLL2.PLL2P = 2; 8000ed2: 2302 movs r3, #2 8000ed4: 9304 str r3, [sp, #16] PeriphClkInitStruct.PLL2.PLL2Q = 2; 8000ed6: 9305 str r3, [sp, #20] PeriphClkInitStruct.PLL2.PLL2R = 2; 8000ed8: 9306 str r3, [sp, #24] PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOMEDIUM; 8000eda: 2320 movs r3, #32 8000edc: 9308 str r3, [sp, #32] PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_PLL2; 8000ede: 2301 movs r3, #1 8000ee0: 931e str r3, [sp, #120] @ 0x78 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8000ee2: 4668 mov r0, sp 8000ee4: f005 f8a8 bl 8006038 8000ee8: b910 cbnz r0, 8000ef0 } 8000eea: b031 add sp, #196 @ 0xc4 8000eec: f85d fb04 ldr.w pc, [sp], #4 Error_Handler(); 8000ef0: f7ff ff7c bl 8000dec 8000ef4: 00080002 .word 0x00080002 08000ef8
: { 8000ef8: b508 push {r3, lr} HAL_Init(); 8000efa: f000 fb6d bl 80015d8 SystemClock_Config(); 8000efe: f7ff ff77 bl 8000df0 PeriphCommonClock_Config(); 8000f02: f7ff ffd7 bl 8000eb4 MX_GPIO_Init(); 8000f06: f7ff fe33 bl 8000b70 MX_DMA_Init(); 8000f0a: f7ff fdf9 bl 8000b00 MX_USART3_UART_Init(); 8000f0e: f000 fa69 bl 80013e4 MX_TIM6_Init(); 8000f12: f000 f9b3 bl 800127c MX_ADC3_Init(); 8000f16: f7ff fd15 bl 8000944 MX_TIM7_Init(); 8000f1a: f000 f9e5 bl 80012e8 ADC_calibrate(); 8000f1e: f7ff fb71 bl 8000604 while(ADC3->CR & ADC_CR_ADCAL){} 8000f22: 4b06 ldr r3, [pc, #24] @ (8000f3c ) 8000f24: 689b ldr r3, [r3, #8] 8000f26: 2b00 cmp r3, #0 8000f28: dbfb blt.n 8000f22 DMA_init(); 8000f2a: f7ff fb81 bl 8000630 ADC_READ_init(); 8000f2e: f7ff fbc3 bl 80006b8 SEMAPHORE_init(); 8000f32: f7ff fc83 bl 800083c USART_init(); 8000f36: f7ff fc0b bl 8000750 while (1){ 8000f3a: e7fe b.n 8000f3a 8000f3c: 58026000 .word 0x58026000 08000f40 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000f40: b480 push {r7} 8000f42: b083 sub sp, #12 8000f44: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000f46: 4b0a ldr r3, [pc, #40] @ (8000f70 ) 8000f48: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8000f4c: 4a08 ldr r2, [pc, #32] @ (8000f70 ) 8000f4e: f043 0302 orr.w r3, r3, #2 8000f52: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 8000f56: 4b06 ldr r3, [pc, #24] @ (8000f70 ) 8000f58: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8000f5c: f003 0302 and.w r3, r3, #2 8000f60: 607b str r3, [r7, #4] 8000f62: 687b ldr r3, [r7, #4] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000f64: bf00 nop 8000f66: 370c adds r7, #12 8000f68: 46bd mov sp, r7 8000f6a: f85d 7b04 ldr.w r7, [sp], #4 8000f6e: 4770 bx lr 8000f70: 58024400 .word 0x58024400 08000f74 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8000f74: b480 push {r7} 8000f76: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000f78: bf00 nop 8000f7a: e7fd b.n 8000f78 08000f7c : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8000f7c: b480 push {r7} 8000f7e: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8000f80: bf00 nop 8000f82: e7fd b.n 8000f80 08000f84 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8000f84: b480 push {r7} 8000f86: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8000f88: bf00 nop 8000f8a: e7fd b.n 8000f88 08000f8c : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8000f8c: b480 push {r7} 8000f8e: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8000f90: bf00 nop 8000f92: e7fd b.n 8000f90 08000f94 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8000f94: b480 push {r7} 8000f96: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8000f98: bf00 nop 8000f9a: e7fd b.n 8000f98 08000f9c : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000f9c: b480 push {r7} 8000f9e: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8000fa0: bf00 nop 8000fa2: 46bd mov sp, r7 8000fa4: f85d 7b04 ldr.w r7, [sp], #4 8000fa8: 4770 bx lr 08000faa : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8000faa: b480 push {r7} 8000fac: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8000fae: bf00 nop 8000fb0: 46bd mov sp, r7 8000fb2: f85d 7b04 ldr.w r7, [sp], #4 8000fb6: 4770 bx lr 08000fb8 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8000fb8: b480 push {r7} 8000fba: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8000fbc: bf00 nop 8000fbe: 46bd mov sp, r7 8000fc0: f85d 7b04 ldr.w r7, [sp], #4 8000fc4: 4770 bx lr 08000fc6 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8000fc6: b580 push {r7, lr} 8000fc8: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8000fca: f000 fb77 bl 80016bc /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8000fce: bf00 nop 8000fd0: bd80 pop {r7, pc} ... 08000fd4 : /** * @brief This function handles DMA1 stream3 global interrupt. */ void DMA1_Stream3_IRQHandler(void) { 8000fd4: b580 push {r7, lr} 8000fd6: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream3_IRQn 0 */ DMA1_Stream3->NDTR = (uint16_t) (N_MEAS+1)*2; // send signle bytes (+ begin position) 8000fd8: 4b07 ldr r3, [pc, #28] @ (8000ff8 ) 8000fda: 22ca movs r2, #202 @ 0xca 8000fdc: 605a str r2, [r3, #4] DMA1->LIFCR = 0xffffffff; 8000fde: 4b07 ldr r3, [pc, #28] @ (8000ffc ) 8000fe0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8000fe4: 609a str r2, [r3, #8] DMA1->HIFCR = 0xffffffff; 8000fe6: 4b05 ldr r3, [pc, #20] @ (8000ffc ) 8000fe8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8000fec: 60da str r2, [r3, #12] /* USER CODE END DMA1_Stream3_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart3_tx); 8000fee: 4804 ldr r0, [pc, #16] @ (8001000 ) 8000ff0: f002 fcd2 bl 8003998 /* USER CODE BEGIN DMA1_Stream3_IRQn 1 */ // empty results array for the next run /* USER CODE END DMA1_Stream3_IRQn 1 */ } 8000ff4: bf00 nop 8000ff6: bd80 pop {r7, pc} 8000ff8: 40020058 .word 0x40020058 8000ffc: 40020000 .word 0x40020000 8001000: 2400030c .word 0x2400030c 08001004 : /** * @brief This function handles USART3 global interrupt. */ void USART3_IRQHandler(void) { 8001004: b580 push {r7, lr} 8001006: af00 add r7, sp, #0 /* USER CODE BEGIN USART3_IRQn 0 */ ESPE_USART_interrupt(); 8001008: f7ff fbc4 bl 8000794 /* USER CODE END USART3_IRQn 0 */ HAL_UART_IRQHandler(&huart3); 800100c: 4802 ldr r0, [pc, #8] @ (8001018 ) 800100e: f008 f83d bl 800908c /* USER CODE BEGIN USART3_IRQn 1 */ /* USER CODE END USART3_IRQn 1 */ } 8001012: bf00 nop 8001014: bd80 pop {r7, pc} 8001016: bf00 nop 8001018: 24000278 .word 0x24000278 0800101c : /** * @brief This function handles TIM6 global interrupt, DAC1_CH1 and DAC1_CH2 underrun error interrupts. */ void TIM6_DAC_IRQHandler(void) { 800101c: b580 push {r7, lr} 800101e: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ /* USER CODE END TIM6_DAC_IRQn 0 */ HAL_TIM_IRQHandler(&htim6); 8001020: 4802 ldr r0, [pc, #8] @ (800102c ) 8001022: f007 fd5e bl 8008ae2 /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ /* USER CODE END TIM6_DAC_IRQn 1 */ } 8001026: bf00 nop 8001028: bd80 pop {r7, pc} 800102a: bf00 nop 800102c: 240001e0 .word 0x240001e0 08001030 : /** * @brief This function handles TIM7 global interrupt. */ void TIM7_IRQHandler(void) { 8001030: b580 push {r7, lr} 8001032: af00 add r7, sp, #0 /* USER CODE BEGIN TIM7_IRQn 0 */ SEMAPHORE_TIM7_interrupt(); 8001034: f7ff fc28 bl 8000888 /* USER CODE END TIM7_IRQn 0 */ HAL_TIM_IRQHandler(&htim7); 8001038: 4802 ldr r0, [pc, #8] @ (8001044 ) 800103a: f007 fd52 bl 8008ae2 /* USER CODE BEGIN TIM7_IRQn 1 */ /* USER CODE END TIM7_IRQn 1 */ } 800103e: bf00 nop 8001040: bd80 pop {r7, pc} 8001042: bf00 nop 8001044: 2400022c .word 0x2400022c 08001048 : /** * @brief This function handles DMA2 stream0 global interrupt. */ void DMA2_Stream0_IRQHandler(void) { 8001048: b480 push {r7} 800104a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Stream0_IRQn 0 */ // reset DMA to inital state //DMA2_Stream0->NDTR |= (uint16_t) N_MEAS; FULL = 1; 800104c: 4b07 ldr r3, [pc, #28] @ (800106c ) 800104e: 2201 movs r2, #1 8001050: 701a strb r2, [r3, #0] DMA2->LIFCR = 0xffffffff; 8001052: 4b07 ldr r3, [pc, #28] @ (8001070 ) 8001054: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8001058: 609a str r2, [r3, #8] DMA2->HIFCR = 0xffffffff; 800105a: 4b05 ldr r3, [pc, #20] @ (8001070 ) 800105c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8001060: 60da str r2, [r3, #12] /* USER CODE END DMA2_Stream0_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc3); /* USER CODE BEGIN DMA2_Stream0_IRQn 1 */ } /* USER CODE END DMA2_Stream0_IRQn 1 */ } 8001062: bf00 nop 8001064: 46bd mov sp, r7 8001066: f85d 7b04 ldr.w r7, [sp], #4 800106a: 4770 bx lr 800106c: 240001d9 .word 0x240001d9 8001070: 40020400 .word 0x40020400 08001074 : /** * @brief This function handles ADC3 global interrupt. */ void ADC3_IRQHandler(void) { 8001074: b480 push {r7} 8001076: af00 add r7, sp, #0 /* USER CODE BEGIN ADC3_IRQn 0 */ // mettere il codice direttamente qua aiuta con la velocità di campionamento // TODO: dovresti segnalare che ADC è pronta per la lettura al resto del codice tmp = ADC3->DR; 8001078: 4b32 ldr r3, [pc, #200] @ (8001144 ) 800107a: 6c1b ldr r3, [r3, #64] @ 0x40 800107c: b29a uxth r2, r3 800107e: 4b32 ldr r3, [pc, #200] @ (8001148 ) 8001080: 801a strh r2, [r3, #0] if(TA & FULL){ 8001082: 4b32 ldr r3, [pc, #200] @ (800114c ) 8001084: 781a ldrb r2, [r3, #0] 8001086: 4b32 ldr r3, [pc, #200] @ (8001150 ) 8001088: 781b ldrb r3, [r3, #0] 800108a: 4013 ands r3, r2 800108c: b2db uxtb r3, r3 800108e: 2b00 cmp r3, #0 8001090: d01a beq.n 80010c8 // trigger attivo if(indx == N_POST){ 8001092: 4b30 ldr r3, [pc, #192] @ (8001154 ) 8001094: 781b ldrb r3, [r3, #0] 8001096: 2b46 cmp r3, #70 @ 0x46 8001098: d10f bne.n 80010ba TIM6->CR1 &= ~(TIM_CR1_CEN); // stop timer 800109a: 4b2f ldr r3, [pc, #188] @ (8001158 ) 800109c: 681b ldr r3, [r3, #0] 800109e: 4a2e ldr r2, [pc, #184] @ (8001158 ) 80010a0: f023 0301 bic.w r3, r3, #1 80010a4: 6013 str r3, [r2, #0] TA = 0; 80010a6: 4b29 ldr r3, [pc, #164] @ (800114c ) 80010a8: 2200 movs r2, #0 80010aa: 701a strb r2, [r3, #0] FULL = 0; 80010ac: 4b28 ldr r3, [pc, #160] @ (8001150 ) 80010ae: 2200 movs r2, #0 80010b0: 701a strb r2, [r3, #0] indx = 0; 80010b2: 4b28 ldr r3, [pc, #160] @ (8001154 ) 80010b4: 2200 movs r2, #0 80010b6: 701a strb r2, [r3, #0] 80010b8: e038 b.n 800112c }else{ indx++; 80010ba: 4b26 ldr r3, [pc, #152] @ (8001154 ) 80010bc: 781b ldrb r3, [r3, #0] 80010be: 3301 adds r3, #1 80010c0: b2da uxtb r2, r3 80010c2: 4b24 ldr r3, [pc, #144] @ (8001154 ) 80010c4: 701a strb r2, [r3, #0] 80010c6: e031 b.n 800112c } }else{ // trigger logic if(tmp < TH_lo){ 80010c8: 4b1f ldr r3, [pc, #124] @ (8001148 ) 80010ca: 881b ldrh r3, [r3, #0] 80010cc: f244 52d1 movw r2, #17873 @ 0x45d1 80010d0: 4293 cmp r3, r2 80010d2: d803 bhi.n 80010dc // trigger ready TR = 1; 80010d4: 4b21 ldr r3, [pc, #132] @ (800115c ) 80010d6: 2201 movs r2, #1 80010d8: 701a strb r2, [r3, #0] 80010da: e027 b.n 800112c }else if( (tmp > TH_hi) & (TR == 1) ){ 80010dc: 4b1a ldr r3, [pc, #104] @ (8001148 ) 80010de: 881b ldrh r3, [r3, #0] 80010e0: f644 5293 movw r2, #19859 @ 0x4d93 80010e4: 4293 cmp r3, r2 80010e6: bf8c ite hi 80010e8: 2301 movhi r3, #1 80010ea: 2300 movls r3, #0 80010ec: b2da uxtb r2, r3 80010ee: 4b1b ldr r3, [pc, #108] @ (800115c ) 80010f0: 781b ldrb r3, [r3, #0] 80010f2: 2b01 cmp r3, #1 80010f4: bf0c ite eq 80010f6: 2301 moveq r3, #1 80010f8: 2300 movne r3, #0 80010fa: b2db uxtb r3, r3 80010fc: 4013 ands r3, r2 80010fe: b2db uxtb r3, r3 8001100: 2b00 cmp r3, #0 8001102: d013 beq.n 800112c // trigger active TR = 0; 8001104: 4b15 ldr r3, [pc, #84] @ (800115c ) 8001106: 2200 movs r2, #0 8001108: 701a strb r2, [r3, #0] TA = 1; 800110a: 4b10 ldr r3, [pc, #64] @ (800114c ) 800110c: 2201 movs r2, #1 800110e: 701a strb r2, [r3, #0] POS = N_MEAS - DMA2_Stream0->NDTR -1; 8001110: 4b13 ldr r3, [pc, #76] @ (8001160 ) 8001112: 685b ldr r3, [r3, #4] 8001114: b2db uxtb r3, r3 8001116: f1c3 0363 rsb r3, r3, #99 @ 0x63 800111a: b2da uxtb r2, r3 800111c: 4b11 ldr r3, [pc, #68] @ (8001164 ) 800111e: 701a strb r2, [r3, #0] results[100] = POS; 8001120: 4b10 ldr r3, [pc, #64] @ (8001164 ) 8001122: 781b ldrb r3, [r3, #0] 8001124: 461a mov r2, r3 8001126: 4b10 ldr r3, [pc, #64] @ (8001168 ) 8001128: f8a3 20c8 strh.w r2, [r3, #200] @ 0xc8 }*/ } } // TODO: necessary? ADC3->ISR |= ADC_ISR_EOC; 800112c: 4b05 ldr r3, [pc, #20] @ (8001144 ) 800112e: 681b ldr r3, [r3, #0] 8001130: 4a04 ldr r2, [pc, #16] @ (8001144 ) 8001132: f043 0304 orr.w r3, r3, #4 8001136: 6013 str r3, [r2, #0] /* USER CODE END ADC3_IRQn 0 */ HAL_ADC_IRQHandler(&hadc3); /* USER CODE BEGIN ADC3_IRQn 1 */ #endif /* USER CODE END ADC3_IRQn 1 */ } 8001138: bf00 nop 800113a: 46bd mov sp, r7 800113c: f85d 7b04 ldr.w r7, [sp], #4 8001140: 4770 bx lr 8001142: bf00 nop 8001144: 58026000 .word 0x58026000 8001148: 240001dc .word 0x240001dc 800114c: 240001d6 .word 0x240001d6 8001150: 240001d9 .word 0x240001d9 8001154: 240001da .word 0x240001da 8001158: 40001000 .word 0x40001000 800115c: 240001d7 .word 0x240001d7 8001160: 40020410 .word 0x40020410 8001164: 240001d8 .word 0x240001d8 8001168: 2400010c .word 0x2400010c 0800116c : * configuration. * @param None * @retval None */ void SystemInit (void) { 800116c: b480 push {r7} 800116e: af00 add r7, sp, #0 __IO uint32_t tmpreg; #endif /* DATA_IN_D2_SRAM */ /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 8001170: 4b37 ldr r3, [pc, #220] @ (8001250 ) 8001172: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8001176: 4a36 ldr r2, [pc, #216] @ (8001250 ) 8001178: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 800117c: f8c2 3088 str.w r3, [r2, #136] @ 0x88 #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Increasing the CPU frequency */ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 8001180: 4b34 ldr r3, [pc, #208] @ (8001254 ) 8001182: 681b ldr r3, [r3, #0] 8001184: f003 030f and.w r3, r3, #15 8001188: 2b06 cmp r3, #6 800118a: d807 bhi.n 800119c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 800118c: 4b31 ldr r3, [pc, #196] @ (8001254 ) 800118e: 681b ldr r3, [r3, #0] 8001190: f023 030f bic.w r3, r3, #15 8001194: 4a2f ldr r2, [pc, #188] @ (8001254 ) 8001196: f043 0307 orr.w r3, r3, #7 800119a: 6013 str r3, [r2, #0] } /* Set HSION bit */ RCC->CR |= RCC_CR_HSION; 800119c: 4b2e ldr r3, [pc, #184] @ (8001258 ) 800119e: 681b ldr r3, [r3, #0] 80011a0: 4a2d ldr r2, [pc, #180] @ (8001258 ) 80011a2: f043 0301 orr.w r3, r3, #1 80011a6: 6013 str r3, [r2, #0] /* Reset CFGR register */ RCC->CFGR = 0x00000000; 80011a8: 4b2b ldr r3, [pc, #172] @ (8001258 ) 80011aa: 2200 movs r2, #0 80011ac: 611a str r2, [r3, #16] /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ RCC->CR &= 0xEAF6ED7FU; 80011ae: 4b2a ldr r3, [pc, #168] @ (8001258 ) 80011b0: 681a ldr r2, [r3, #0] 80011b2: 4929 ldr r1, [pc, #164] @ (8001258 ) 80011b4: 4b29 ldr r3, [pc, #164] @ (800125c ) 80011b6: 4013 ands r3, r2 80011b8: 600b str r3, [r1, #0] /* Decreasing the number of wait states because of lower CPU frequency */ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 80011ba: 4b26 ldr r3, [pc, #152] @ (8001254 ) 80011bc: 681b ldr r3, [r3, #0] 80011be: f003 0308 and.w r3, r3, #8 80011c2: 2b00 cmp r3, #0 80011c4: d007 beq.n 80011d6 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 80011c6: 4b23 ldr r3, [pc, #140] @ (8001254 ) 80011c8: 681b ldr r3, [r3, #0] 80011ca: f023 030f bic.w r3, r3, #15 80011ce: 4a21 ldr r2, [pc, #132] @ (8001254 ) 80011d0: f043 0307 orr.w r3, r3, #7 80011d4: 6013 str r3, [r2, #0] } #if defined(D3_SRAM_BASE) /* Reset D1CFGR register */ RCC->D1CFGR = 0x00000000; 80011d6: 4b20 ldr r3, [pc, #128] @ (8001258 ) 80011d8: 2200 movs r2, #0 80011da: 619a str r2, [r3, #24] /* Reset D2CFGR register */ RCC->D2CFGR = 0x00000000; 80011dc: 4b1e ldr r3, [pc, #120] @ (8001258 ) 80011de: 2200 movs r2, #0 80011e0: 61da str r2, [r3, #28] /* Reset D3CFGR register */ RCC->D3CFGR = 0x00000000; 80011e2: 4b1d ldr r3, [pc, #116] @ (8001258 ) 80011e4: 2200 movs r2, #0 80011e6: 621a str r2, [r3, #32] /* Reset SRDCFGR register */ RCC->SRDCFGR = 0x00000000; #endif /* Reset PLLCKSELR register */ RCC->PLLCKSELR = 0x02020200; 80011e8: 4b1b ldr r3, [pc, #108] @ (8001258 ) 80011ea: 4a1d ldr r2, [pc, #116] @ (8001260 ) 80011ec: 629a str r2, [r3, #40] @ 0x28 /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x01FF0000; 80011ee: 4b1a ldr r3, [pc, #104] @ (8001258 ) 80011f0: 4a1c ldr r2, [pc, #112] @ (8001264 ) 80011f2: 62da str r2, [r3, #44] @ 0x2c /* Reset PLL1DIVR register */ RCC->PLL1DIVR = 0x01010280; 80011f4: 4b18 ldr r3, [pc, #96] @ (8001258 ) 80011f6: 4a1c ldr r2, [pc, #112] @ (8001268 ) 80011f8: 631a str r2, [r3, #48] @ 0x30 /* Reset PLL1FRACR register */ RCC->PLL1FRACR = 0x00000000; 80011fa: 4b17 ldr r3, [pc, #92] @ (8001258 ) 80011fc: 2200 movs r2, #0 80011fe: 635a str r2, [r3, #52] @ 0x34 /* Reset PLL2DIVR register */ RCC->PLL2DIVR = 0x01010280; 8001200: 4b15 ldr r3, [pc, #84] @ (8001258 ) 8001202: 4a19 ldr r2, [pc, #100] @ (8001268 ) 8001204: 639a str r2, [r3, #56] @ 0x38 /* Reset PLL2FRACR register */ RCC->PLL2FRACR = 0x00000000; 8001206: 4b14 ldr r3, [pc, #80] @ (8001258 ) 8001208: 2200 movs r2, #0 800120a: 63da str r2, [r3, #60] @ 0x3c /* Reset PLL3DIVR register */ RCC->PLL3DIVR = 0x01010280; 800120c: 4b12 ldr r3, [pc, #72] @ (8001258 ) 800120e: 4a16 ldr r2, [pc, #88] @ (8001268 ) 8001210: 641a str r2, [r3, #64] @ 0x40 /* Reset PLL3FRACR register */ RCC->PLL3FRACR = 0x00000000; 8001212: 4b11 ldr r3, [pc, #68] @ (8001258 ) 8001214: 2200 movs r2, #0 8001216: 645a str r2, [r3, #68] @ 0x44 /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 8001218: 4b0f ldr r3, [pc, #60] @ (8001258 ) 800121a: 681b ldr r3, [r3, #0] 800121c: 4a0e ldr r2, [pc, #56] @ (8001258 ) 800121e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8001222: 6013 str r3, [r2, #0] /* Disable all interrupts */ RCC->CIER = 0x00000000; 8001224: 4b0c ldr r3, [pc, #48] @ (8001258 ) 8001226: 2200 movs r2, #0 8001228: 661a str r2, [r3, #96] @ 0x60 #if (STM32H7_DEV_ID == 0x450UL) /* dual core CM7 or single core line */ if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) 800122a: 4b10 ldr r3, [pc, #64] @ (800126c ) 800122c: 681a ldr r2, [r3, #0] 800122e: 4b10 ldr r3, [pc, #64] @ (8001270 ) 8001230: 4013 ands r3, r2 8001232: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8001236: d202 bcs.n 800123e { /* if stm32h7 revY*/ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ *((__IO uint32_t*)0x51008108) = 0x000000001U; 8001238: 4b0e ldr r3, [pc, #56] @ (8001274 ) 800123a: 2201 movs r2, #1 800123c: 601a str r2, [r3, #0] /* * Disable the FMC bank1 (enabled after reset). * This, prevents CPU speculation access on this bank which blocks the use of FMC during * 24us. During this time the others FMC master (such as LTDC) cannot use it! */ FMC_Bank1_R->BTCR[0] = 0x000030D2; 800123e: 4b0e ldr r3, [pc, #56] @ (8001278 ) 8001240: f243 02d2 movw r2, #12498 @ 0x30d2 8001244: 601a str r2, [r3, #0] #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ #endif /* USER_VECT_TAB_ADDRESS */ #endif /*DUAL_CORE && CORE_CM4*/ } 8001246: bf00 nop 8001248: 46bd mov sp, r7 800124a: f85d 7b04 ldr.w r7, [sp], #4 800124e: 4770 bx lr 8001250: e000ed00 .word 0xe000ed00 8001254: 52002000 .word 0x52002000 8001258: 58024400 .word 0x58024400 800125c: eaf6ed7f .word 0xeaf6ed7f 8001260: 02020200 .word 0x02020200 8001264: 01ff0000 .word 0x01ff0000 8001268: 01010280 .word 0x01010280 800126c: 5c001000 .word 0x5c001000 8001270: ffff0000 .word 0xffff0000 8001274: 51008108 .word 0x51008108 8001278: 52004000 .word 0x52004000 0800127c : TIM_HandleTypeDef htim6; TIM_HandleTypeDef htim7; /* TIM6 init function */ void MX_TIM6_Init(void) { 800127c: b580 push {r7, lr} 800127e: b084 sub sp, #16 8001280: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_Init 0 */ /* USER CODE END TIM6_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 8001282: 1d3b adds r3, r7, #4 8001284: 2200 movs r2, #0 8001286: 601a str r2, [r3, #0] 8001288: 605a str r2, [r3, #4] 800128a: 609a str r2, [r3, #8] /* USER CODE BEGIN TIM6_Init 1 */ /* USER CODE END TIM6_Init 1 */ htim6.Instance = TIM6; 800128c: 4b14 ldr r3, [pc, #80] @ (80012e0 ) 800128e: 4a15 ldr r2, [pc, #84] @ (80012e4 ) 8001290: 601a str r2, [r3, #0] htim6.Init.Prescaler = 0; 8001292: 4b13 ldr r3, [pc, #76] @ (80012e0 ) 8001294: 2200 movs r2, #0 8001296: 605a str r2, [r3, #4] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; 8001298: 4b11 ldr r3, [pc, #68] @ (80012e0 ) 800129a: 2200 movs r2, #0 800129c: 609a str r2, [r3, #8] htim6.Init.Period = 65535; 800129e: 4b10 ldr r3, [pc, #64] @ (80012e0 ) 80012a0: f64f 72ff movw r2, #65535 @ 0xffff 80012a4: 60da str r2, [r3, #12] htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 80012a6: 4b0e ldr r3, [pc, #56] @ (80012e0 ) 80012a8: 2200 movs r2, #0 80012aa: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim6) != HAL_OK) 80012ac: 480c ldr r0, [pc, #48] @ (80012e0 ) 80012ae: f007 fbc1 bl 8008a34 80012b2: 4603 mov r3, r0 80012b4: 2b00 cmp r3, #0 80012b6: d001 beq.n 80012bc { Error_Handler(); 80012b8: f7ff fd98 bl 8000dec } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 80012bc: 2320 movs r3, #32 80012be: 607b str r3, [r7, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 80012c0: 2300 movs r3, #0 80012c2: 60fb str r3, [r7, #12] if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) 80012c4: 1d3b adds r3, r7, #4 80012c6: 4619 mov r1, r3 80012c8: 4805 ldr r0, [pc, #20] @ (80012e0 ) 80012ca: f007 fde3 bl 8008e94 80012ce: 4603 mov r3, r0 80012d0: 2b00 cmp r3, #0 80012d2: d001 beq.n 80012d8 { Error_Handler(); 80012d4: f7ff fd8a bl 8000dec } /* USER CODE BEGIN TIM6_Init 2 */ /* USER CODE END TIM6_Init 2 */ } 80012d8: bf00 nop 80012da: 3710 adds r7, #16 80012dc: 46bd mov sp, r7 80012de: bd80 pop {r7, pc} 80012e0: 240001e0 .word 0x240001e0 80012e4: 40001000 .word 0x40001000 080012e8 : /* TIM7 init function */ void MX_TIM7_Init(void) { 80012e8: b580 push {r7, lr} 80012ea: b084 sub sp, #16 80012ec: af00 add r7, sp, #0 /* USER CODE BEGIN TIM7_Init 0 */ /* USER CODE END TIM7_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 80012ee: 1d3b adds r3, r7, #4 80012f0: 2200 movs r2, #0 80012f2: 601a str r2, [r3, #0] 80012f4: 605a str r2, [r3, #4] 80012f6: 609a str r2, [r3, #8] /* USER CODE BEGIN TIM7_Init 1 */ /* USER CODE END TIM7_Init 1 */ htim7.Instance = TIM7; 80012f8: 4b14 ldr r3, [pc, #80] @ (800134c ) 80012fa: 4a15 ldr r2, [pc, #84] @ (8001350 ) 80012fc: 601a str r2, [r3, #0] htim7.Init.Prescaler = 0; 80012fe: 4b13 ldr r3, [pc, #76] @ (800134c ) 8001300: 2200 movs r2, #0 8001302: 605a str r2, [r3, #4] htim7.Init.CounterMode = TIM_COUNTERMODE_UP; 8001304: 4b11 ldr r3, [pc, #68] @ (800134c ) 8001306: 2200 movs r2, #0 8001308: 609a str r2, [r3, #8] htim7.Init.Period = 65535; 800130a: 4b10 ldr r3, [pc, #64] @ (800134c ) 800130c: f64f 72ff movw r2, #65535 @ 0xffff 8001310: 60da str r2, [r3, #12] htim7.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8001312: 4b0e ldr r3, [pc, #56] @ (800134c ) 8001314: 2200 movs r2, #0 8001316: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim7) != HAL_OK) 8001318: 480c ldr r0, [pc, #48] @ (800134c ) 800131a: f007 fb8b bl 8008a34 800131e: 4603 mov r3, r0 8001320: 2b00 cmp r3, #0 8001322: d001 beq.n 8001328 { Error_Handler(); 8001324: f7ff fd62 bl 8000dec } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8001328: 2300 movs r3, #0 800132a: 607b str r3, [r7, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800132c: 2300 movs r3, #0 800132e: 60fb str r3, [r7, #12] if (HAL_TIMEx_MasterConfigSynchronization(&htim7, &sMasterConfig) != HAL_OK) 8001330: 1d3b adds r3, r7, #4 8001332: 4619 mov r1, r3 8001334: 4805 ldr r0, [pc, #20] @ (800134c ) 8001336: f007 fdad bl 8008e94 800133a: 4603 mov r3, r0 800133c: 2b00 cmp r3, #0 800133e: d001 beq.n 8001344 { Error_Handler(); 8001340: f7ff fd54 bl 8000dec } /* USER CODE BEGIN TIM7_Init 2 */ /* USER CODE END TIM7_Init 2 */ } 8001344: bf00 nop 8001346: 3710 adds r7, #16 8001348: 46bd mov sp, r7 800134a: bd80 pop {r7, pc} 800134c: 2400022c .word 0x2400022c 8001350: 40001400 .word 0x40001400 08001354 : void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) { 8001354: b580 push {r7, lr} 8001356: b084 sub sp, #16 8001358: af00 add r7, sp, #0 800135a: 6078 str r0, [r7, #4] if(tim_baseHandle->Instance==TIM6) 800135c: 687b ldr r3, [r7, #4] 800135e: 681b ldr r3, [r3, #0] 8001360: 4a1d ldr r2, [pc, #116] @ (80013d8 ) 8001362: 4293 cmp r3, r2 8001364: d117 bne.n 8001396 { /* USER CODE BEGIN TIM6_MspInit 0 */ /* USER CODE END TIM6_MspInit 0 */ /* TIM6 clock enable */ __HAL_RCC_TIM6_CLK_ENABLE(); 8001366: 4b1d ldr r3, [pc, #116] @ (80013dc ) 8001368: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 800136c: 4a1b ldr r2, [pc, #108] @ (80013dc ) 800136e: f043 0310 orr.w r3, r3, #16 8001372: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8001376: 4b19 ldr r3, [pc, #100] @ (80013dc ) 8001378: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 800137c: f003 0310 and.w r3, r3, #16 8001380: 60fb str r3, [r7, #12] 8001382: 68fb ldr r3, [r7, #12] /* TIM6 interrupt Init */ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0); 8001384: 2200 movs r2, #0 8001386: 2100 movs r1, #0 8001388: 2036 movs r0, #54 @ 0x36 800138a: f001 fa10 bl 80027ae HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 800138e: 2036 movs r0, #54 @ 0x36 8001390: f001 fa27 bl 80027e2 HAL_NVIC_EnableIRQ(TIM7_IRQn); /* USER CODE BEGIN TIM7_MspInit 1 */ /* USER CODE END TIM7_MspInit 1 */ } } 8001394: e01b b.n 80013ce else if(tim_baseHandle->Instance==TIM7) 8001396: 687b ldr r3, [r7, #4] 8001398: 681b ldr r3, [r3, #0] 800139a: 4a11 ldr r2, [pc, #68] @ (80013e0 ) 800139c: 4293 cmp r3, r2 800139e: d116 bne.n 80013ce __HAL_RCC_TIM7_CLK_ENABLE(); 80013a0: 4b0e ldr r3, [pc, #56] @ (80013dc ) 80013a2: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80013a6: 4a0d ldr r2, [pc, #52] @ (80013dc ) 80013a8: f043 0320 orr.w r3, r3, #32 80013ac: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 80013b0: 4b0a ldr r3, [pc, #40] @ (80013dc ) 80013b2: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80013b6: f003 0320 and.w r3, r3, #32 80013ba: 60bb str r3, [r7, #8] 80013bc: 68bb ldr r3, [r7, #8] HAL_NVIC_SetPriority(TIM7_IRQn, 0, 0); 80013be: 2200 movs r2, #0 80013c0: 2100 movs r1, #0 80013c2: 2037 movs r0, #55 @ 0x37 80013c4: f001 f9f3 bl 80027ae HAL_NVIC_EnableIRQ(TIM7_IRQn); 80013c8: 2037 movs r0, #55 @ 0x37 80013ca: f001 fa0a bl 80027e2 } 80013ce: bf00 nop 80013d0: 3710 adds r7, #16 80013d2: 46bd mov sp, r7 80013d4: bd80 pop {r7, pc} 80013d6: bf00 nop 80013d8: 40001000 .word 0x40001000 80013dc: 58024400 .word 0x58024400 80013e0: 40001400 .word 0x40001400 080013e4 : DMA_HandleTypeDef hdma_usart3_tx; /* USART3 init function */ void MX_USART3_UART_Init(void) { 80013e4: b580 push {r7, lr} 80013e6: af00 add r7, sp, #0 /* USER CODE END USART3_Init 0 */ /* USER CODE BEGIN USART3_Init 1 */ /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; 80013e8: 4b22 ldr r3, [pc, #136] @ (8001474 ) 80013ea: 4a23 ldr r2, [pc, #140] @ (8001478 ) 80013ec: 601a str r2, [r3, #0] huart3.Init.BaudRate = 115200; 80013ee: 4b21 ldr r3, [pc, #132] @ (8001474 ) 80013f0: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80013f4: 605a str r2, [r3, #4] huart3.Init.WordLength = UART_WORDLENGTH_8B; 80013f6: 4b1f ldr r3, [pc, #124] @ (8001474 ) 80013f8: 2200 movs r2, #0 80013fa: 609a str r2, [r3, #8] huart3.Init.StopBits = UART_STOPBITS_1; 80013fc: 4b1d ldr r3, [pc, #116] @ (8001474 ) 80013fe: 2200 movs r2, #0 8001400: 60da str r2, [r3, #12] huart3.Init.Parity = UART_PARITY_NONE; 8001402: 4b1c ldr r3, [pc, #112] @ (8001474 ) 8001404: 2200 movs r2, #0 8001406: 611a str r2, [r3, #16] huart3.Init.Mode = UART_MODE_TX_RX; 8001408: 4b1a ldr r3, [pc, #104] @ (8001474 ) 800140a: 220c movs r2, #12 800140c: 615a str r2, [r3, #20] huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800140e: 4b19 ldr r3, [pc, #100] @ (8001474 ) 8001410: 2200 movs r2, #0 8001412: 619a str r2, [r3, #24] huart3.Init.OverSampling = UART_OVERSAMPLING_16; 8001414: 4b17 ldr r3, [pc, #92] @ (8001474 ) 8001416: 2200 movs r2, #0 8001418: 61da str r2, [r3, #28] huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 800141a: 4b16 ldr r3, [pc, #88] @ (8001474 ) 800141c: 2200 movs r2, #0 800141e: 621a str r2, [r3, #32] huart3.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8001420: 4b14 ldr r3, [pc, #80] @ (8001474 ) 8001422: 2200 movs r2, #0 8001424: 625a str r2, [r3, #36] @ 0x24 huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 8001426: 4b13 ldr r3, [pc, #76] @ (8001474 ) 8001428: 2200 movs r2, #0 800142a: 629a str r2, [r3, #40] @ 0x28 if (HAL_UART_Init(&huart3) != HAL_OK) 800142c: 4811 ldr r0, [pc, #68] @ (8001474 ) 800142e: f007 fddd bl 8008fec 8001432: 4603 mov r3, r0 8001434: 2b00 cmp r3, #0 8001436: d001 beq.n 800143c { Error_Handler(); 8001438: f7ff fcd8 bl 8000dec } if (HAL_UARTEx_SetTxFifoThreshold(&huart3, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 800143c: 2100 movs r1, #0 800143e: 480d ldr r0, [pc, #52] @ (8001474 ) 8001440: f009 fa36 bl 800a8b0 8001444: 4603 mov r3, r0 8001446: 2b00 cmp r3, #0 8001448: d001 beq.n 800144e { Error_Handler(); 800144a: f7ff fccf bl 8000dec } if (HAL_UARTEx_SetRxFifoThreshold(&huart3, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 800144e: 2100 movs r1, #0 8001450: 4808 ldr r0, [pc, #32] @ (8001474 ) 8001452: f009 fa6b bl 800a92c 8001456: 4603 mov r3, r0 8001458: 2b00 cmp r3, #0 800145a: d001 beq.n 8001460 { Error_Handler(); 800145c: f7ff fcc6 bl 8000dec } if (HAL_UARTEx_DisableFifoMode(&huart3) != HAL_OK) 8001460: 4804 ldr r0, [pc, #16] @ (8001474 ) 8001462: f009 f9ec bl 800a83e 8001466: 4603 mov r3, r0 8001468: 2b00 cmp r3, #0 800146a: d001 beq.n 8001470 { Error_Handler(); 800146c: f7ff fcbe bl 8000dec } /* USER CODE BEGIN USART3_Init 2 */ /* USER CODE END USART3_Init 2 */ } 8001470: bf00 nop 8001472: bd80 pop {r7, pc} 8001474: 24000278 .word 0x24000278 8001478: 40004800 .word 0x40004800 0800147c : void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) { 800147c: b580 push {r7, lr} 800147e: b08a sub sp, #40 @ 0x28 8001480: af00 add r7, sp, #0 8001482: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001484: f107 0314 add.w r3, r7, #20 8001488: 2200 movs r2, #0 800148a: 601a str r2, [r3, #0] 800148c: 605a str r2, [r3, #4] 800148e: 609a str r2, [r3, #8] 8001490: 60da str r2, [r3, #12] 8001492: 611a str r2, [r3, #16] if(uartHandle->Instance==USART3) 8001494: 687b ldr r3, [r7, #4] 8001496: 681b ldr r3, [r3, #0] 8001498: 4a35 ldr r2, [pc, #212] @ (8001570 ) 800149a: 4293 cmp r3, r2 800149c: d163 bne.n 8001566 { /* USER CODE BEGIN USART3_MspInit 0 */ /* USER CODE END USART3_MspInit 0 */ /* USART3 clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); 800149e: 4b35 ldr r3, [pc, #212] @ (8001574 ) 80014a0: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80014a4: 4a33 ldr r2, [pc, #204] @ (8001574 ) 80014a6: f443 2380 orr.w r3, r3, #262144 @ 0x40000 80014aa: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 80014ae: 4b31 ldr r3, [pc, #196] @ (8001574 ) 80014b0: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80014b4: f403 2380 and.w r3, r3, #262144 @ 0x40000 80014b8: 613b str r3, [r7, #16] 80014ba: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOD_CLK_ENABLE(); 80014bc: 4b2d ldr r3, [pc, #180] @ (8001574 ) 80014be: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80014c2: 4a2c ldr r2, [pc, #176] @ (8001574 ) 80014c4: f043 0308 orr.w r3, r3, #8 80014c8: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80014cc: 4b29 ldr r3, [pc, #164] @ (8001574 ) 80014ce: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80014d2: f003 0308 and.w r3, r3, #8 80014d6: 60fb str r3, [r7, #12] 80014d8: 68fb ldr r3, [r7, #12] /**USART3 GPIO Configuration PD8 ------> USART3_TX PD9 ------> USART3_RX */ GPIO_InitStruct.Pin = STLINK_RX_Pin|STLINK_TX_Pin; 80014da: f44f 7340 mov.w r3, #768 @ 0x300 80014de: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80014e0: 2302 movs r3, #2 80014e2: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80014e4: 2300 movs r3, #0 80014e6: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80014e8: 2300 movs r3, #0 80014ea: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF7_USART3; 80014ec: 2307 movs r3, #7 80014ee: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 80014f0: f107 0314 add.w r3, r7, #20 80014f4: 4619 mov r1, r3 80014f6: 4820 ldr r0, [pc, #128] @ (8001578 ) 80014f8: f003 fbb4 bl 8004c64 /* USART3 DMA Init */ /* USART3_TX Init */ hdma_usart3_tx.Instance = DMA1_Stream3; 80014fc: 4b1f ldr r3, [pc, #124] @ (800157c ) 80014fe: 4a20 ldr r2, [pc, #128] @ (8001580 ) 8001500: 601a str r2, [r3, #0] hdma_usart3_tx.Init.Request = DMA_REQUEST_USART3_TX; 8001502: 4b1e ldr r3, [pc, #120] @ (800157c ) 8001504: 222e movs r2, #46 @ 0x2e 8001506: 605a str r2, [r3, #4] hdma_usart3_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001508: 4b1c ldr r3, [pc, #112] @ (800157c ) 800150a: 2240 movs r2, #64 @ 0x40 800150c: 609a str r2, [r3, #8] hdma_usart3_tx.Init.PeriphInc = DMA_PINC_DISABLE; 800150e: 4b1b ldr r3, [pc, #108] @ (800157c ) 8001510: 2200 movs r2, #0 8001512: 60da str r2, [r3, #12] hdma_usart3_tx.Init.MemInc = DMA_MINC_ENABLE; 8001514: 4b19 ldr r3, [pc, #100] @ (800157c ) 8001516: f44f 6280 mov.w r2, #1024 @ 0x400 800151a: 611a str r2, [r3, #16] hdma_usart3_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800151c: 4b17 ldr r3, [pc, #92] @ (800157c ) 800151e: 2200 movs r2, #0 8001520: 615a str r2, [r3, #20] hdma_usart3_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001522: 4b16 ldr r3, [pc, #88] @ (800157c ) 8001524: 2200 movs r2, #0 8001526: 619a str r2, [r3, #24] hdma_usart3_tx.Init.Mode = DMA_NORMAL; 8001528: 4b14 ldr r3, [pc, #80] @ (800157c ) 800152a: 2200 movs r2, #0 800152c: 61da str r2, [r3, #28] hdma_usart3_tx.Init.Priority = DMA_PRIORITY_LOW; 800152e: 4b13 ldr r3, [pc, #76] @ (800157c ) 8001530: 2200 movs r2, #0 8001532: 621a str r2, [r3, #32] hdma_usart3_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001534: 4b11 ldr r3, [pc, #68] @ (800157c ) 8001536: 2200 movs r2, #0 8001538: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_usart3_tx) != HAL_OK) 800153a: 4810 ldr r0, [pc, #64] @ (800157c ) 800153c: f001 f96c bl 8002818 8001540: 4603 mov r3, r0 8001542: 2b00 cmp r3, #0 8001544: d001 beq.n 800154a { Error_Handler(); 8001546: f7ff fc51 bl 8000dec } __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart3_tx); 800154a: 687b ldr r3, [r7, #4] 800154c: 4a0b ldr r2, [pc, #44] @ (800157c ) 800154e: 67da str r2, [r3, #124] @ 0x7c 8001550: 4a0a ldr r2, [pc, #40] @ (800157c ) 8001552: 687b ldr r3, [r7, #4] 8001554: 6393 str r3, [r2, #56] @ 0x38 /* USART3 interrupt Init */ HAL_NVIC_SetPriority(USART3_IRQn, 0, 0); 8001556: 2200 movs r2, #0 8001558: 2100 movs r1, #0 800155a: 2027 movs r0, #39 @ 0x27 800155c: f001 f927 bl 80027ae HAL_NVIC_EnableIRQ(USART3_IRQn); 8001560: 2027 movs r0, #39 @ 0x27 8001562: f001 f93e bl 80027e2 /* USER CODE BEGIN USART3_MspInit 1 */ /* USER CODE END USART3_MspInit 1 */ } } 8001566: bf00 nop 8001568: 3728 adds r7, #40 @ 0x28 800156a: 46bd mov sp, r7 800156c: bd80 pop {r7, pc} 800156e: bf00 nop 8001570: 40004800 .word 0x40004800 8001574: 58024400 .word 0x58024400 8001578: 58020c00 .word 0x58020c00 800157c: 2400030c .word 0x2400030c 8001580: 40020058 .word 0x40020058 08001584 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8001584: f8df d034 ldr.w sp, [pc, #52] @ 80015bc /* Call the clock system initialization function.*/ bl SystemInit 8001588: f7ff fdf0 bl 800116c /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 800158c: 480c ldr r0, [pc, #48] @ (80015c0 ) ldr r1, =_edata 800158e: 490d ldr r1, [pc, #52] @ (80015c4 ) ldr r2, =_sidata 8001590: 4a0d ldr r2, [pc, #52] @ (80015c8 ) movs r3, #0 8001592: 2300 movs r3, #0 b LoopCopyDataInit 8001594: e002 b.n 800159c 08001596 : CopyDataInit: ldr r4, [r2, r3] 8001596: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8001598: 50c4 str r4, [r0, r3] adds r3, r3, #4 800159a: 3304 adds r3, #4 0800159c : LoopCopyDataInit: adds r4, r0, r3 800159c: 18c4 adds r4, r0, r3 cmp r4, r1 800159e: 428c cmp r4, r1 bcc CopyDataInit 80015a0: d3f9 bcc.n 8001596 /* Zero fill the bss segment. */ ldr r2, =_sbss 80015a2: 4a0a ldr r2, [pc, #40] @ (80015cc ) ldr r4, =_ebss 80015a4: 4c0a ldr r4, [pc, #40] @ (80015d0 ) movs r3, #0 80015a6: 2300 movs r3, #0 b LoopFillZerobss 80015a8: e001 b.n 80015ae 080015aa : FillZerobss: str r3, [r2] 80015aa: 6013 str r3, [r2, #0] adds r2, r2, #4 80015ac: 3204 adds r2, #4 080015ae : LoopFillZerobss: cmp r2, r4 80015ae: 42a2 cmp r2, r4 bcc FillZerobss 80015b0: d3fb bcc.n 80015aa /* Call static constructors */ bl __libc_init_array 80015b2: f009 fa4f bl 800aa54 <__libc_init_array> /* Call the application's entry point.*/ bl main 80015b6: f7ff fc9f bl 8000ef8
bx lr 80015ba: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 80015bc: 24080000 .word 0x24080000 ldr r0, =_sdata 80015c0: 24000000 .word 0x24000000 ldr r1, =_edata 80015c4: 24000010 .word 0x24000010 ldr r2, =_sidata 80015c8: 0800ab04 .word 0x0800ab04 ldr r2, =_sbss 80015cc: 24000010 .word 0x24000010 ldr r4, =_ebss 80015d0: 24000388 .word 0x24000388 080015d4 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80015d4: e7fe b.n 80015d4 ... 080015d8 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80015d8: b580 push {r7, lr} 80015da: b082 sub sp, #8 80015dc: af00 add r7, sp, #0 __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */ __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */ #endif /* DUAL_CORE && CORE_CM4 */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 80015de: 2003 movs r0, #3 80015e0: f001 f8da bl 8002798 /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 80015e4: f004 fb52 bl 8005c8c 80015e8: 4602 mov r2, r0 80015ea: 4b15 ldr r3, [pc, #84] @ (8001640 ) 80015ec: 699b ldr r3, [r3, #24] 80015ee: 0a1b lsrs r3, r3, #8 80015f0: f003 030f and.w r3, r3, #15 80015f4: 4913 ldr r1, [pc, #76] @ (8001644 ) 80015f6: 5ccb ldrb r3, [r1, r3] 80015f8: f003 031f and.w r3, r3, #31 80015fc: fa22 f303 lsr.w r3, r2, r3 8001600: 607b str r3, [r7, #4] common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif /* Update the SystemD2Clock global variable */ #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8001602: 4b0f ldr r3, [pc, #60] @ (8001640 ) 8001604: 699b ldr r3, [r3, #24] 8001606: f003 030f and.w r3, r3, #15 800160a: 4a0e ldr r2, [pc, #56] @ (8001644 ) 800160c: 5cd3 ldrb r3, [r2, r3] 800160e: f003 031f and.w r3, r3, #31 8001612: 687a ldr r2, [r7, #4] 8001614: fa22 f303 lsr.w r3, r2, r3 8001618: 4a0b ldr r2, [pc, #44] @ (8001648 ) 800161a: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 800161c: 4a0b ldr r2, [pc, #44] @ (800164c ) 800161e: 687b ldr r3, [r7, #4] 8001620: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8001622: 2000 movs r0, #0 8001624: f000 f814 bl 8001650 8001628: 4603 mov r3, r0 800162a: 2b00 cmp r3, #0 800162c: d001 beq.n 8001632 { return HAL_ERROR; 800162e: 2301 movs r3, #1 8001630: e002 b.n 8001638 } /* Init the low level hardware */ HAL_MspInit(); 8001632: f7ff fc85 bl 8000f40 /* Return function status */ return HAL_OK; 8001636: 2300 movs r3, #0 } 8001638: 4618 mov r0, r3 800163a: 3708 adds r7, #8 800163c: 46bd mov sp, r7 800163e: bd80 pop {r7, pc} 8001640: 58024400 .word 0x58024400 8001644: 0800aab4 .word 0x0800aab4 8001648: 24000004 .word 0x24000004 800164c: 24000000 .word 0x24000000 08001650 : * implementation in user file. * @param TickPriority: Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8001650: b580 push {r7, lr} 8001652: b082 sub sp, #8 8001654: af00 add r7, sp, #0 8001656: 6078 str r0, [r7, #4] /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/ if((uint32_t)uwTickFreq == 0UL) 8001658: 4b15 ldr r3, [pc, #84] @ (80016b0 ) 800165a: 781b ldrb r3, [r3, #0] 800165c: 2b00 cmp r3, #0 800165e: d101 bne.n 8001664 { return HAL_ERROR; 8001660: 2301 movs r3, #1 8001662: e021 b.n 80016a8 } /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U) 8001664: 4b13 ldr r3, [pc, #76] @ (80016b4 ) 8001666: 681a ldr r2, [r3, #0] 8001668: 4b11 ldr r3, [pc, #68] @ (80016b0 ) 800166a: 781b ldrb r3, [r3, #0] 800166c: 4619 mov r1, r3 800166e: f44f 737a mov.w r3, #1000 @ 0x3e8 8001672: fbb3 f3f1 udiv r3, r3, r1 8001676: fbb2 f3f3 udiv r3, r2, r3 800167a: 4618 mov r0, r3 800167c: f001 f8bf bl 80027fe 8001680: 4603 mov r3, r0 8001682: 2b00 cmp r3, #0 8001684: d001 beq.n 800168a { return HAL_ERROR; 8001686: 2301 movs r3, #1 8001688: e00e b.n 80016a8 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800168a: 687b ldr r3, [r7, #4] 800168c: 2b0f cmp r3, #15 800168e: d80a bhi.n 80016a6 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8001690: 2200 movs r2, #0 8001692: 6879 ldr r1, [r7, #4] 8001694: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8001698: f001 f889 bl 80027ae uwTickPrio = TickPriority; 800169c: 4a06 ldr r2, [pc, #24] @ (80016b8 ) 800169e: 687b ldr r3, [r7, #4] 80016a0: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 80016a2: 2300 movs r3, #0 80016a4: e000 b.n 80016a8 return HAL_ERROR; 80016a6: 2301 movs r3, #1 } 80016a8: 4618 mov r0, r3 80016aa: 3708 adds r7, #8 80016ac: 46bd mov sp, r7 80016ae: bd80 pop {r7, pc} 80016b0: 2400000c .word 0x2400000c 80016b4: 24000000 .word 0x24000000 80016b8: 24000008 .word 0x24000008 080016bc : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 80016bc: b480 push {r7} 80016be: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 80016c0: 4b06 ldr r3, [pc, #24] @ (80016dc ) 80016c2: 781b ldrb r3, [r3, #0] 80016c4: 461a mov r2, r3 80016c6: 4b06 ldr r3, [pc, #24] @ (80016e0 ) 80016c8: 681b ldr r3, [r3, #0] 80016ca: 4413 add r3, r2 80016cc: 4a04 ldr r2, [pc, #16] @ (80016e0 ) 80016ce: 6013 str r3, [r2, #0] } 80016d0: bf00 nop 80016d2: 46bd mov sp, r7 80016d4: f85d 7b04 ldr.w r7, [sp], #4 80016d8: 4770 bx lr 80016da: bf00 nop 80016dc: 2400000c .word 0x2400000c 80016e0: 24000384 .word 0x24000384 080016e4 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80016e4: b480 push {r7} 80016e6: af00 add r7, sp, #0 return uwTick; 80016e8: 4b03 ldr r3, [pc, #12] @ (80016f8 ) 80016ea: 681b ldr r3, [r3, #0] } 80016ec: 4618 mov r0, r3 80016ee: 46bd mov sp, r7 80016f0: f85d 7b04 ldr.w r7, [sp], #4 80016f4: 4770 bx lr 80016f6: bf00 nop 80016f8: 24000384 .word 0x24000384 080016fc : /** * @brief Returns the device revision identifier. * @retval Device revision identifier */ uint32_t HAL_GetREVID(void) { 80016fc: b480 push {r7} 80016fe: af00 add r7, sp, #0 return((DBGMCU->IDCODE) >> 16); 8001700: 4b03 ldr r3, [pc, #12] @ (8001710 ) 8001702: 681b ldr r3, [r3, #0] 8001704: 0c1b lsrs r3, r3, #16 } 8001706: 4618 mov r0, r3 8001708: 46bd mov sp, r7 800170a: f85d 7b04 ldr.w r7, [sp], #4 800170e: 4770 bx lr 8001710: 5c001000 .word 0x5c001000 08001714 : * @arg SYSCFG_SWITCH_PC3_CLOSE * @retval None */ void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState ) { 8001714: b480 push {r7} 8001716: b083 sub sp, #12 8001718: af00 add r7, sp, #0 800171a: 6078 str r0, [r7, #4] 800171c: 6039 str r1, [r7, #0] /* Check the parameter */ assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch)); assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState)); MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState)); 800171e: 4b07 ldr r3, [pc, #28] @ (800173c ) 8001720: 685a ldr r2, [r3, #4] 8001722: 687b ldr r3, [r7, #4] 8001724: 43db mvns r3, r3 8001726: 401a ands r2, r3 8001728: 4904 ldr r1, [pc, #16] @ (800173c ) 800172a: 683b ldr r3, [r7, #0] 800172c: 4313 orrs r3, r2 800172e: 604b str r3, [r1, #4] } 8001730: bf00 nop 8001732: 370c adds r7, #12 8001734: 46bd mov sp, r7 8001736: f85d 7b04 ldr.w r7, [sp], #4 800173a: 4770 bx lr 800173c: 58000400 .word 0x58000400 08001740 : * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) { 8001740: b480 push {r7} 8001742: b083 sub sp, #12 8001744: af00 add r7, sp, #0 8001746: 6078 str r0, [r7, #4] 8001748: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); 800174a: 687b ldr r3, [r7, #4] 800174c: 689b ldr r3, [r3, #8] 800174e: f423 127c bic.w r2, r3, #4128768 @ 0x3f0000 8001752: 683b ldr r3, [r7, #0] 8001754: 431a orrs r2, r3 8001756: 687b ldr r3, [r7, #4] 8001758: 609a str r2, [r3, #8] } 800175a: bf00 nop 800175c: 370c adds r7, #12 800175e: 46bd mov sp, r7 8001760: f85d 7b04 ldr.w r7, [sp], #4 8001764: 4770 bx lr 08001766 : * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) { 8001766: b480 push {r7} 8001768: b083 sub sp, #12 800176a: af00 add r7, sp, #0 800176c: 6078 str r0, [r7, #4] 800176e: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal); 8001770: 687b ldr r3, [r7, #4] 8001772: 689b ldr r3, [r3, #8] 8001774: f023 72e0 bic.w r2, r3, #29360128 @ 0x1c00000 8001778: 683b ldr r3, [r7, #0] 800177a: 431a orrs r2, r3 800177c: 687b ldr r3, [r7, #4] 800177e: 609a str r2, [r3, #8] } 8001780: bf00 nop 8001782: 370c adds r7, #12 8001784: 46bd mov sp, r7 8001786: f85d 7b04 ldr.w r7, [sp], #4 800178a: 4770 bx lr 0800178c : * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT */ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON) { 800178c: b480 push {r7} 800178e: b083 sub sp, #12 8001790: af00 add r7, sp, #0 8001792: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); 8001794: 687b ldr r3, [r7, #4] 8001796: 689b ldr r3, [r3, #8] 8001798: f003 73e0 and.w r3, r3, #29360128 @ 0x1c00000 } 800179c: 4618 mov r0, r3 800179e: 370c adds r7, #12 80017a0: 46bd mov sp, r7 80017a2: f85d 7b04 ldr.w r7, [sp], #4 80017a6: 4770 bx lr 080017a8 : * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_19 * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelPreselection(ADC_TypeDef *ADCx, uint32_t Channel) { 80017a8: b480 push {r7} 80017aa: b087 sub sp, #28 80017ac: af00 add r7, sp, #0 80017ae: 6078 str r0, [r7, #4] 80017b0: 6039 str r1, [r7, #0] /* ADC channels preselection */ ADCx->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL)); } #else /* ADC channels preselection */ ADCx->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL)); 80017b2: 683b ldr r3, [r7, #0] 80017b4: f3c3 0313 ubfx r3, r3, #0, #20 80017b8: 2b00 cmp r3, #0 80017ba: d107 bne.n 80017cc 80017bc: 683b ldr r3, [r7, #0] 80017be: 0e9b lsrs r3, r3, #26 80017c0: f003 031f and.w r3, r3, #31 80017c4: 2201 movs r2, #1 80017c6: fa02 f303 lsl.w r3, r2, r3 80017ca: e015 b.n 80017f8 80017cc: 683b ldr r3, [r7, #0] 80017ce: 613b str r3, [r7, #16] uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80017d0: 693b ldr r3, [r7, #16] 80017d2: fa93 f3a3 rbit r3, r3 80017d6: 60fb str r3, [r7, #12] result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; 80017d8: 68fb ldr r3, [r7, #12] 80017da: 617b str r3, [r7, #20] optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) 80017dc: 697b ldr r3, [r7, #20] 80017de: 2b00 cmp r3, #0 80017e0: d101 bne.n 80017e6 { return 32U; 80017e2: 2320 movs r3, #32 80017e4: e003 b.n 80017ee } return __builtin_clz(value); 80017e6: 697b ldr r3, [r7, #20] 80017e8: fab3 f383 clz r3, r3 80017ec: b2db uxtb r3, r3 80017ee: f003 031f and.w r3, r3, #31 80017f2: 2201 movs r2, #1 80017f4: fa02 f303 lsl.w r3, r2, r3 80017f8: 687a ldr r2, [r7, #4] 80017fa: 69d2 ldr r2, [r2, #28] 80017fc: 431a orrs r2, r3 80017fe: 687b ldr r3, [r7, #4] 8001800: 61da str r2, [r3, #28] #endif /* ADC_VER_V5_V90 */ } 8001802: bf00 nop 8001804: 371c adds r7, #28 8001806: 46bd mov sp, r7 8001808: f85d 7b04 ldr.w r7, [sp], #4 800180c: 4770 bx lr 0800180e : * Other channels are slow channels (conversion rate: refer to reference manual). * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0x3FFFFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) { 800180e: b480 push {r7} 8001810: b087 sub sp, #28 8001812: af00 add r7, sp, #0 8001814: 60f8 str r0, [r7, #12] 8001816: 60b9 str r1, [r7, #8] 8001818: 607a str r2, [r7, #4] 800181a: 603b str r3, [r7, #0] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 800181c: 68fb ldr r3, [r7, #12] 800181e: 3360 adds r3, #96 @ 0x60 8001820: 461a mov r2, r3 8001822: 68bb ldr r3, [r7, #8] 8001824: 009b lsls r3, r3, #2 8001826: 4413 add r3, r2 8001828: 617b str r3, [r7, #20] ADC3_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); } else #endif /* ADC_VER_V5_V90 */ { MODIFY_REG(*preg, 800182a: 697b ldr r3, [r7, #20] 800182c: 681b ldr r3, [r3, #0] 800182e: f003 4200 and.w r2, r3, #2147483648 @ 0x80000000 8001832: 687b ldr r3, [r7, #4] 8001834: f003 41f8 and.w r1, r3, #2080374784 @ 0x7c000000 8001838: 683b ldr r3, [r7, #0] 800183a: 430b orrs r3, r1 800183c: 431a orrs r2, r3 800183e: 697b ldr r3, [r7, #20] 8001840: 601a str r2, [r3, #0] ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); } } 8001842: bf00 nop 8001844: 371c adds r7, #28 8001846: 46bd mov sp, r7 8001848: f85d 7b04 ldr.w r7, [sp], #4 800184c: 4770 bx lr 0800184e : * @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE * @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE * @retval Returned None */ __STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift) { 800184e: b480 push {r7} 8001850: b085 sub sp, #20 8001852: af00 add r7, sp, #0 8001854: 60f8 str r0, [r7, #12] 8001856: 60b9 str r1, [r7, #8] 8001858: 607a str r2, [r7, #4] MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL)); 800185a: 68fb ldr r3, [r7, #12] 800185c: 691b ldr r3, [r3, #16] 800185e: f423 42f0 bic.w r2, r3, #30720 @ 0x7800 8001862: 68bb ldr r3, [r7, #8] 8001864: f003 031f and.w r3, r3, #31 8001868: 6879 ldr r1, [r7, #4] 800186a: fa01 f303 lsl.w r3, r1, r3 800186e: 431a orrs r2, r3 8001870: 68fb ldr r3, [r7, #12] 8001872: 611a str r2, [r3, #16] } 8001874: bf00 nop 8001876: 3714 adds r7, #20 8001878: 46bd mov sp, r7 800187a: f85d 7b04 ldr.w r7, [sp], #4 800187e: 4770 bx lr 08001880 : * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE * @retval Returned None */ __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation) { 8001880: b480 push {r7} 8001882: b087 sub sp, #28 8001884: af00 add r7, sp, #0 8001886: 60f8 str r0, [r7, #12] 8001888: 60b9 str r1, [r7, #8] 800188a: 607a str r2, [r7, #4] /* Function not available on this instance */ } else #endif /* ADC_VER_V5_V90 */ { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 800188c: 68fb ldr r3, [r7, #12] 800188e: 3360 adds r3, #96 @ 0x60 8001890: 461a mov r2, r3 8001892: 68bb ldr r3, [r7, #8] 8001894: 009b lsls r3, r3, #2 8001896: 4413 add r3, r2 8001898: 617b str r3, [r7, #20] MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation); 800189a: 697b ldr r3, [r7, #20] 800189c: 681b ldr r3, [r3, #0] 800189e: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000 80018a2: 687b ldr r3, [r7, #4] 80018a4: 431a orrs r2, r3 80018a6: 697b ldr r3, [r7, #20] 80018a8: 601a str r2, [r3, #0] } } 80018aa: bf00 nop 80018ac: 371c adds r7, #28 80018ae: 46bd mov sp, r7 80018b0: f85d 7b04 ldr.w r7, [sp], #4 80018b4: 4770 bx lr 080018b6 : * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) { 80018b6: b480 push {r7} 80018b8: b087 sub sp, #28 80018ba: af00 add r7, sp, #0 80018bc: 60f8 str r0, [r7, #12] 80018be: 60b9 str r1, [r7, #8] 80018c0: 607a str r2, [r7, #4] /* Set bits with content of parameter "Channel" with bits position */ /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); 80018c2: 68fb ldr r3, [r7, #12] 80018c4: 3330 adds r3, #48 @ 0x30 80018c6: 461a mov r2, r3 80018c8: 68bb ldr r3, [r7, #8] 80018ca: 0a1b lsrs r3, r3, #8 80018cc: 009b lsls r3, r3, #2 80018ce: f003 030c and.w r3, r3, #12 80018d2: 4413 add r3, r2 80018d4: 617b str r3, [r7, #20] MODIFY_REG(*preg, 80018d6: 697b ldr r3, [r7, #20] 80018d8: 681a ldr r2, [r3, #0] 80018da: 68bb ldr r3, [r7, #8] 80018dc: f003 031f and.w r3, r3, #31 80018e0: 211f movs r1, #31 80018e2: fa01 f303 lsl.w r3, r1, r3 80018e6: 43db mvns r3, r3 80018e8: 401a ands r2, r3 80018ea: 687b ldr r3, [r7, #4] 80018ec: 0e9b lsrs r3, r3, #26 80018ee: f003 011f and.w r1, r3, #31 80018f2: 68bb ldr r3, [r7, #8] 80018f4: f003 031f and.w r3, r3, #31 80018f8: fa01 f303 lsl.w r3, r1, r3 80018fc: 431a orrs r2, r3 80018fe: 697b ldr r3, [r7, #20] 8001900: 601a str r2, [r3, #0] ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); } 8001902: bf00 nop 8001904: 371c adds r7, #28 8001906: 46bd mov sp, r7 8001908: f85d 7b04 ldr.w r7, [sp], #4 800190c: 4770 bx lr 0800190e : * @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5 * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) { 800190e: b480 push {r7} 8001910: b087 sub sp, #28 8001912: af00 add r7, sp, #0 8001914: 60f8 str r0, [r7, #12] 8001916: 60b9 str r1, [r7, #8] 8001918: 607a str r2, [r7, #4] /* Set bits with content of parameter "SamplingTime" with bits position */ /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); 800191a: 68fb ldr r3, [r7, #12] 800191c: 3314 adds r3, #20 800191e: 461a mov r2, r3 8001920: 68bb ldr r3, [r7, #8] 8001922: 0e5b lsrs r3, r3, #25 8001924: 009b lsls r3, r3, #2 8001926: f003 0304 and.w r3, r3, #4 800192a: 4413 add r3, r2 800192c: 617b str r3, [r7, #20] MODIFY_REG(*preg, 800192e: 697b ldr r3, [r7, #20] 8001930: 681a ldr r2, [r3, #0] 8001932: 68bb ldr r3, [r7, #8] 8001934: 0d1b lsrs r3, r3, #20 8001936: f003 031f and.w r3, r3, #31 800193a: 2107 movs r1, #7 800193c: fa01 f303 lsl.w r3, r1, r3 8001940: 43db mvns r3, r3 8001942: 401a ands r2, r3 8001944: 68bb ldr r3, [r7, #8] 8001946: 0d1b lsrs r3, r3, #20 8001948: f003 031f and.w r3, r3, #31 800194c: 6879 ldr r1, [r7, #4] 800194e: fa01 f303 lsl.w r3, r1, r3 8001952: 431a orrs r2, r3 8001954: 697b ldr r3, [r7, #20] 8001956: 601a str r2, [r3, #0] ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); } 8001958: bf00 nop 800195a: 371c adds r7, #28 800195c: 46bd mov sp, r7 800195e: f85d 7b04 ldr.w r7, [sp], #4 8001962: 4770 bx lr 08001964 : * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff) { 8001964: b480 push {r7} 8001966: b085 sub sp, #20 8001968: af00 add r7, sp, #0 800196a: 60f8 str r0, [r7, #12] 800196c: 60b9 str r1, [r7, #8] 800196e: 607a str r2, [r7, #4] } #else /* ADC_VER_V5_V90 */ /* Bits of channels in single or differential mode are set only for */ /* differential mode (for single mode, mask of bits allowed to be set is */ /* shifted out of range of bits of channels in single or differential mode. */ MODIFY_REG(ADCx->DIFSEL, 8001970: 68fb ldr r3, [r7, #12] 8001972: f8d3 20c0 ldr.w r2, [r3, #192] @ 0xc0 8001976: 68bb ldr r3, [r7, #8] 8001978: f3c3 0313 ubfx r3, r3, #0, #20 800197c: 43db mvns r3, r3 800197e: 401a ands r2, r3 8001980: 687b ldr r3, [r7, #4] 8001982: f003 0318 and.w r3, r3, #24 8001986: 4908 ldr r1, [pc, #32] @ (80019a8 ) 8001988: 40d9 lsrs r1, r3 800198a: 68bb ldr r3, [r7, #8] 800198c: 400b ands r3, r1 800198e: f3c3 0313 ubfx r3, r3, #0, #20 8001992: 431a orrs r2, r3 8001994: 68fb ldr r3, [r7, #12] 8001996: f8c3 20c0 str.w r2, [r3, #192] @ 0xc0 Channel & ADC_SINGLEDIFF_CHANNEL_MASK, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK))); #endif /* ADC_VER_V5_V90 */ } 800199a: bf00 nop 800199c: 3714 adds r7, #20 800199e: 46bd mov sp, r7 80019a0: f85d 7b04 ldr.w r7, [sp], #4 80019a4: 4770 bx lr 80019a6: bf00 nop 80019a8: 000fffff .word 0x000fffff 080019ac : * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) { 80019ac: b480 push {r7} 80019ae: b083 sub sp, #12 80019b0: af00 add r7, sp, #0 80019b2: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS)); 80019b4: 687b ldr r3, [r7, #4] 80019b6: 689a ldr r2, [r3, #8] 80019b8: 4b04 ldr r3, [pc, #16] @ (80019cc ) 80019ba: 4013 ands r3, r2 80019bc: 687a ldr r2, [r7, #4] 80019be: 6093 str r3, [r2, #8] } 80019c0: bf00 nop 80019c2: 370c adds r7, #12 80019c4: 46bd mov sp, r7 80019c6: f85d 7b04 ldr.w r7, [sp], #4 80019ca: 4770 bx lr 80019cc: 5fffffc0 .word 0x5fffffc0 080019d0 : * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled * @param ADCx ADC instance * @retval 0: deep power down is disabled, 1: deep power down is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx) { 80019d0: b480 push {r7} 80019d2: b083 sub sp, #12 80019d4: af00 add r7, sp, #0 80019d6: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); 80019d8: 687b ldr r3, [r7, #4] 80019da: 689b ldr r3, [r3, #8] 80019dc: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 80019e0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80019e4: d101 bne.n 80019ea 80019e6: 2301 movs r3, #1 80019e8: e000 b.n 80019ec 80019ea: 2300 movs r3, #0 } 80019ec: 4618 mov r0, r3 80019ee: 370c adds r7, #12 80019f0: 46bd mov sp, r7 80019f2: f85d 7b04 ldr.w r7, [sp], #4 80019f6: 4770 bx lr 080019f8 : * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) { 80019f8: b480 push {r7} 80019fa: b083 sub sp, #12 80019fc: af00 add r7, sp, #0 80019fe: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8001a00: 687b ldr r3, [r7, #4] 8001a02: 689a ldr r2, [r3, #8] 8001a04: 4b05 ldr r3, [pc, #20] @ (8001a1c ) 8001a06: 4013 ands r3, r2 8001a08: f043 5280 orr.w r2, r3, #268435456 @ 0x10000000 8001a0c: 687b ldr r3, [r7, #4] 8001a0e: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADVREGEN); } 8001a10: bf00 nop 8001a12: 370c adds r7, #12 8001a14: 46bd mov sp, r7 8001a16: f85d 7b04 ldr.w r7, [sp], #4 8001a1a: 4770 bx lr 8001a1c: 6fffffc0 .word 0x6fffffc0 08001a20 : * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx) { 8001a20: b480 push {r7} 8001a22: b083 sub sp, #12 8001a24: af00 add r7, sp, #0 8001a26: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); 8001a28: 687b ldr r3, [r7, #4] 8001a2a: 689b ldr r3, [r3, #8] 8001a2c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8001a30: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8001a34: d101 bne.n 8001a3a 8001a36: 2301 movs r3, #1 8001a38: e000 b.n 8001a3c 8001a3a: 2300 movs r3, #0 } 8001a3c: 4618 mov r0, r3 8001a3e: 370c adds r7, #12 8001a40: 46bd mov sp, r7 8001a42: f85d 7b04 ldr.w r7, [sp], #4 8001a46: 4770 bx lr 08001a48 : * @rmtoll CR ADEN LL_ADC_IsEnabled * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx) { 8001a48: b480 push {r7} 8001a4a: b083 sub sp, #12 8001a4c: af00 add r7, sp, #0 8001a4e: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8001a50: 687b ldr r3, [r7, #4] 8001a52: 689b ldr r3, [r3, #8] 8001a54: f003 0301 and.w r3, r3, #1 8001a58: 2b01 cmp r3, #1 8001a5a: d101 bne.n 8001a60 8001a5c: 2301 movs r3, #1 8001a5e: e000 b.n 8001a62 8001a60: 2300 movs r3, #0 } 8001a62: 4618 mov r0, r3 8001a64: 370c adds r7, #12 8001a66: 46bd mov sp, r7 8001a68: f85d 7b04 ldr.w r7, [sp], #4 8001a6c: 4770 bx lr 08001a6e : * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx) { 8001a6e: b480 push {r7} 8001a70: b083 sub sp, #12 8001a72: af00 add r7, sp, #0 8001a74: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8001a76: 687b ldr r3, [r7, #4] 8001a78: 689b ldr r3, [r3, #8] 8001a7a: f003 0304 and.w r3, r3, #4 8001a7e: 2b04 cmp r3, #4 8001a80: d101 bne.n 8001a86 8001a82: 2301 movs r3, #1 8001a84: e000 b.n 8001a88 8001a86: 2300 movs r3, #0 } 8001a88: 4618 mov r0, r3 8001a8a: 370c adds r7, #12 8001a8c: 46bd mov sp, r7 8001a8e: f85d 7b04 ldr.w r7, [sp], #4 8001a92: 4770 bx lr 08001a94 : * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx) { 8001a94: b480 push {r7} 8001a96: b083 sub sp, #12 8001a98: af00 add r7, sp, #0 8001a9a: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 8001a9c: 687b ldr r3, [r7, #4] 8001a9e: 689b ldr r3, [r3, #8] 8001aa0: f003 0308 and.w r3, r3, #8 8001aa4: 2b08 cmp r3, #8 8001aa6: d101 bne.n 8001aac 8001aa8: 2301 movs r3, #1 8001aaa: e000 b.n 8001aae 8001aac: 2300 movs r3, #0 } 8001aae: 4618 mov r0, r3 8001ab0: 370c adds r7, #12 8001ab2: 46bd mov sp, r7 8001ab4: f85d 7b04 ldr.w r7, [sp], #4 8001ab8: 4770 bx lr ... 08001abc : * without disabling the other ADCs. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { 8001abc: b590 push {r4, r7, lr} 8001abe: b089 sub sp, #36 @ 0x24 8001ac0: af00 add r7, sp, #0 8001ac2: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001ac4: 2300 movs r3, #0 8001ac6: 77fb strb r3, [r7, #31] uint32_t tmpCFGR; uint32_t tmp_adc_reg_is_conversion_on_going; __IO uint32_t wait_loop_index = 0UL; 8001ac8: 2300 movs r3, #0 8001aca: 60bb str r3, [r7, #8] uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check ADC handle */ if (hadc == NULL) 8001acc: 687b ldr r3, [r7, #4] 8001ace: 2b00 cmp r3, #0 8001ad0: d101 bne.n 8001ad6 { return HAL_ERROR; 8001ad2: 2301 movs r3, #1 8001ad4: e18f b.n 8001df6 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 8001ad6: 687b ldr r3, [r7, #4] 8001ad8: 68db ldr r3, [r3, #12] 8001ada: 2b00 cmp r3, #0 /* DISCEN and CONT bits cannot be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 8001adc: 687b ldr r3, [r7, #4] 8001ade: 6d5b ldr r3, [r3, #84] @ 0x54 8001ae0: 2b00 cmp r3, #0 8001ae2: d109 bne.n 8001af8 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 8001ae4: 6878 ldr r0, [r7, #4] 8001ae6: f7fe ff99 bl 8000a1c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8001aea: 687b ldr r3, [r7, #4] 8001aec: 2200 movs r2, #0 8001aee: 659a str r2, [r3, #88] @ 0x58 /* Initialize Lock */ hadc->Lock = HAL_UNLOCKED; 8001af0: 687b ldr r3, [r7, #4] 8001af2: 2200 movs r2, #0 8001af4: f883 2050 strb.w r2, [r3, #80] @ 0x50 } /* - Exit from deep-power-down mode and ADC voltage regulator enable */ if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) 8001af8: 687b ldr r3, [r7, #4] 8001afa: 681b ldr r3, [r3, #0] 8001afc: 4618 mov r0, r3 8001afe: f7ff ff67 bl 80019d0 8001b02: 4603 mov r3, r0 8001b04: 2b00 cmp r3, #0 8001b06: d004 beq.n 8001b12 { /* Disable ADC deep power down mode */ LL_ADC_DisableDeepPowerDown(hadc->Instance); 8001b08: 687b ldr r3, [r7, #4] 8001b0a: 681b ldr r3, [r3, #0] 8001b0c: 4618 mov r0, r3 8001b0e: f7ff ff4d bl 80019ac /* System was in deep power down mode, calibration must be relaunched or a previously saved calibration factor re-applied once the ADC voltage regulator is enabled */ } if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 8001b12: 687b ldr r3, [r7, #4] 8001b14: 681b ldr r3, [r3, #0] 8001b16: 4618 mov r0, r3 8001b18: f7ff ff82 bl 8001a20 8001b1c: 4603 mov r3, r0 8001b1e: 2b00 cmp r3, #0 8001b20: d114 bne.n 8001b4c { /* Enable ADC internal voltage regulator */ LL_ADC_EnableInternalRegulator(hadc->Instance); 8001b22: 687b ldr r3, [r7, #4] 8001b24: 681b ldr r3, [r3, #0] 8001b26: 4618 mov r0, r3 8001b28: f7ff ff66 bl 80019f8 /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8001b2c: 4b87 ldr r3, [pc, #540] @ (8001d4c ) 8001b2e: 681b ldr r3, [r3, #0] 8001b30: 099b lsrs r3, r3, #6 8001b32: 4a87 ldr r2, [pc, #540] @ (8001d50 ) 8001b34: fba2 2303 umull r2, r3, r2, r3 8001b38: 099b lsrs r3, r3, #6 8001b3a: 3301 adds r3, #1 8001b3c: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 8001b3e: e002 b.n 8001b46 { wait_loop_index--; 8001b40: 68bb ldr r3, [r7, #8] 8001b42: 3b01 subs r3, #1 8001b44: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 8001b46: 68bb ldr r3, [r7, #8] 8001b48: 2b00 cmp r3, #0 8001b4a: d1f9 bne.n 8001b40 } /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 8001b4c: 687b ldr r3, [r7, #4] 8001b4e: 681b ldr r3, [r3, #0] 8001b50: 4618 mov r0, r3 8001b52: f7ff ff65 bl 8001a20 8001b56: 4603 mov r3, r0 8001b58: 2b00 cmp r3, #0 8001b5a: d10d bne.n 8001b78 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001b5c: 687b ldr r3, [r7, #4] 8001b5e: 6d5b ldr r3, [r3, #84] @ 0x54 8001b60: f043 0210 orr.w r2, r3, #16 8001b64: 687b ldr r3, [r7, #4] 8001b66: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001b68: 687b ldr r3, [r7, #4] 8001b6a: 6d9b ldr r3, [r3, #88] @ 0x58 8001b6c: f043 0201 orr.w r2, r3, #1 8001b70: 687b ldr r3, [r7, #4] 8001b72: 659a str r2, [r3, #88] @ 0x58 tmp_hal_status = HAL_ERROR; 8001b74: 2301 movs r3, #1 8001b76: 77fb strb r3, [r7, #31] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 8001b78: 687b ldr r3, [r7, #4] 8001b7a: 681b ldr r3, [r3, #0] 8001b7c: 4618 mov r0, r3 8001b7e: f7ff ff76 bl 8001a6e 8001b82: 6178 str r0, [r7, #20] if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) 8001b84: 687b ldr r3, [r7, #4] 8001b86: 6d5b ldr r3, [r3, #84] @ 0x54 8001b88: f003 0310 and.w r3, r3, #16 8001b8c: 2b00 cmp r3, #0 8001b8e: f040 8129 bne.w 8001de4 && (tmp_adc_reg_is_conversion_on_going == 0UL) 8001b92: 697b ldr r3, [r7, #20] 8001b94: 2b00 cmp r3, #0 8001b96: f040 8125 bne.w 8001de4 ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8001b9a: 687b ldr r3, [r7, #4] 8001b9c: 6d5b ldr r3, [r3, #84] @ 0x54 8001b9e: f423 7381 bic.w r3, r3, #258 @ 0x102 8001ba2: f043 0202 orr.w r2, r3, #2 8001ba6: 687b ldr r3, [r7, #4] 8001ba8: 655a str r2, [r3, #84] @ 0x54 /* Configuration of common ADC parameters */ /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - clock configuration */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8001baa: 687b ldr r3, [r7, #4] 8001bac: 681b ldr r3, [r3, #0] 8001bae: 4618 mov r0, r3 8001bb0: f7ff ff4a bl 8001a48 8001bb4: 4603 mov r3, r0 8001bb6: 2b00 cmp r3, #0 8001bb8: d136 bne.n 8001c28 { if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8001bba: 687b ldr r3, [r7, #4] 8001bbc: 681b ldr r3, [r3, #0] 8001bbe: 4a65 ldr r2, [pc, #404] @ (8001d54 ) 8001bc0: 4293 cmp r3, r2 8001bc2: d004 beq.n 8001bce 8001bc4: 687b ldr r3, [r7, #4] 8001bc6: 681b ldr r3, [r3, #0] 8001bc8: 4a63 ldr r2, [pc, #396] @ (8001d58 ) 8001bca: 4293 cmp r3, r2 8001bcc: d10e bne.n 8001bec 8001bce: 4861 ldr r0, [pc, #388] @ (8001d54 ) 8001bd0: f7ff ff3a bl 8001a48 8001bd4: 4604 mov r4, r0 8001bd6: 4860 ldr r0, [pc, #384] @ (8001d58 ) 8001bd8: f7ff ff36 bl 8001a48 8001bdc: 4603 mov r3, r0 8001bde: 4323 orrs r3, r4 8001be0: 2b00 cmp r3, #0 8001be2: bf0c ite eq 8001be4: 2301 moveq r3, #1 8001be6: 2300 movne r3, #0 8001be8: b2db uxtb r3, r3 8001bea: e008 b.n 8001bfe 8001bec: 485b ldr r0, [pc, #364] @ (8001d5c ) 8001bee: f7ff ff2b bl 8001a48 8001bf2: 4603 mov r3, r0 8001bf4: 2b00 cmp r3, #0 8001bf6: bf0c ite eq 8001bf8: 2301 moveq r3, #1 8001bfa: 2300 movne r3, #0 8001bfc: b2db uxtb r3, r3 8001bfe: 2b00 cmp r3, #0 8001c00: d012 beq.n 8001c28 /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */ /* HAL_ADCEx_MultiModeConfigChannel() ) */ /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() or */ /* HAL_ADCEx_InjectedConfigChannel() ) */ LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); 8001c02: 687b ldr r3, [r7, #4] 8001c04: 681b ldr r3, [r3, #0] 8001c06: 4a53 ldr r2, [pc, #332] @ (8001d54 ) 8001c08: 4293 cmp r3, r2 8001c0a: d004 beq.n 8001c16 8001c0c: 687b ldr r3, [r7, #4] 8001c0e: 681b ldr r3, [r3, #0] 8001c10: 4a51 ldr r2, [pc, #324] @ (8001d58 ) 8001c12: 4293 cmp r3, r2 8001c14: d101 bne.n 8001c1a 8001c16: 4a52 ldr r2, [pc, #328] @ (8001d60 ) 8001c18: e000 b.n 8001c1c 8001c1a: 4a52 ldr r2, [pc, #328] @ (8001d64 ) 8001c1c: 687b ldr r3, [r7, #4] 8001c1e: 685b ldr r3, [r3, #4] 8001c20: 4619 mov r1, r3 8001c22: 4610 mov r0, r2 8001c24: f7ff fd8c bl 8001740 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); } #else if ((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution)) 8001c28: f7ff fd68 bl 80016fc 8001c2c: 4603 mov r3, r0 8001c2e: f241 0203 movw r2, #4099 @ 0x1003 8001c32: 4293 cmp r3, r2 8001c34: d914 bls.n 8001c60 8001c36: 687b ldr r3, [r7, #4] 8001c38: 689b ldr r3, [r3, #8] 8001c3a: 2b10 cmp r3, #16 8001c3c: d110 bne.n 8001c60 { /* for STM32H7 silicon rev.B and above , ADC_CFGR_RES value for 8bits resolution is : b111 */ tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8001c3e: 687b ldr r3, [r7, #4] 8001c40: 7d5b ldrb r3, [r3, #21] 8001c42: 035a lsls r2, r3, #13 hadc->Init.Overrun | 8001c44: 687b ldr r3, [r7, #4] 8001c46: 6b1b ldr r3, [r3, #48] @ 0x30 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8001c48: 431a orrs r2, r3 hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) | 8001c4a: 687b ldr r3, [r7, #4] 8001c4c: 689b ldr r3, [r3, #8] hadc->Init.Overrun | 8001c4e: 431a orrs r2, r3 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 8001c50: 687b ldr r3, [r7, #4] 8001c52: 7f1b ldrb r3, [r3, #28] 8001c54: 041b lsls r3, r3, #16 hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) | 8001c56: 4313 orrs r3, r2 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8001c58: f043 030c orr.w r3, r3, #12 8001c5c: 61bb str r3, [r7, #24] 8001c5e: e00d b.n 8001c7c } else { tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8001c60: 687b ldr r3, [r7, #4] 8001c62: 7d5b ldrb r3, [r3, #21] 8001c64: 035a lsls r2, r3, #13 hadc->Init.Overrun | 8001c66: 687b ldr r3, [r7, #4] 8001c68: 6b1b ldr r3, [r3, #48] @ 0x30 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8001c6a: 431a orrs r2, r3 hadc->Init.Resolution | 8001c6c: 687b ldr r3, [r7, #4] 8001c6e: 689b ldr r3, [r3, #8] hadc->Init.Overrun | 8001c70: 431a orrs r2, r3 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 8001c72: 687b ldr r3, [r7, #4] 8001c74: 7f1b ldrb r3, [r3, #28] 8001c76: 041b lsls r3, r3, #16 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8001c78: 4313 orrs r3, r2 8001c7a: 61bb str r3, [r7, #24] } #endif /* ADC_VER_V5_3 */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 8001c7c: 687b ldr r3, [r7, #4] 8001c7e: 7f1b ldrb r3, [r3, #28] 8001c80: 2b01 cmp r3, #1 8001c82: d106 bne.n 8001c92 { tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); 8001c84: 687b ldr r3, [r7, #4] 8001c86: 6a1b ldr r3, [r3, #32] 8001c88: 3b01 subs r3, #1 8001c8a: 045b lsls r3, r3, #17 8001c8c: 69ba ldr r2, [r7, #24] 8001c8e: 4313 orrs r3, r2 8001c90: 61bb str r3, [r7, #24] /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 8001c92: 687b ldr r3, [r7, #4] 8001c94: 6a5b ldr r3, [r3, #36] @ 0x24 8001c96: 2b00 cmp r3, #0 8001c98: d009 beq.n 8001cae { tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 8001c9a: 687b ldr r3, [r7, #4] 8001c9c: 6a5b ldr r3, [r3, #36] @ 0x24 8001c9e: f403 7278 and.w r2, r3, #992 @ 0x3e0 | hadc->Init.ExternalTrigConvEdge 8001ca2: 687b ldr r3, [r7, #4] 8001ca4: 6a9b ldr r3, [r3, #40] @ 0x28 8001ca6: 4313 orrs r3, r2 tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 8001ca8: 69ba ldr r2, [r7, #24] 8001caa: 4313 orrs r3, r2 8001cac: 61bb str r3, [r7, #24] /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); } #else /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); 8001cae: 687b ldr r3, [r7, #4] 8001cb0: 681b ldr r3, [r3, #0] 8001cb2: 68da ldr r2, [r3, #12] 8001cb4: 4b2c ldr r3, [pc, #176] @ (8001d68 ) 8001cb6: 4013 ands r3, r2 8001cb8: 687a ldr r2, [r7, #4] 8001cba: 6812 ldr r2, [r2, #0] 8001cbc: 69b9 ldr r1, [r7, #24] 8001cbe: 430b orrs r3, r1 8001cc0: 60d3 str r3, [r2, #12] /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ /* - Conversion data management Init.ConversionDataManagement */ /* - LowPowerAutoWait feature Init.LowPowerAutoWait */ /* - Oversampling parameters Init.Oversampling */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 8001cc2: 687b ldr r3, [r7, #4] 8001cc4: 681b ldr r3, [r3, #0] 8001cc6: 4618 mov r0, r3 8001cc8: f7ff fed1 bl 8001a6e 8001ccc: 6138 str r0, [r7, #16] tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); 8001cce: 687b ldr r3, [r7, #4] 8001cd0: 681b ldr r3, [r3, #0] 8001cd2: 4618 mov r0, r3 8001cd4: f7ff fede bl 8001a94 8001cd8: 60f8 str r0, [r7, #12] if ((tmp_adc_is_conversion_on_going_regular == 0UL) 8001cda: 693b ldr r3, [r7, #16] 8001cdc: 2b00 cmp r3, #0 8001cde: d15f bne.n 8001da0 && (tmp_adc_is_conversion_on_going_injected == 0UL) 8001ce0: 68fb ldr r3, [r7, #12] 8001ce2: 2b00 cmp r3, #0 8001ce4: d15c bne.n 8001da0 ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); } #else tmpCFGR = ( ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 8001ce6: 687b ldr r3, [r7, #4] 8001ce8: 7d1b ldrb r3, [r3, #20] 8001cea: 039a lsls r2, r3, #14 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); 8001cec: 687b ldr r3, [r7, #4] 8001cee: 6adb ldr r3, [r3, #44] @ 0x2c tmpCFGR = ( 8001cf0: 4313 orrs r3, r2 8001cf2: 61bb str r3, [r7, #24] #endif MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); 8001cf4: 687b ldr r3, [r7, #4] 8001cf6: 681b ldr r3, [r3, #0] 8001cf8: 68da ldr r2, [r3, #12] 8001cfa: 4b1c ldr r3, [pc, #112] @ (8001d6c ) 8001cfc: 4013 ands r3, r2 8001cfe: 687a ldr r2, [r7, #4] 8001d00: 6812 ldr r2, [r2, #0] 8001d02: 69b9 ldr r1, [r7, #24] 8001d04: 430b orrs r3, r1 8001d06: 60d3 str r3, [r2, #12] if (hadc->Init.OversamplingMode == ENABLE) 8001d08: 687b ldr r3, [r7, #4] 8001d0a: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 8001d0e: 2b01 cmp r3, #1 8001d10: d130 bne.n 8001d74 #endif assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset)); if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START) 8001d12: 687b ldr r3, [r7, #4] 8001d14: 6a5b ldr r3, [r3, #36] @ 0x24 8001d16: 2b00 cmp r3, #0 /* - Oversampling Ratio */ /* - Right bit shift */ /* - Left bit shift */ /* - Triggered mode */ /* - Oversampling mode (continued/resumed) */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS, 8001d18: 687b ldr r3, [r7, #4] 8001d1a: 681b ldr r3, [r3, #0] 8001d1c: 691a ldr r2, [r3, #16] 8001d1e: 4b14 ldr r3, [pc, #80] @ (8001d70 ) 8001d20: 4013 ands r3, r2 8001d22: 687a ldr r2, [r7, #4] 8001d24: 6bd2 ldr r2, [r2, #60] @ 0x3c 8001d26: 3a01 subs r2, #1 8001d28: 0411 lsls r1, r2, #16 8001d2a: 687a ldr r2, [r7, #4] 8001d2c: 6c12 ldr r2, [r2, #64] @ 0x40 8001d2e: 4311 orrs r1, r2 8001d30: 687a ldr r2, [r7, #4] 8001d32: 6c52 ldr r2, [r2, #68] @ 0x44 8001d34: 4311 orrs r1, r2 8001d36: 687a ldr r2, [r7, #4] 8001d38: 6c92 ldr r2, [r2, #72] @ 0x48 8001d3a: 430a orrs r2, r1 8001d3c: 431a orrs r2, r3 8001d3e: 687b ldr r3, [r7, #4] 8001d40: 681b ldr r3, [r3, #0] 8001d42: f042 0201 orr.w r2, r2, #1 8001d46: 611a str r2, [r3, #16] 8001d48: e01c b.n 8001d84 8001d4a: bf00 nop 8001d4c: 24000000 .word 0x24000000 8001d50: 053e2d63 .word 0x053e2d63 8001d54: 40022000 .word 0x40022000 8001d58: 40022100 .word 0x40022100 8001d5c: 58026000 .word 0x58026000 8001d60: 40022300 .word 0x40022300 8001d64: 58026300 .word 0x58026300 8001d68: fff0c003 .word 0xfff0c003 8001d6c: ffffbffc .word 0xffffbffc 8001d70: fc00f81e .word 0xfc00f81e } else { /* Disable ADC oversampling scope on ADC group regular */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); 8001d74: 687b ldr r3, [r7, #4] 8001d76: 681b ldr r3, [r3, #0] 8001d78: 691a ldr r2, [r3, #16] 8001d7a: 687b ldr r3, [r7, #4] 8001d7c: 681b ldr r3, [r3, #0] 8001d7e: f022 0201 bic.w r2, r2, #1 8001d82: 611a str r2, [r3, #16] } /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift); 8001d84: 687b ldr r3, [r7, #4] 8001d86: 681b ldr r3, [r3, #0] 8001d88: 691b ldr r3, [r3, #16] 8001d8a: f023 4170 bic.w r1, r3, #4026531840 @ 0xf0000000 8001d8e: 687b ldr r3, [r7, #4] 8001d90: 6b5a ldr r2, [r3, #52] @ 0x34 8001d92: 687b ldr r3, [r7, #4] 8001d94: 681b ldr r3, [r3, #0] 8001d96: 430a orrs r2, r1 8001d98: 611a str r2, [r3, #16] /* Configure the BOOST Mode */ ADC_ConfigureBoostMode(hadc); } #else /* Configure the BOOST Mode */ ADC_ConfigureBoostMode(hadc); 8001d9a: 6878 ldr r0, [r7, #4] 8001d9c: f000 fb20 bl 80023e0 /* Note: Scan mode is not present by hardware on this device, but */ /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion". */ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) 8001da0: 687b ldr r3, [r7, #4] 8001da2: 68db ldr r3, [r3, #12] 8001da4: 2b01 cmp r3, #1 8001da6: d10c bne.n 8001dc2 { /* Set number of ranks in regular group sequencer */ MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); 8001da8: 687b ldr r3, [r7, #4] 8001daa: 681b ldr r3, [r3, #0] 8001dac: 6b1b ldr r3, [r3, #48] @ 0x30 8001dae: f023 010f bic.w r1, r3, #15 8001db2: 687b ldr r3, [r7, #4] 8001db4: 699b ldr r3, [r3, #24] 8001db6: 1e5a subs r2, r3, #1 8001db8: 687b ldr r3, [r7, #4] 8001dba: 681b ldr r3, [r3, #0] 8001dbc: 430a orrs r2, r1 8001dbe: 631a str r2, [r3, #48] @ 0x30 8001dc0: e007 b.n 8001dd2 } else { CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); 8001dc2: 687b ldr r3, [r7, #4] 8001dc4: 681b ldr r3, [r3, #0] 8001dc6: 6b1a ldr r2, [r3, #48] @ 0x30 8001dc8: 687b ldr r3, [r7, #4] 8001dca: 681b ldr r3, [r3, #0] 8001dcc: f022 020f bic.w r2, r2, #15 8001dd0: 631a str r2, [r3, #48] @ 0x30 } /* Initialize the ADC state */ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); 8001dd2: 687b ldr r3, [r7, #4] 8001dd4: 6d5b ldr r3, [r3, #84] @ 0x54 8001dd6: f023 0303 bic.w r3, r3, #3 8001dda: f043 0201 orr.w r2, r3, #1 8001dde: 687b ldr r3, [r7, #4] 8001de0: 655a str r2, [r3, #84] @ 0x54 8001de2: e007 b.n 8001df4 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001de4: 687b ldr r3, [r7, #4] 8001de6: 6d5b ldr r3, [r3, #84] @ 0x54 8001de8: f043 0210 orr.w r2, r3, #16 8001dec: 687b ldr r3, [r7, #4] 8001dee: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8001df0: 2301 movs r3, #1 8001df2: 77fb strb r3, [r7, #31] } /* Return function status */ return tmp_hal_status; 8001df4: 7ffb ldrb r3, [r7, #31] } 8001df6: 4618 mov r0, r3 8001df8: 3724 adds r7, #36 @ 0x24 8001dfa: 46bd mov sp, r7 8001dfc: bd90 pop {r4, r7, pc} 8001dfe: bf00 nop 08001e00 : * @param hadc ADC handle * @param sConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) { 8001e00: b590 push {r4, r7, lr} 8001e02: b08d sub sp, #52 @ 0x34 8001e04: af00 add r7, sp, #0 8001e06: 6078 str r0, [r7, #4] 8001e08: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001e0a: 2300 movs r3, #0 8001e0c: f887 302f strb.w r3, [r7, #47] @ 0x2f uint32_t tmpOffsetShifted; uint32_t tmp_config_internal_channel; __IO uint32_t wait_loop_index = 0; 8001e10: 2300 movs r3, #0 8001e12: 60fb str r3, [r7, #12] /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is ignored (considered as reset) */ assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); /* Verification of channel number */ if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) 8001e14: 683b ldr r3, [r7, #0] 8001e16: 68db ldr r3, [r3, #12] 8001e18: 4a65 ldr r2, [pc, #404] @ (8001fb0 ) 8001e1a: 4293 cmp r3, r2 } #endif } /* Process locked */ __HAL_LOCK(hadc); 8001e1c: 687b ldr r3, [r7, #4] 8001e1e: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8001e22: 2b01 cmp r3, #1 8001e24: d101 bne.n 8001e2a 8001e26: 2302 movs r3, #2 8001e28: e2c7 b.n 80023ba 8001e2a: 687b ldr r3, [r7, #4] 8001e2c: 2201 movs r2, #1 8001e2e: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel rank */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 8001e32: 687b ldr r3, [r7, #4] 8001e34: 681b ldr r3, [r3, #0] 8001e36: 4618 mov r0, r3 8001e38: f7ff fe19 bl 8001a6e 8001e3c: 4603 mov r3, r0 8001e3e: 2b00 cmp r3, #0 8001e40: f040 82ac bne.w 800239c { if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))) 8001e44: 683b ldr r3, [r7, #0] 8001e46: 681b ldr r3, [r3, #0] 8001e48: 2b00 cmp r3, #0 8001e4a: db2c blt.n 8001ea6 /* ADC channels preselection */ hadc->Instance->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); } #else /* ADC channels preselection */ hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); 8001e4c: 683b ldr r3, [r7, #0] 8001e4e: 681b ldr r3, [r3, #0] 8001e50: f3c3 0313 ubfx r3, r3, #0, #20 8001e54: 2b00 cmp r3, #0 8001e56: d108 bne.n 8001e6a 8001e58: 683b ldr r3, [r7, #0] 8001e5a: 681b ldr r3, [r3, #0] 8001e5c: 0e9b lsrs r3, r3, #26 8001e5e: f003 031f and.w r3, r3, #31 8001e62: 2201 movs r2, #1 8001e64: fa02 f303 lsl.w r3, r2, r3 8001e68: e016 b.n 8001e98 8001e6a: 683b ldr r3, [r7, #0] 8001e6c: 681b ldr r3, [r3, #0] 8001e6e: 617b str r3, [r7, #20] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8001e70: 697b ldr r3, [r7, #20] 8001e72: fa93 f3a3 rbit r3, r3 8001e76: 613b str r3, [r7, #16] return result; 8001e78: 693b ldr r3, [r7, #16] 8001e7a: 61bb str r3, [r7, #24] if (value == 0U) 8001e7c: 69bb ldr r3, [r7, #24] 8001e7e: 2b00 cmp r3, #0 8001e80: d101 bne.n 8001e86 return 32U; 8001e82: 2320 movs r3, #32 8001e84: e003 b.n 8001e8e return __builtin_clz(value); 8001e86: 69bb ldr r3, [r7, #24] 8001e88: fab3 f383 clz r3, r3 8001e8c: b2db uxtb r3, r3 8001e8e: f003 031f and.w r3, r3, #31 8001e92: 2201 movs r2, #1 8001e94: fa02 f303 lsl.w r3, r2, r3 8001e98: 687a ldr r2, [r7, #4] 8001e9a: 6812 ldr r2, [r2, #0] 8001e9c: 69d1 ldr r1, [r2, #28] 8001e9e: 687a ldr r2, [r7, #4] 8001ea0: 6812 ldr r2, [r2, #0] 8001ea2: 430b orrs r3, r1 8001ea4: 61d3 str r3, [r2, #28] #endif /* ADC_VER_V5_V90 */ } /* Set ADC group regular sequence: channel on the selected scan sequence rank */ LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); 8001ea6: 687b ldr r3, [r7, #4] 8001ea8: 6818 ldr r0, [r3, #0] 8001eaa: 683b ldr r3, [r7, #0] 8001eac: 6859 ldr r1, [r3, #4] 8001eae: 683b ldr r3, [r7, #0] 8001eb0: 681b ldr r3, [r3, #0] 8001eb2: 461a mov r2, r3 8001eb4: f7ff fcff bl 80018b6 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel sampling time */ /* - Channel offset */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 8001eb8: 687b ldr r3, [r7, #4] 8001eba: 681b ldr r3, [r3, #0] 8001ebc: 4618 mov r0, r3 8001ebe: f7ff fdd6 bl 8001a6e 8001ec2: 62b8 str r0, [r7, #40] @ 0x28 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); 8001ec4: 687b ldr r3, [r7, #4] 8001ec6: 681b ldr r3, [r3, #0] 8001ec8: 4618 mov r0, r3 8001eca: f7ff fde3 bl 8001a94 8001ece: 6278 str r0, [r7, #36] @ 0x24 if ((tmp_adc_is_conversion_on_going_regular == 0UL) 8001ed0: 6abb ldr r3, [r7, #40] @ 0x28 8001ed2: 2b00 cmp r3, #0 8001ed4: f040 80b8 bne.w 8002048 && (tmp_adc_is_conversion_on_going_injected == 0UL) 8001ed8: 6a7b ldr r3, [r7, #36] @ 0x24 8001eda: 2b00 cmp r3, #0 8001edc: f040 80b4 bne.w 8002048 ) { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); 8001ee0: 687b ldr r3, [r7, #4] 8001ee2: 6818 ldr r0, [r3, #0] 8001ee4: 683b ldr r3, [r7, #0] 8001ee6: 6819 ldr r1, [r3, #0] 8001ee8: 683b ldr r3, [r7, #0] 8001eea: 689b ldr r3, [r3, #8] 8001eec: 461a mov r2, r3 8001eee: f7ff fd0e bl 800190e tmpOffsetShifted = ADC3_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); } else #endif /* ADC_VER_V5_V90 */ { tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); 8001ef2: 4b30 ldr r3, [pc, #192] @ (8001fb4 ) 8001ef4: 681b ldr r3, [r3, #0] 8001ef6: f003 4370 and.w r3, r3, #4026531840 @ 0xf0000000 8001efa: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8001efe: d10b bne.n 8001f18 8001f00: 683b ldr r3, [r7, #0] 8001f02: 695a ldr r2, [r3, #20] 8001f04: 687b ldr r3, [r7, #4] 8001f06: 681b ldr r3, [r3, #0] 8001f08: 68db ldr r3, [r3, #12] 8001f0a: 089b lsrs r3, r3, #2 8001f0c: f003 0307 and.w r3, r3, #7 8001f10: 005b lsls r3, r3, #1 8001f12: fa02 f303 lsl.w r3, r2, r3 8001f16: e01d b.n 8001f54 8001f18: 687b ldr r3, [r7, #4] 8001f1a: 681b ldr r3, [r3, #0] 8001f1c: 68db ldr r3, [r3, #12] 8001f1e: f003 0310 and.w r3, r3, #16 8001f22: 2b00 cmp r3, #0 8001f24: d10b bne.n 8001f3e 8001f26: 683b ldr r3, [r7, #0] 8001f28: 695a ldr r2, [r3, #20] 8001f2a: 687b ldr r3, [r7, #4] 8001f2c: 681b ldr r3, [r3, #0] 8001f2e: 68db ldr r3, [r3, #12] 8001f30: 089b lsrs r3, r3, #2 8001f32: f003 0307 and.w r3, r3, #7 8001f36: 005b lsls r3, r3, #1 8001f38: fa02 f303 lsl.w r3, r2, r3 8001f3c: e00a b.n 8001f54 8001f3e: 683b ldr r3, [r7, #0] 8001f40: 695a ldr r2, [r3, #20] 8001f42: 687b ldr r3, [r7, #4] 8001f44: 681b ldr r3, [r3, #0] 8001f46: 68db ldr r3, [r3, #12] 8001f48: 089b lsrs r3, r3, #2 8001f4a: f003 0304 and.w r3, r3, #4 8001f4e: 005b lsls r3, r3, #1 8001f50: fa02 f303 lsl.w r3, r2, r3 8001f54: 623b str r3, [r7, #32] } if (sConfig->OffsetNumber != ADC_OFFSET_NONE) 8001f56: 683b ldr r3, [r7, #0] 8001f58: 691b ldr r3, [r3, #16] 8001f5a: 2b04 cmp r3, #4 8001f5c: d02c beq.n 8001fb8 { /* Set ADC selected offset number */ LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted); 8001f5e: 687b ldr r3, [r7, #4] 8001f60: 6818 ldr r0, [r3, #0] 8001f62: 683b ldr r3, [r7, #0] 8001f64: 6919 ldr r1, [r3, #16] 8001f66: 683b ldr r3, [r7, #0] 8001f68: 681a ldr r2, [r3, #0] 8001f6a: 6a3b ldr r3, [r7, #32] 8001f6c: f7ff fc4f bl 800180e else #endif /* ADC_VER_V5_V90 */ { assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSignedSaturation)); /* Set ADC selected offset signed saturation */ LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); 8001f70: 687b ldr r3, [r7, #4] 8001f72: 6818 ldr r0, [r3, #0] 8001f74: 683b ldr r3, [r7, #0] 8001f76: 6919 ldr r1, [r3, #16] 8001f78: 683b ldr r3, [r7, #0] 8001f7a: 7e5b ldrb r3, [r3, #25] 8001f7c: 2b01 cmp r3, #1 8001f7e: d102 bne.n 8001f86 8001f80: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 8001f84: e000 b.n 8001f88 8001f86: 2300 movs r3, #0 8001f88: 461a mov r2, r3 8001f8a: f7ff fc79 bl 8001880 assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetRightShift)); /* Set ADC selected offset right shift */ LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE); 8001f8e: 687b ldr r3, [r7, #4] 8001f90: 6818 ldr r0, [r3, #0] 8001f92: 683b ldr r3, [r7, #0] 8001f94: 6919 ldr r1, [r3, #16] 8001f96: 683b ldr r3, [r7, #0] 8001f98: 7e1b ldrb r3, [r3, #24] 8001f9a: 2b01 cmp r3, #1 8001f9c: d102 bne.n 8001fa4 8001f9e: f44f 6300 mov.w r3, #2048 @ 0x800 8001fa2: e000 b.n 8001fa6 8001fa4: 2300 movs r3, #0 8001fa6: 461a mov r2, r3 8001fa8: f7ff fc51 bl 800184e 8001fac: e04c b.n 8002048 8001fae: bf00 nop 8001fb0: 47ff0000 .word 0x47ff0000 8001fb4: 5c001000 .word 0x5c001000 } } else #endif /* ADC_VER_V5_V90 */ { if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8001fb8: 687b ldr r3, [r7, #4] 8001fba: 681b ldr r3, [r3, #0] 8001fbc: 6e1b ldr r3, [r3, #96] @ 0x60 8001fbe: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8001fc2: 683b ldr r3, [r7, #0] 8001fc4: 681b ldr r3, [r3, #0] 8001fc6: 069b lsls r3, r3, #26 8001fc8: 429a cmp r2, r3 8001fca: d107 bne.n 8001fdc { CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE); 8001fcc: 687b ldr r3, [r7, #4] 8001fce: 681b ldr r3, [r3, #0] 8001fd0: 6e1a ldr r2, [r3, #96] @ 0x60 8001fd2: 687b ldr r3, [r7, #4] 8001fd4: 681b ldr r3, [r3, #0] 8001fd6: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 8001fda: 661a str r2, [r3, #96] @ 0x60 } if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8001fdc: 687b ldr r3, [r7, #4] 8001fde: 681b ldr r3, [r3, #0] 8001fe0: 6e5b ldr r3, [r3, #100] @ 0x64 8001fe2: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8001fe6: 683b ldr r3, [r7, #0] 8001fe8: 681b ldr r3, [r3, #0] 8001fea: 069b lsls r3, r3, #26 8001fec: 429a cmp r2, r3 8001fee: d107 bne.n 8002000 { CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE); 8001ff0: 687b ldr r3, [r7, #4] 8001ff2: 681b ldr r3, [r3, #0] 8001ff4: 6e5a ldr r2, [r3, #100] @ 0x64 8001ff6: 687b ldr r3, [r7, #4] 8001ff8: 681b ldr r3, [r3, #0] 8001ffa: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 8001ffe: 665a str r2, [r3, #100] @ 0x64 } if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8002000: 687b ldr r3, [r7, #4] 8002002: 681b ldr r3, [r3, #0] 8002004: 6e9b ldr r3, [r3, #104] @ 0x68 8002006: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 800200a: 683b ldr r3, [r7, #0] 800200c: 681b ldr r3, [r3, #0] 800200e: 069b lsls r3, r3, #26 8002010: 429a cmp r2, r3 8002012: d107 bne.n 8002024 { CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE); 8002014: 687b ldr r3, [r7, #4] 8002016: 681b ldr r3, [r3, #0] 8002018: 6e9a ldr r2, [r3, #104] @ 0x68 800201a: 687b ldr r3, [r7, #4] 800201c: 681b ldr r3, [r3, #0] 800201e: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 8002022: 669a str r2, [r3, #104] @ 0x68 } if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8002024: 687b ldr r3, [r7, #4] 8002026: 681b ldr r3, [r3, #0] 8002028: 6edb ldr r3, [r3, #108] @ 0x6c 800202a: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 800202e: 683b ldr r3, [r7, #0] 8002030: 681b ldr r3, [r3, #0] 8002032: 069b lsls r3, r3, #26 8002034: 429a cmp r2, r3 8002036: d107 bne.n 8002048 { CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE); 8002038: 687b ldr r3, [r7, #4] 800203a: 681b ldr r3, [r3, #0] 800203c: 6eda ldr r2, [r3, #108] @ 0x6c 800203e: 687b ldr r3, [r7, #4] 8002040: 681b ldr r3, [r3, #0] 8002042: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 8002046: 66da str r2, [r3, #108] @ 0x6c /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ /* - Internal measurement channels: Vbat/VrefInt/TempSensor */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8002048: 687b ldr r3, [r7, #4] 800204a: 681b ldr r3, [r3, #0] 800204c: 4618 mov r0, r3 800204e: f7ff fcfb bl 8001a48 8002052: 4603 mov r3, r0 8002054: 2b00 cmp r3, #0 8002056: f040 81aa bne.w 80023ae { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff); 800205a: 687b ldr r3, [r7, #4] 800205c: 6818 ldr r0, [r3, #0] 800205e: 683b ldr r3, [r7, #0] 8002060: 6819 ldr r1, [r3, #0] 8002062: 683b ldr r3, [r7, #0] 8002064: 68db ldr r3, [r3, #12] 8002066: 461a mov r2, r3 8002068: f7ff fc7c bl 8001964 /* Configuration of differential mode */ if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) 800206c: 683b ldr r3, [r7, #0] 800206e: 68db ldr r3, [r3, #12] 8002070: 4a87 ldr r2, [pc, #540] @ (8002290 ) 8002072: 4293 cmp r3, r2 8002074: f040 809a bne.w 80021ac { /* Set ADC channel preselection of corresponding negative channel */ LL_ADC_SetChannelPreselection(hadc->Instance, ADC_CHANNEL_DIFF_NEG_INPUT(hadc, sConfig->Channel)); 8002078: 687b ldr r3, [r7, #4] 800207a: 681a ldr r2, [r3, #0] 800207c: 687b ldr r3, [r7, #4] 800207e: 681b ldr r3, [r3, #0] 8002080: 4984 ldr r1, [pc, #528] @ (8002294 ) 8002082: 428b cmp r3, r1 8002084: d147 bne.n 8002116 8002086: 683b ldr r3, [r7, #0] 8002088: 681b ldr r3, [r3, #0] 800208a: 4983 ldr r1, [pc, #524] @ (8002298 ) 800208c: 428b cmp r3, r1 800208e: d040 beq.n 8002112 8002090: 683b ldr r3, [r7, #0] 8002092: 681b ldr r3, [r3, #0] 8002094: 4981 ldr r1, [pc, #516] @ (800229c ) 8002096: 428b cmp r3, r1 8002098: d039 beq.n 800210e 800209a: 683b ldr r3, [r7, #0] 800209c: 681b ldr r3, [r3, #0] 800209e: 4980 ldr r1, [pc, #512] @ (80022a0 ) 80020a0: 428b cmp r3, r1 80020a2: d032 beq.n 800210a 80020a4: 683b ldr r3, [r7, #0] 80020a6: 681b ldr r3, [r3, #0] 80020a8: 497e ldr r1, [pc, #504] @ (80022a4 ) 80020aa: 428b cmp r3, r1 80020ac: d02b beq.n 8002106 80020ae: 683b ldr r3, [r7, #0] 80020b0: 681b ldr r3, [r3, #0] 80020b2: 497d ldr r1, [pc, #500] @ (80022a8 ) 80020b4: 428b cmp r3, r1 80020b6: d024 beq.n 8002102 80020b8: 683b ldr r3, [r7, #0] 80020ba: 681b ldr r3, [r3, #0] 80020bc: 497b ldr r1, [pc, #492] @ (80022ac ) 80020be: 428b cmp r3, r1 80020c0: d01d beq.n 80020fe 80020c2: 683b ldr r3, [r7, #0] 80020c4: 681b ldr r3, [r3, #0] 80020c6: 497a ldr r1, [pc, #488] @ (80022b0 ) 80020c8: 428b cmp r3, r1 80020ca: d016 beq.n 80020fa 80020cc: 683b ldr r3, [r7, #0] 80020ce: 681b ldr r3, [r3, #0] 80020d0: 4978 ldr r1, [pc, #480] @ (80022b4 ) 80020d2: 428b cmp r3, r1 80020d4: d00f beq.n 80020f6 80020d6: 683b ldr r3, [r7, #0] 80020d8: 681b ldr r3, [r3, #0] 80020da: 4977 ldr r1, [pc, #476] @ (80022b8 ) 80020dc: 428b cmp r3, r1 80020de: d008 beq.n 80020f2 80020e0: 683b ldr r3, [r7, #0] 80020e2: 681b ldr r3, [r3, #0] 80020e4: 4975 ldr r1, [pc, #468] @ (80022bc ) 80020e6: 428b cmp r3, r1 80020e8: d101 bne.n 80020ee 80020ea: 4b75 ldr r3, [pc, #468] @ (80022c0 ) 80020ec: e05a b.n 80021a4 80020ee: 2300 movs r3, #0 80020f0: e058 b.n 80021a4 80020f2: 4b74 ldr r3, [pc, #464] @ (80022c4 ) 80020f4: e056 b.n 80021a4 80020f6: 4b74 ldr r3, [pc, #464] @ (80022c8 ) 80020f8: e054 b.n 80021a4 80020fa: 4b6e ldr r3, [pc, #440] @ (80022b4 ) 80020fc: e052 b.n 80021a4 80020fe: 4b6c ldr r3, [pc, #432] @ (80022b0 ) 8002100: e050 b.n 80021a4 8002102: 4b72 ldr r3, [pc, #456] @ (80022cc ) 8002104: e04e b.n 80021a4 8002106: 4b72 ldr r3, [pc, #456] @ (80022d0 ) 8002108: e04c b.n 80021a4 800210a: 4b72 ldr r3, [pc, #456] @ (80022d4 ) 800210c: e04a b.n 80021a4 800210e: 4b72 ldr r3, [pc, #456] @ (80022d8 ) 8002110: e048 b.n 80021a4 8002112: 2301 movs r3, #1 8002114: e046 b.n 80021a4 8002116: 687b ldr r3, [r7, #4] 8002118: 681b ldr r3, [r3, #0] 800211a: 4970 ldr r1, [pc, #448] @ (80022dc ) 800211c: 428b cmp r3, r1 800211e: d140 bne.n 80021a2 8002120: 683b ldr r3, [r7, #0] 8002122: 681b ldr r3, [r3, #0] 8002124: 495c ldr r1, [pc, #368] @ (8002298 ) 8002126: 428b cmp r3, r1 8002128: d039 beq.n 800219e 800212a: 683b ldr r3, [r7, #0] 800212c: 681b ldr r3, [r3, #0] 800212e: 495b ldr r1, [pc, #364] @ (800229c ) 8002130: 428b cmp r3, r1 8002132: d032 beq.n 800219a 8002134: 683b ldr r3, [r7, #0] 8002136: 681b ldr r3, [r3, #0] 8002138: 4959 ldr r1, [pc, #356] @ (80022a0 ) 800213a: 428b cmp r3, r1 800213c: d02b beq.n 8002196 800213e: 683b ldr r3, [r7, #0] 8002140: 681b ldr r3, [r3, #0] 8002142: 4958 ldr r1, [pc, #352] @ (80022a4 ) 8002144: 428b cmp r3, r1 8002146: d024 beq.n 8002192 8002148: 683b ldr r3, [r7, #0] 800214a: 681b ldr r3, [r3, #0] 800214c: 4956 ldr r1, [pc, #344] @ (80022a8 ) 800214e: 428b cmp r3, r1 8002150: d01d beq.n 800218e 8002152: 683b ldr r3, [r7, #0] 8002154: 681b ldr r3, [r3, #0] 8002156: 4955 ldr r1, [pc, #340] @ (80022ac ) 8002158: 428b cmp r3, r1 800215a: d016 beq.n 800218a 800215c: 683b ldr r3, [r7, #0] 800215e: 681b ldr r3, [r3, #0] 8002160: 4953 ldr r1, [pc, #332] @ (80022b0 ) 8002162: 428b cmp r3, r1 8002164: d00f beq.n 8002186 8002166: 683b ldr r3, [r7, #0] 8002168: 681b ldr r3, [r3, #0] 800216a: 4952 ldr r1, [pc, #328] @ (80022b4 ) 800216c: 428b cmp r3, r1 800216e: d008 beq.n 8002182 8002170: 683b ldr r3, [r7, #0] 8002172: 681b ldr r3, [r3, #0] 8002174: 4951 ldr r1, [pc, #324] @ (80022bc ) 8002176: 428b cmp r3, r1 8002178: d101 bne.n 800217e 800217a: 4b51 ldr r3, [pc, #324] @ (80022c0 ) 800217c: e012 b.n 80021a4 800217e: 2300 movs r3, #0 8002180: e010 b.n 80021a4 8002182: 4b51 ldr r3, [pc, #324] @ (80022c8 ) 8002184: e00e b.n 80021a4 8002186: 4b4b ldr r3, [pc, #300] @ (80022b4 ) 8002188: e00c b.n 80021a4 800218a: 4b49 ldr r3, [pc, #292] @ (80022b0 ) 800218c: e00a b.n 80021a4 800218e: 4b4f ldr r3, [pc, #316] @ (80022cc ) 8002190: e008 b.n 80021a4 8002192: 4b4f ldr r3, [pc, #316] @ (80022d0 ) 8002194: e006 b.n 80021a4 8002196: 4b4f ldr r3, [pc, #316] @ (80022d4 ) 8002198: e004 b.n 80021a4 800219a: 4b4f ldr r3, [pc, #316] @ (80022d8 ) 800219c: e002 b.n 80021a4 800219e: 2301 movs r3, #1 80021a0: e000 b.n 80021a4 80021a2: 2300 movs r3, #0 80021a4: 4619 mov r1, r3 80021a6: 4610 mov r0, r2 80021a8: f7ff fafe bl 80017a8 /* If internal channel selected, enable dedicated internal buffers and */ /* paths. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) 80021ac: 683b ldr r3, [r7, #0] 80021ae: 681b ldr r3, [r3, #0] 80021b0: 2b00 cmp r3, #0 80021b2: f280 80fc bge.w 80023ae { /* Configuration of common ADC parameters */ tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 80021b6: 687b ldr r3, [r7, #4] 80021b8: 681b ldr r3, [r3, #0] 80021ba: 4a36 ldr r2, [pc, #216] @ (8002294 ) 80021bc: 4293 cmp r3, r2 80021be: d004 beq.n 80021ca 80021c0: 687b ldr r3, [r7, #4] 80021c2: 681b ldr r3, [r3, #0] 80021c4: 4a45 ldr r2, [pc, #276] @ (80022dc ) 80021c6: 4293 cmp r3, r2 80021c8: d101 bne.n 80021ce 80021ca: 4b45 ldr r3, [pc, #276] @ (80022e0 ) 80021cc: e000 b.n 80021d0 80021ce: 4b45 ldr r3, [pc, #276] @ (80022e4 ) 80021d0: 4618 mov r0, r3 80021d2: f7ff fadb bl 800178c 80021d6: 61f8 str r0, [r7, #28] /* Software is allowed to change common parameters only when all ADCs */ /* of the common group are disabled. */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 80021d8: 687b ldr r3, [r7, #4] 80021da: 681b ldr r3, [r3, #0] 80021dc: 4a2d ldr r2, [pc, #180] @ (8002294 ) 80021de: 4293 cmp r3, r2 80021e0: d004 beq.n 80021ec 80021e2: 687b ldr r3, [r7, #4] 80021e4: 681b ldr r3, [r3, #0] 80021e6: 4a3d ldr r2, [pc, #244] @ (80022dc ) 80021e8: 4293 cmp r3, r2 80021ea: d10e bne.n 800220a 80021ec: 4829 ldr r0, [pc, #164] @ (8002294 ) 80021ee: f7ff fc2b bl 8001a48 80021f2: 4604 mov r4, r0 80021f4: 4839 ldr r0, [pc, #228] @ (80022dc ) 80021f6: f7ff fc27 bl 8001a48 80021fa: 4603 mov r3, r0 80021fc: 4323 orrs r3, r4 80021fe: 2b00 cmp r3, #0 8002200: bf0c ite eq 8002202: 2301 moveq r3, #1 8002204: 2300 movne r3, #0 8002206: b2db uxtb r3, r3 8002208: e008 b.n 800221c 800220a: 4837 ldr r0, [pc, #220] @ (80022e8 ) 800220c: f7ff fc1c bl 8001a48 8002210: 4603 mov r3, r0 8002212: 2b00 cmp r3, #0 8002214: bf0c ite eq 8002216: 2301 moveq r3, #1 8002218: 2300 movne r3, #0 800221a: b2db uxtb r3, r3 800221c: 2b00 cmp r3, #0 800221e: f000 80b3 beq.w 8002388 { /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) 8002222: 683b ldr r3, [r7, #0] 8002224: 681b ldr r3, [r3, #0] 8002226: 4a31 ldr r2, [pc, #196] @ (80022ec ) 8002228: 4293 cmp r3, r2 800222a: d165 bne.n 80022f8 800222c: 69fb ldr r3, [r7, #28] 800222e: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8002232: 2b00 cmp r3, #0 8002234: d160 bne.n 80022f8 { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 8002236: 687b ldr r3, [r7, #4] 8002238: 681b ldr r3, [r3, #0] 800223a: 4a2b ldr r2, [pc, #172] @ (80022e8 ) 800223c: 4293 cmp r3, r2 800223e: f040 80b6 bne.w 80023ae { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); 8002242: 687b ldr r3, [r7, #4] 8002244: 681b ldr r3, [r3, #0] 8002246: 4a13 ldr r2, [pc, #76] @ (8002294 ) 8002248: 4293 cmp r3, r2 800224a: d004 beq.n 8002256 800224c: 687b ldr r3, [r7, #4] 800224e: 681b ldr r3, [r3, #0] 8002250: 4a22 ldr r2, [pc, #136] @ (80022dc ) 8002252: 4293 cmp r3, r2 8002254: d101 bne.n 800225a 8002256: 4a22 ldr r2, [pc, #136] @ (80022e0 ) 8002258: e000 b.n 800225c 800225a: 4a22 ldr r2, [pc, #136] @ (80022e4 ) 800225c: 69fb ldr r3, [r7, #28] 800225e: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 8002262: 4619 mov r1, r3 8002264: 4610 mov r0, r2 8002266: f7ff fa7e bl 8001766 /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 800226a: 4b21 ldr r3, [pc, #132] @ (80022f0 ) 800226c: 681b ldr r3, [r3, #0] 800226e: 099b lsrs r3, r3, #6 8002270: 4a20 ldr r2, [pc, #128] @ (80022f4 ) 8002272: fba2 2303 umull r2, r3, r2, r3 8002276: 099b lsrs r3, r3, #6 8002278: 3301 adds r3, #1 800227a: 005b lsls r3, r3, #1 800227c: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) 800227e: e002 b.n 8002286 { wait_loop_index--; 8002280: 68fb ldr r3, [r7, #12] 8002282: 3b01 subs r3, #1 8002284: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) 8002286: 68fb ldr r3, [r7, #12] 8002288: 2b00 cmp r3, #0 800228a: d1f9 bne.n 8002280 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 800228c: e08f b.n 80023ae 800228e: bf00 nop 8002290: 47ff0000 .word 0x47ff0000 8002294: 40022000 .word 0x40022000 8002298: 04300002 .word 0x04300002 800229c: 08600004 .word 0x08600004 80022a0: 0c900008 .word 0x0c900008 80022a4: 10c00010 .word 0x10c00010 80022a8: 14f00020 .word 0x14f00020 80022ac: 2a000400 .word 0x2a000400 80022b0: 2e300800 .word 0x2e300800 80022b4: 32601000 .word 0x32601000 80022b8: 43210000 .word 0x43210000 80022bc: 4b840000 .word 0x4b840000 80022c0: 4fb80000 .word 0x4fb80000 80022c4: 47520000 .word 0x47520000 80022c8: 36902000 .word 0x36902000 80022cc: 25b00200 .word 0x25b00200 80022d0: 21800100 .word 0x21800100 80022d4: 1d500080 .word 0x1d500080 80022d8: 19200040 .word 0x19200040 80022dc: 40022100 .word 0x40022100 80022e0: 40022300 .word 0x40022300 80022e4: 58026300 .word 0x58026300 80022e8: 58026000 .word 0x58026000 80022ec: cb840000 .word 0xcb840000 80022f0: 24000000 .word 0x24000000 80022f4: 053e2d63 .word 0x053e2d63 } } } else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) 80022f8: 683b ldr r3, [r7, #0] 80022fa: 681b ldr r3, [r3, #0] 80022fc: 4a31 ldr r2, [pc, #196] @ (80023c4 ) 80022fe: 4293 cmp r3, r2 8002300: d11e bne.n 8002340 8002302: 69fb ldr r3, [r7, #28] 8002304: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8002308: 2b00 cmp r3, #0 800230a: d119 bne.n 8002340 { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 800230c: 687b ldr r3, [r7, #4] 800230e: 681b ldr r3, [r3, #0] 8002310: 4a2d ldr r2, [pc, #180] @ (80023c8 ) 8002312: 4293 cmp r3, r2 8002314: d14b bne.n 80023ae { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); 8002316: 687b ldr r3, [r7, #4] 8002318: 681b ldr r3, [r3, #0] 800231a: 4a2c ldr r2, [pc, #176] @ (80023cc ) 800231c: 4293 cmp r3, r2 800231e: d004 beq.n 800232a 8002320: 687b ldr r3, [r7, #4] 8002322: 681b ldr r3, [r3, #0] 8002324: 4a2a ldr r2, [pc, #168] @ (80023d0 ) 8002326: 4293 cmp r3, r2 8002328: d101 bne.n 800232e 800232a: 4a2a ldr r2, [pc, #168] @ (80023d4 ) 800232c: e000 b.n 8002330 800232e: 4a2a ldr r2, [pc, #168] @ (80023d8 ) 8002330: 69fb ldr r3, [r7, #28] 8002332: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8002336: 4619 mov r1, r3 8002338: 4610 mov r0, r2 800233a: f7ff fa14 bl 8001766 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 800233e: e036 b.n 80023ae } } else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) 8002340: 683b ldr r3, [r7, #0] 8002342: 681b ldr r3, [r3, #0] 8002344: 4a25 ldr r2, [pc, #148] @ (80023dc ) 8002346: 4293 cmp r3, r2 8002348: d131 bne.n 80023ae 800234a: 69fb ldr r3, [r7, #28] 800234c: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8002350: 2b00 cmp r3, #0 8002352: d12c bne.n 80023ae { if (ADC_VREFINT_INSTANCE(hadc)) 8002354: 687b ldr r3, [r7, #4] 8002356: 681b ldr r3, [r3, #0] 8002358: 4a1b ldr r2, [pc, #108] @ (80023c8 ) 800235a: 4293 cmp r3, r2 800235c: d127 bne.n 80023ae { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); 800235e: 687b ldr r3, [r7, #4] 8002360: 681b ldr r3, [r3, #0] 8002362: 4a1a ldr r2, [pc, #104] @ (80023cc ) 8002364: 4293 cmp r3, r2 8002366: d004 beq.n 8002372 8002368: 687b ldr r3, [r7, #4] 800236a: 681b ldr r3, [r3, #0] 800236c: 4a18 ldr r2, [pc, #96] @ (80023d0 ) 800236e: 4293 cmp r3, r2 8002370: d101 bne.n 8002376 8002372: 4a18 ldr r2, [pc, #96] @ (80023d4 ) 8002374: e000 b.n 8002378 8002376: 4a18 ldr r2, [pc, #96] @ (80023d8 ) 8002378: 69fb ldr r3, [r7, #28] 800237a: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 800237e: 4619 mov r1, r3 8002380: 4610 mov r0, r2 8002382: f7ff f9f0 bl 8001766 8002386: e012 b.n 80023ae /* enabled and other ADC of the common group are enabled, internal */ /* measurement paths cannot be enabled. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8002388: 687b ldr r3, [r7, #4] 800238a: 6d5b ldr r3, [r3, #84] @ 0x54 800238c: f043 0220 orr.w r2, r3, #32 8002390: 687b ldr r3, [r7, #4] 8002392: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8002394: 2301 movs r3, #1 8002396: f887 302f strb.w r3, [r7, #47] @ 0x2f 800239a: e008 b.n 80023ae /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800239c: 687b ldr r3, [r7, #4] 800239e: 6d5b ldr r3, [r3, #84] @ 0x54 80023a0: f043 0220 orr.w r2, r3, #32 80023a4: 687b ldr r3, [r7, #4] 80023a6: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 80023a8: 2301 movs r3, #1 80023aa: f887 302f strb.w r3, [r7, #47] @ 0x2f } /* Process unlocked */ __HAL_UNLOCK(hadc); 80023ae: 687b ldr r3, [r7, #4] 80023b0: 2200 movs r2, #0 80023b2: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 80023b6: f897 302f ldrb.w r3, [r7, #47] @ 0x2f } 80023ba: 4618 mov r0, r3 80023bc: 3734 adds r7, #52 @ 0x34 80023be: 46bd mov sp, r7 80023c0: bd90 pop {r4, r7, pc} 80023c2: bf00 nop 80023c4: c7520000 .word 0xc7520000 80023c8: 58026000 .word 0x58026000 80023cc: 40022000 .word 0x40022000 80023d0: 40022100 .word 0x40022100 80023d4: 40022300 .word 0x40022300 80023d8: 58026300 .word 0x58026300 80023dc: cfb80000 .word 0xcfb80000 080023e0 : * stopped. * @param hadc ADC handle * @retval None. */ void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc) { 80023e0: b580 push {r7, lr} 80023e2: b084 sub sp, #16 80023e4: af00 add r7, sp, #0 80023e6: 6078 str r0, [r7, #4] uint32_t freq; if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc)) 80023e8: 687b ldr r3, [r7, #4] 80023ea: 681b ldr r3, [r3, #0] 80023ec: 4a7a ldr r2, [pc, #488] @ (80025d8 ) 80023ee: 4293 cmp r3, r2 80023f0: d004 beq.n 80023fc 80023f2: 687b ldr r3, [r7, #4] 80023f4: 681b ldr r3, [r3, #0] 80023f6: 4a79 ldr r2, [pc, #484] @ (80025dc ) 80023f8: 4293 cmp r3, r2 80023fa: d109 bne.n 8002410 80023fc: 4b78 ldr r3, [pc, #480] @ (80025e0 ) 80023fe: 689b ldr r3, [r3, #8] 8002400: f403 3340 and.w r3, r3, #196608 @ 0x30000 8002404: 2b00 cmp r3, #0 8002406: bf14 ite ne 8002408: 2301 movne r3, #1 800240a: 2300 moveq r3, #0 800240c: b2db uxtb r3, r3 800240e: e008 b.n 8002422 8002410: 4b74 ldr r3, [pc, #464] @ (80025e4 ) 8002412: 689b ldr r3, [r3, #8] 8002414: f403 3340 and.w r3, r3, #196608 @ 0x30000 8002418: 2b00 cmp r3, #0 800241a: bf14 ite ne 800241c: 2301 movne r3, #1 800241e: 2300 moveq r3, #0 8002420: b2db uxtb r3, r3 8002422: 2b00 cmp r3, #0 8002424: d01c beq.n 8002460 { freq = HAL_RCC_GetHCLKFreq(); 8002426: f003 fdab bl 8005f80 800242a: 60f8 str r0, [r7, #12] switch (hadc->Init.ClockPrescaler) 800242c: 687b ldr r3, [r7, #4] 800242e: 685b ldr r3, [r3, #4] 8002430: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8002434: d010 beq.n 8002458 8002436: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800243a: d873 bhi.n 8002524 800243c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8002440: d002 beq.n 8002448 8002442: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8002446: d16d bne.n 8002524 { case ADC_CLOCK_SYNC_PCLK_DIV1: case ADC_CLOCK_SYNC_PCLK_DIV2: freq /= (hadc->Init.ClockPrescaler >> ADC_CCR_CKMODE_Pos); 8002448: 687b ldr r3, [r7, #4] 800244a: 685b ldr r3, [r3, #4] 800244c: 0c1b lsrs r3, r3, #16 800244e: 68fa ldr r2, [r7, #12] 8002450: fbb2 f3f3 udiv r3, r2, r3 8002454: 60fb str r3, [r7, #12] break; 8002456: e068 b.n 800252a case ADC_CLOCK_SYNC_PCLK_DIV4: freq /= 4UL; 8002458: 68fb ldr r3, [r7, #12] 800245a: 089b lsrs r3, r3, #2 800245c: 60fb str r3, [r7, #12] break; 800245e: e064 b.n 800252a break; } } else { freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC); 8002460: f44f 2000 mov.w r0, #524288 @ 0x80000 8002464: f04f 0100 mov.w r1, #0 8002468: f004 fff0 bl 800744c 800246c: 60f8 str r0, [r7, #12] switch (hadc->Init.ClockPrescaler) 800246e: 687b ldr r3, [r7, #4] 8002470: 685b ldr r3, [r3, #4] 8002472: f5b3 1f30 cmp.w r3, #2883584 @ 0x2c0000 8002476: d051 beq.n 800251c 8002478: f5b3 1f30 cmp.w r3, #2883584 @ 0x2c0000 800247c: d854 bhi.n 8002528 800247e: f5b3 1f20 cmp.w r3, #2621440 @ 0x280000 8002482: d047 beq.n 8002514 8002484: f5b3 1f20 cmp.w r3, #2621440 @ 0x280000 8002488: d84e bhi.n 8002528 800248a: f5b3 1f10 cmp.w r3, #2359296 @ 0x240000 800248e: d03d beq.n 800250c 8002490: f5b3 1f10 cmp.w r3, #2359296 @ 0x240000 8002494: d848 bhi.n 8002528 8002496: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800249a: d033 beq.n 8002504 800249c: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 80024a0: d842 bhi.n 8002528 80024a2: f5b3 1fe0 cmp.w r3, #1835008 @ 0x1c0000 80024a6: d029 beq.n 80024fc 80024a8: f5b3 1fe0 cmp.w r3, #1835008 @ 0x1c0000 80024ac: d83c bhi.n 8002528 80024ae: f5b3 1fc0 cmp.w r3, #1572864 @ 0x180000 80024b2: d01a beq.n 80024ea 80024b4: f5b3 1fc0 cmp.w r3, #1572864 @ 0x180000 80024b8: d836 bhi.n 8002528 80024ba: f5b3 1fa0 cmp.w r3, #1310720 @ 0x140000 80024be: d014 beq.n 80024ea 80024c0: f5b3 1fa0 cmp.w r3, #1310720 @ 0x140000 80024c4: d830 bhi.n 8002528 80024c6: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80024ca: d00e beq.n 80024ea 80024cc: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80024d0: d82a bhi.n 8002528 80024d2: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 80024d6: d008 beq.n 80024ea 80024d8: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 80024dc: d824 bhi.n 8002528 80024de: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 80024e2: d002 beq.n 80024ea 80024e4: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 80024e8: d11e bne.n 8002528 case ADC_CLOCK_ASYNC_DIV4: case ADC_CLOCK_ASYNC_DIV6: case ADC_CLOCK_ASYNC_DIV8: case ADC_CLOCK_ASYNC_DIV10: case ADC_CLOCK_ASYNC_DIV12: freq /= ((hadc->Init.ClockPrescaler >> ADC_CCR_PRESC_Pos) << 1UL); 80024ea: 687b ldr r3, [r7, #4] 80024ec: 685b ldr r3, [r3, #4] 80024ee: 0c9b lsrs r3, r3, #18 80024f0: 005b lsls r3, r3, #1 80024f2: 68fa ldr r2, [r7, #12] 80024f4: fbb2 f3f3 udiv r3, r2, r3 80024f8: 60fb str r3, [r7, #12] break; 80024fa: e016 b.n 800252a case ADC_CLOCK_ASYNC_DIV16: freq /= 16UL; 80024fc: 68fb ldr r3, [r7, #12] 80024fe: 091b lsrs r3, r3, #4 8002500: 60fb str r3, [r7, #12] break; 8002502: e012 b.n 800252a case ADC_CLOCK_ASYNC_DIV32: freq /= 32UL; 8002504: 68fb ldr r3, [r7, #12] 8002506: 095b lsrs r3, r3, #5 8002508: 60fb str r3, [r7, #12] break; 800250a: e00e b.n 800252a case ADC_CLOCK_ASYNC_DIV64: freq /= 64UL; 800250c: 68fb ldr r3, [r7, #12] 800250e: 099b lsrs r3, r3, #6 8002510: 60fb str r3, [r7, #12] break; 8002512: e00a b.n 800252a case ADC_CLOCK_ASYNC_DIV128: freq /= 128UL; 8002514: 68fb ldr r3, [r7, #12] 8002516: 09db lsrs r3, r3, #7 8002518: 60fb str r3, [r7, #12] break; 800251a: e006 b.n 800252a case ADC_CLOCK_ASYNC_DIV256: freq /= 256UL; 800251c: 68fb ldr r3, [r7, #12] 800251e: 0a1b lsrs r3, r3, #8 8002520: 60fb str r3, [r7, #12] break; 8002522: e002 b.n 800252a break; 8002524: bf00 nop 8002526: e000 b.n 800252a default: break; 8002528: bf00 nop else /* if(freq > 25000000UL) */ { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); } #else if (HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */ 800252a: f7ff f8e7 bl 80016fc 800252e: 4603 mov r3, r0 8002530: f241 0203 movw r2, #4099 @ 0x1003 8002534: 4293 cmp r3, r2 8002536: d815 bhi.n 8002564 { if (freq > 20000000UL) 8002538: 68fb ldr r3, [r7, #12] 800253a: 4a2b ldr r2, [pc, #172] @ (80025e8 ) 800253c: 4293 cmp r3, r2 800253e: d908 bls.n 8002552 { SET_BIT(hadc->Instance->CR, ADC_CR_BOOST_0); 8002540: 687b ldr r3, [r7, #4] 8002542: 681b ldr r3, [r3, #0] 8002544: 689a ldr r2, [r3, #8] 8002546: 687b ldr r3, [r7, #4] 8002548: 681b ldr r3, [r3, #0] 800254a: f442 7280 orr.w r2, r2, #256 @ 0x100 800254e: 609a str r2, [r3, #8] { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); } } #endif /* ADC_VER_V5_3 */ } 8002550: e03e b.n 80025d0 CLEAR_BIT(hadc->Instance->CR, ADC_CR_BOOST_0); 8002552: 687b ldr r3, [r7, #4] 8002554: 681b ldr r3, [r3, #0] 8002556: 689a ldr r2, [r3, #8] 8002558: 687b ldr r3, [r7, #4] 800255a: 681b ldr r3, [r3, #0] 800255c: f422 7280 bic.w r2, r2, #256 @ 0x100 8002560: 609a str r2, [r3, #8] } 8002562: e035 b.n 80025d0 freq /= 2U; /* divider by 2 for Rev.V */ 8002564: 68fb ldr r3, [r7, #12] 8002566: 085b lsrs r3, r3, #1 8002568: 60fb str r3, [r7, #12] if (freq <= 6250000UL) 800256a: 68fb ldr r3, [r7, #12] 800256c: 4a1f ldr r2, [pc, #124] @ (80025ec ) 800256e: 4293 cmp r3, r2 8002570: d808 bhi.n 8002584 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL); 8002572: 687b ldr r3, [r7, #4] 8002574: 681b ldr r3, [r3, #0] 8002576: 689a ldr r2, [r3, #8] 8002578: 687b ldr r3, [r7, #4] 800257a: 681b ldr r3, [r3, #0] 800257c: f422 7240 bic.w r2, r2, #768 @ 0x300 8002580: 609a str r2, [r3, #8] } 8002582: e025 b.n 80025d0 else if (freq <= 12500000UL) 8002584: 68fb ldr r3, [r7, #12] 8002586: 4a1a ldr r2, [pc, #104] @ (80025f0 ) 8002588: 4293 cmp r3, r2 800258a: d80a bhi.n 80025a2 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0); 800258c: 687b ldr r3, [r7, #4] 800258e: 681b ldr r3, [r3, #0] 8002590: 689b ldr r3, [r3, #8] 8002592: f423 7240 bic.w r2, r3, #768 @ 0x300 8002596: 687b ldr r3, [r7, #4] 8002598: 681b ldr r3, [r3, #0] 800259a: f442 7280 orr.w r2, r2, #256 @ 0x100 800259e: 609a str r2, [r3, #8] } 80025a0: e016 b.n 80025d0 else if (freq <= 25000000UL) 80025a2: 68fb ldr r3, [r7, #12] 80025a4: 4a13 ldr r2, [pc, #76] @ (80025f4 ) 80025a6: 4293 cmp r3, r2 80025a8: d80a bhi.n 80025c0 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1); 80025aa: 687b ldr r3, [r7, #4] 80025ac: 681b ldr r3, [r3, #0] 80025ae: 689b ldr r3, [r3, #8] 80025b0: f423 7240 bic.w r2, r3, #768 @ 0x300 80025b4: 687b ldr r3, [r7, #4] 80025b6: 681b ldr r3, [r3, #0] 80025b8: f442 7200 orr.w r2, r2, #512 @ 0x200 80025bc: 609a str r2, [r3, #8] } 80025be: e007 b.n 80025d0 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); 80025c0: 687b ldr r3, [r7, #4] 80025c2: 681b ldr r3, [r3, #0] 80025c4: 689a ldr r2, [r3, #8] 80025c6: 687b ldr r3, [r7, #4] 80025c8: 681b ldr r3, [r3, #0] 80025ca: f442 7240 orr.w r2, r2, #768 @ 0x300 80025ce: 609a str r2, [r3, #8] } 80025d0: bf00 nop 80025d2: 3710 adds r7, #16 80025d4: 46bd mov sp, r7 80025d6: bd80 pop {r7, pc} 80025d8: 40022000 .word 0x40022000 80025dc: 40022100 .word 0x40022100 80025e0: 40022300 .word 0x40022300 80025e4: 58026300 .word 0x58026300 80025e8: 01312d00 .word 0x01312d00 80025ec: 005f5e10 .word 0x005f5e10 80025f0: 00bebc20 .word 0x00bebc20 80025f4: 017d7840 .word 0x017d7840 080025f8 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80025f8: b480 push {r7} 80025fa: b085 sub sp, #20 80025fc: af00 add r7, sp, #0 80025fe: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8002600: 687b ldr r3, [r7, #4] 8002602: f003 0307 and.w r3, r3, #7 8002606: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8002608: 4b0b ldr r3, [pc, #44] @ (8002638 <__NVIC_SetPriorityGrouping+0x40>) 800260a: 68db ldr r3, [r3, #12] 800260c: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 800260e: 68ba ldr r2, [r7, #8] 8002610: f64f 03ff movw r3, #63743 @ 0xf8ff 8002614: 4013 ands r3, r2 8002616: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8002618: 68fb ldr r3, [r7, #12] 800261a: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800261c: 68bb ldr r3, [r7, #8] 800261e: 431a orrs r2, r3 reg_value = (reg_value | 8002620: 4b06 ldr r3, [pc, #24] @ (800263c <__NVIC_SetPriorityGrouping+0x44>) 8002622: 4313 orrs r3, r2 8002624: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8002626: 4a04 ldr r2, [pc, #16] @ (8002638 <__NVIC_SetPriorityGrouping+0x40>) 8002628: 68bb ldr r3, [r7, #8] 800262a: 60d3 str r3, [r2, #12] } 800262c: bf00 nop 800262e: 3714 adds r7, #20 8002630: 46bd mov sp, r7 8002632: f85d 7b04 ldr.w r7, [sp], #4 8002636: 4770 bx lr 8002638: e000ed00 .word 0xe000ed00 800263c: 05fa0000 .word 0x05fa0000 08002640 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8002640: b480 push {r7} 8002642: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8002644: 4b04 ldr r3, [pc, #16] @ (8002658 <__NVIC_GetPriorityGrouping+0x18>) 8002646: 68db ldr r3, [r3, #12] 8002648: 0a1b lsrs r3, r3, #8 800264a: f003 0307 and.w r3, r3, #7 } 800264e: 4618 mov r0, r3 8002650: 46bd mov sp, r7 8002652: f85d 7b04 ldr.w r7, [sp], #4 8002656: 4770 bx lr 8002658: e000ed00 .word 0xe000ed00 0800265c <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 800265c: b480 push {r7} 800265e: b083 sub sp, #12 8002660: af00 add r7, sp, #0 8002662: 4603 mov r3, r0 8002664: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8002666: f9b7 3006 ldrsh.w r3, [r7, #6] 800266a: 2b00 cmp r3, #0 800266c: db0b blt.n 8002686 <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800266e: 88fb ldrh r3, [r7, #6] 8002670: f003 021f and.w r2, r3, #31 8002674: 4907 ldr r1, [pc, #28] @ (8002694 <__NVIC_EnableIRQ+0x38>) 8002676: f9b7 3006 ldrsh.w r3, [r7, #6] 800267a: 095b lsrs r3, r3, #5 800267c: 2001 movs r0, #1 800267e: fa00 f202 lsl.w r2, r0, r2 8002682: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } 8002686: bf00 nop 8002688: 370c adds r7, #12 800268a: 46bd mov sp, r7 800268c: f85d 7b04 ldr.w r7, [sp], #4 8002690: 4770 bx lr 8002692: bf00 nop 8002694: e000e100 .word 0xe000e100 08002698 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8002698: b480 push {r7} 800269a: b083 sub sp, #12 800269c: af00 add r7, sp, #0 800269e: 4603 mov r3, r0 80026a0: 6039 str r1, [r7, #0] 80026a2: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 80026a4: f9b7 3006 ldrsh.w r3, [r7, #6] 80026a8: 2b00 cmp r3, #0 80026aa: db0a blt.n 80026c2 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80026ac: 683b ldr r3, [r7, #0] 80026ae: b2da uxtb r2, r3 80026b0: 490c ldr r1, [pc, #48] @ (80026e4 <__NVIC_SetPriority+0x4c>) 80026b2: f9b7 3006 ldrsh.w r3, [r7, #6] 80026b6: 0112 lsls r2, r2, #4 80026b8: b2d2 uxtb r2, r2 80026ba: 440b add r3, r1 80026bc: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 80026c0: e00a b.n 80026d8 <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80026c2: 683b ldr r3, [r7, #0] 80026c4: b2da uxtb r2, r3 80026c6: 4908 ldr r1, [pc, #32] @ (80026e8 <__NVIC_SetPriority+0x50>) 80026c8: 88fb ldrh r3, [r7, #6] 80026ca: f003 030f and.w r3, r3, #15 80026ce: 3b04 subs r3, #4 80026d0: 0112 lsls r2, r2, #4 80026d2: b2d2 uxtb r2, r2 80026d4: 440b add r3, r1 80026d6: 761a strb r2, [r3, #24] } 80026d8: bf00 nop 80026da: 370c adds r7, #12 80026dc: 46bd mov sp, r7 80026de: f85d 7b04 ldr.w r7, [sp], #4 80026e2: 4770 bx lr 80026e4: e000e100 .word 0xe000e100 80026e8: e000ed00 .word 0xe000ed00 080026ec : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 80026ec: b480 push {r7} 80026ee: b089 sub sp, #36 @ 0x24 80026f0: af00 add r7, sp, #0 80026f2: 60f8 str r0, [r7, #12] 80026f4: 60b9 str r1, [r7, #8] 80026f6: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80026f8: 68fb ldr r3, [r7, #12] 80026fa: f003 0307 and.w r3, r3, #7 80026fe: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8002700: 69fb ldr r3, [r7, #28] 8002702: f1c3 0307 rsb r3, r3, #7 8002706: 2b04 cmp r3, #4 8002708: bf28 it cs 800270a: 2304 movcs r3, #4 800270c: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 800270e: 69fb ldr r3, [r7, #28] 8002710: 3304 adds r3, #4 8002712: 2b06 cmp r3, #6 8002714: d902 bls.n 800271c 8002716: 69fb ldr r3, [r7, #28] 8002718: 3b03 subs r3, #3 800271a: e000 b.n 800271e 800271c: 2300 movs r3, #0 800271e: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8002720: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8002724: 69bb ldr r3, [r7, #24] 8002726: fa02 f303 lsl.w r3, r2, r3 800272a: 43da mvns r2, r3 800272c: 68bb ldr r3, [r7, #8] 800272e: 401a ands r2, r3 8002730: 697b ldr r3, [r7, #20] 8002732: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8002734: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002738: 697b ldr r3, [r7, #20] 800273a: fa01 f303 lsl.w r3, r1, r3 800273e: 43d9 mvns r1, r3 8002740: 687b ldr r3, [r7, #4] 8002742: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8002744: 4313 orrs r3, r2 ); } 8002746: 4618 mov r0, r3 8002748: 3724 adds r7, #36 @ 0x24 800274a: 46bd mov sp, r7 800274c: f85d 7b04 ldr.w r7, [sp], #4 8002750: 4770 bx lr ... 08002754 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8002754: b580 push {r7, lr} 8002756: b082 sub sp, #8 8002758: af00 add r7, sp, #0 800275a: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 800275c: 687b ldr r3, [r7, #4] 800275e: 3b01 subs r3, #1 8002760: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8002764: d301 bcc.n 800276a { return (1UL); /* Reload value impossible */ 8002766: 2301 movs r3, #1 8002768: e00f b.n 800278a } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 800276a: 4a0a ldr r2, [pc, #40] @ (8002794 ) 800276c: 687b ldr r3, [r7, #4] 800276e: 3b01 subs r3, #1 8002770: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8002772: 210f movs r1, #15 8002774: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8002778: f7ff ff8e bl 8002698 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 800277c: 4b05 ldr r3, [pc, #20] @ (8002794 ) 800277e: 2200 movs r2, #0 8002780: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8002782: 4b04 ldr r3, [pc, #16] @ (8002794 ) 8002784: 2207 movs r2, #7 8002786: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8002788: 2300 movs r3, #0 } 800278a: 4618 mov r0, r3 800278c: 3708 adds r7, #8 800278e: 46bd mov sp, r7 8002790: bd80 pop {r7, pc} 8002792: bf00 nop 8002794: e000e010 .word 0xe000e010 08002798 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8002798: b580 push {r7, lr} 800279a: b082 sub sp, #8 800279c: af00 add r7, sp, #0 800279e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 80027a0: 6878 ldr r0, [r7, #4] 80027a2: f7ff ff29 bl 80025f8 <__NVIC_SetPriorityGrouping> } 80027a6: bf00 nop 80027a8: 3708 adds r7, #8 80027aa: 46bd mov sp, r7 80027ac: bd80 pop {r7, pc} 080027ae : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 80027ae: b580 push {r7, lr} 80027b0: b086 sub sp, #24 80027b2: af00 add r7, sp, #0 80027b4: 4603 mov r3, r0 80027b6: 60b9 str r1, [r7, #8] 80027b8: 607a str r2, [r7, #4] 80027ba: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 80027bc: f7ff ff40 bl 8002640 <__NVIC_GetPriorityGrouping> 80027c0: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 80027c2: 687a ldr r2, [r7, #4] 80027c4: 68b9 ldr r1, [r7, #8] 80027c6: 6978 ldr r0, [r7, #20] 80027c8: f7ff ff90 bl 80026ec 80027cc: 4602 mov r2, r0 80027ce: f9b7 300e ldrsh.w r3, [r7, #14] 80027d2: 4611 mov r1, r2 80027d4: 4618 mov r0, r3 80027d6: f7ff ff5f bl 8002698 <__NVIC_SetPriority> } 80027da: bf00 nop 80027dc: 3718 adds r7, #24 80027de: 46bd mov sp, r7 80027e0: bd80 pop {r7, pc} 080027e2 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 80027e2: b580 push {r7, lr} 80027e4: b082 sub sp, #8 80027e6: af00 add r7, sp, #0 80027e8: 4603 mov r3, r0 80027ea: 80fb strh r3, [r7, #6] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 80027ec: f9b7 3006 ldrsh.w r3, [r7, #6] 80027f0: 4618 mov r0, r3 80027f2: f7ff ff33 bl 800265c <__NVIC_EnableIRQ> } 80027f6: bf00 nop 80027f8: 3708 adds r7, #8 80027fa: 46bd mov sp, r7 80027fc: bd80 pop {r7, pc} 080027fe : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 80027fe: b580 push {r7, lr} 8002800: b082 sub sp, #8 8002802: af00 add r7, sp, #0 8002804: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8002806: 6878 ldr r0, [r7, #4] 8002808: f7ff ffa4 bl 8002754 800280c: 4603 mov r3, r0 } 800280e: 4618 mov r0, r3 8002810: 3708 adds r7, #8 8002812: 46bd mov sp, r7 8002814: bd80 pop {r7, pc} ... 08002818 : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8002818: b580 push {r7, lr} 800281a: b086 sub sp, #24 800281c: af00 add r7, sp, #0 800281e: 6078 str r0, [r7, #4] uint32_t registerValue; uint32_t tickstart = HAL_GetTick(); 8002820: f7fe ff60 bl 80016e4 8002824: 6138 str r0, [r7, #16] DMA_Base_Registers *regs_dma; BDMA_Base_Registers *regs_bdma; /* Check the DMA peripheral handle */ if(hdma == NULL) 8002826: 687b ldr r3, [r7, #4] 8002828: 2b00 cmp r3, #0 800282a: d101 bne.n 8002830 { return HAL_ERROR; 800282c: 2301 movs r3, #1 800282e: e316 b.n 8002e5e assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8002830: 687b ldr r3, [r7, #4] 8002832: 681b ldr r3, [r3, #0] 8002834: 4a66 ldr r2, [pc, #408] @ (80029d0 ) 8002836: 4293 cmp r3, r2 8002838: d04a beq.n 80028d0 800283a: 687b ldr r3, [r7, #4] 800283c: 681b ldr r3, [r3, #0] 800283e: 4a65 ldr r2, [pc, #404] @ (80029d4 ) 8002840: 4293 cmp r3, r2 8002842: d045 beq.n 80028d0 8002844: 687b ldr r3, [r7, #4] 8002846: 681b ldr r3, [r3, #0] 8002848: 4a63 ldr r2, [pc, #396] @ (80029d8 ) 800284a: 4293 cmp r3, r2 800284c: d040 beq.n 80028d0 800284e: 687b ldr r3, [r7, #4] 8002850: 681b ldr r3, [r3, #0] 8002852: 4a62 ldr r2, [pc, #392] @ (80029dc ) 8002854: 4293 cmp r3, r2 8002856: d03b beq.n 80028d0 8002858: 687b ldr r3, [r7, #4] 800285a: 681b ldr r3, [r3, #0] 800285c: 4a60 ldr r2, [pc, #384] @ (80029e0 ) 800285e: 4293 cmp r3, r2 8002860: d036 beq.n 80028d0 8002862: 687b ldr r3, [r7, #4] 8002864: 681b ldr r3, [r3, #0] 8002866: 4a5f ldr r2, [pc, #380] @ (80029e4 ) 8002868: 4293 cmp r3, r2 800286a: d031 beq.n 80028d0 800286c: 687b ldr r3, [r7, #4] 800286e: 681b ldr r3, [r3, #0] 8002870: 4a5d ldr r2, [pc, #372] @ (80029e8 ) 8002872: 4293 cmp r3, r2 8002874: d02c beq.n 80028d0 8002876: 687b ldr r3, [r7, #4] 8002878: 681b ldr r3, [r3, #0] 800287a: 4a5c ldr r2, [pc, #368] @ (80029ec ) 800287c: 4293 cmp r3, r2 800287e: d027 beq.n 80028d0 8002880: 687b ldr r3, [r7, #4] 8002882: 681b ldr r3, [r3, #0] 8002884: 4a5a ldr r2, [pc, #360] @ (80029f0 ) 8002886: 4293 cmp r3, r2 8002888: d022 beq.n 80028d0 800288a: 687b ldr r3, [r7, #4] 800288c: 681b ldr r3, [r3, #0] 800288e: 4a59 ldr r2, [pc, #356] @ (80029f4 ) 8002890: 4293 cmp r3, r2 8002892: d01d beq.n 80028d0 8002894: 687b ldr r3, [r7, #4] 8002896: 681b ldr r3, [r3, #0] 8002898: 4a57 ldr r2, [pc, #348] @ (80029f8 ) 800289a: 4293 cmp r3, r2 800289c: d018 beq.n 80028d0 800289e: 687b ldr r3, [r7, #4] 80028a0: 681b ldr r3, [r3, #0] 80028a2: 4a56 ldr r2, [pc, #344] @ (80029fc ) 80028a4: 4293 cmp r3, r2 80028a6: d013 beq.n 80028d0 80028a8: 687b ldr r3, [r7, #4] 80028aa: 681b ldr r3, [r3, #0] 80028ac: 4a54 ldr r2, [pc, #336] @ (8002a00 ) 80028ae: 4293 cmp r3, r2 80028b0: d00e beq.n 80028d0 80028b2: 687b ldr r3, [r7, #4] 80028b4: 681b ldr r3, [r3, #0] 80028b6: 4a53 ldr r2, [pc, #332] @ (8002a04 ) 80028b8: 4293 cmp r3, r2 80028ba: d009 beq.n 80028d0 80028bc: 687b ldr r3, [r7, #4] 80028be: 681b ldr r3, [r3, #0] 80028c0: 4a51 ldr r2, [pc, #324] @ (8002a08 ) 80028c2: 4293 cmp r3, r2 80028c4: d004 beq.n 80028d0 80028c6: 687b ldr r3, [r7, #4] 80028c8: 681b ldr r3, [r3, #0] 80028ca: 4a50 ldr r2, [pc, #320] @ (8002a0c ) 80028cc: 4293 cmp r3, r2 80028ce: d101 bne.n 80028d4 80028d0: 2301 movs r3, #1 80028d2: e000 b.n 80028d6 80028d4: 2300 movs r3, #0 80028d6: 2b00 cmp r3, #0 80028d8: f000 813b beq.w 8002b52 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 80028dc: 687b ldr r3, [r7, #4] 80028de: 2202 movs r2, #2 80028e0: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 80028e4: 687b ldr r3, [r7, #4] 80028e6: 2200 movs r2, #0 80028e8: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 80028ec: 687b ldr r3, [r7, #4] 80028ee: 681b ldr r3, [r3, #0] 80028f0: 4a37 ldr r2, [pc, #220] @ (80029d0 ) 80028f2: 4293 cmp r3, r2 80028f4: d04a beq.n 800298c 80028f6: 687b ldr r3, [r7, #4] 80028f8: 681b ldr r3, [r3, #0] 80028fa: 4a36 ldr r2, [pc, #216] @ (80029d4 ) 80028fc: 4293 cmp r3, r2 80028fe: d045 beq.n 800298c 8002900: 687b ldr r3, [r7, #4] 8002902: 681b ldr r3, [r3, #0] 8002904: 4a34 ldr r2, [pc, #208] @ (80029d8 ) 8002906: 4293 cmp r3, r2 8002908: d040 beq.n 800298c 800290a: 687b ldr r3, [r7, #4] 800290c: 681b ldr r3, [r3, #0] 800290e: 4a33 ldr r2, [pc, #204] @ (80029dc ) 8002910: 4293 cmp r3, r2 8002912: d03b beq.n 800298c 8002914: 687b ldr r3, [r7, #4] 8002916: 681b ldr r3, [r3, #0] 8002918: 4a31 ldr r2, [pc, #196] @ (80029e0 ) 800291a: 4293 cmp r3, r2 800291c: d036 beq.n 800298c 800291e: 687b ldr r3, [r7, #4] 8002920: 681b ldr r3, [r3, #0] 8002922: 4a30 ldr r2, [pc, #192] @ (80029e4 ) 8002924: 4293 cmp r3, r2 8002926: d031 beq.n 800298c 8002928: 687b ldr r3, [r7, #4] 800292a: 681b ldr r3, [r3, #0] 800292c: 4a2e ldr r2, [pc, #184] @ (80029e8 ) 800292e: 4293 cmp r3, r2 8002930: d02c beq.n 800298c 8002932: 687b ldr r3, [r7, #4] 8002934: 681b ldr r3, [r3, #0] 8002936: 4a2d ldr r2, [pc, #180] @ (80029ec ) 8002938: 4293 cmp r3, r2 800293a: d027 beq.n 800298c 800293c: 687b ldr r3, [r7, #4] 800293e: 681b ldr r3, [r3, #0] 8002940: 4a2b ldr r2, [pc, #172] @ (80029f0 ) 8002942: 4293 cmp r3, r2 8002944: d022 beq.n 800298c 8002946: 687b ldr r3, [r7, #4] 8002948: 681b ldr r3, [r3, #0] 800294a: 4a2a ldr r2, [pc, #168] @ (80029f4 ) 800294c: 4293 cmp r3, r2 800294e: d01d beq.n 800298c 8002950: 687b ldr r3, [r7, #4] 8002952: 681b ldr r3, [r3, #0] 8002954: 4a28 ldr r2, [pc, #160] @ (80029f8 ) 8002956: 4293 cmp r3, r2 8002958: d018 beq.n 800298c 800295a: 687b ldr r3, [r7, #4] 800295c: 681b ldr r3, [r3, #0] 800295e: 4a27 ldr r2, [pc, #156] @ (80029fc ) 8002960: 4293 cmp r3, r2 8002962: d013 beq.n 800298c 8002964: 687b ldr r3, [r7, #4] 8002966: 681b ldr r3, [r3, #0] 8002968: 4a25 ldr r2, [pc, #148] @ (8002a00 ) 800296a: 4293 cmp r3, r2 800296c: d00e beq.n 800298c 800296e: 687b ldr r3, [r7, #4] 8002970: 681b ldr r3, [r3, #0] 8002972: 4a24 ldr r2, [pc, #144] @ (8002a04 ) 8002974: 4293 cmp r3, r2 8002976: d009 beq.n 800298c 8002978: 687b ldr r3, [r7, #4] 800297a: 681b ldr r3, [r3, #0] 800297c: 4a22 ldr r2, [pc, #136] @ (8002a08 ) 800297e: 4293 cmp r3, r2 8002980: d004 beq.n 800298c 8002982: 687b ldr r3, [r7, #4] 8002984: 681b ldr r3, [r3, #0] 8002986: 4a21 ldr r2, [pc, #132] @ (8002a0c ) 8002988: 4293 cmp r3, r2 800298a: d108 bne.n 800299e 800298c: 687b ldr r3, [r7, #4] 800298e: 681b ldr r3, [r3, #0] 8002990: 681a ldr r2, [r3, #0] 8002992: 687b ldr r3, [r7, #4] 8002994: 681b ldr r3, [r3, #0] 8002996: f022 0201 bic.w r2, r2, #1 800299a: 601a str r2, [r3, #0] 800299c: e007 b.n 80029ae 800299e: 687b ldr r3, [r7, #4] 80029a0: 681b ldr r3, [r3, #0] 80029a2: 681a ldr r2, [r3, #0] 80029a4: 687b ldr r3, [r7, #4] 80029a6: 681b ldr r3, [r3, #0] 80029a8: f022 0201 bic.w r2, r2, #1 80029ac: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 80029ae: e02f b.n 8002a10 { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 80029b0: f7fe fe98 bl 80016e4 80029b4: 4602 mov r2, r0 80029b6: 693b ldr r3, [r7, #16] 80029b8: 1ad3 subs r3, r2, r3 80029ba: 2b05 cmp r3, #5 80029bc: d928 bls.n 8002a10 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 80029be: 687b ldr r3, [r7, #4] 80029c0: 2220 movs r2, #32 80029c2: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; 80029c4: 687b ldr r3, [r7, #4] 80029c6: 2203 movs r2, #3 80029c8: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 80029cc: 2301 movs r3, #1 80029ce: e246 b.n 8002e5e 80029d0: 40020010 .word 0x40020010 80029d4: 40020028 .word 0x40020028 80029d8: 40020040 .word 0x40020040 80029dc: 40020058 .word 0x40020058 80029e0: 40020070 .word 0x40020070 80029e4: 40020088 .word 0x40020088 80029e8: 400200a0 .word 0x400200a0 80029ec: 400200b8 .word 0x400200b8 80029f0: 40020410 .word 0x40020410 80029f4: 40020428 .word 0x40020428 80029f8: 40020440 .word 0x40020440 80029fc: 40020458 .word 0x40020458 8002a00: 40020470 .word 0x40020470 8002a04: 40020488 .word 0x40020488 8002a08: 400204a0 .word 0x400204a0 8002a0c: 400204b8 .word 0x400204b8 while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 8002a10: 687b ldr r3, [r7, #4] 8002a12: 681b ldr r3, [r3, #0] 8002a14: 681b ldr r3, [r3, #0] 8002a16: f003 0301 and.w r3, r3, #1 8002a1a: 2b00 cmp r3, #0 8002a1c: d1c8 bne.n 80029b0 } } /* Get the CR register value */ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR; 8002a1e: 687b ldr r3, [r7, #4] 8002a20: 681b ldr r3, [r3, #0] 8002a22: 681b ldr r3, [r3, #0] 8002a24: 617b str r3, [r7, #20] /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ 8002a26: 697a ldr r2, [r7, #20] 8002a28: 4b83 ldr r3, [pc, #524] @ (8002c38 ) 8002a2a: 4013 ands r3, r2 8002a2c: 617b str r3, [r7, #20] DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); /* Prepare the DMA Stream configuration */ registerValue |= hdma->Init.Direction | 8002a2e: 687b ldr r3, [r7, #4] 8002a30: 689a ldr r2, [r3, #8] hdma->Init.PeriphInc | hdma->Init.MemInc | 8002a32: 687b ldr r3, [r7, #4] 8002a34: 68db ldr r3, [r3, #12] registerValue |= hdma->Init.Direction | 8002a36: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8002a38: 687b ldr r3, [r7, #4] 8002a3a: 691b ldr r3, [r3, #16] 8002a3c: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8002a3e: 687b ldr r3, [r7, #4] 8002a40: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 8002a42: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8002a44: 687b ldr r3, [r7, #4] 8002a46: 699b ldr r3, [r3, #24] 8002a48: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8002a4a: 687b ldr r3, [r7, #4] 8002a4c: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8002a4e: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8002a50: 687b ldr r3, [r7, #4] 8002a52: 6a1b ldr r3, [r3, #32] 8002a54: 4313 orrs r3, r2 registerValue |= hdma->Init.Direction | 8002a56: 697a ldr r2, [r7, #20] 8002a58: 4313 orrs r3, r2 8002a5a: 617b str r3, [r7, #20] /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8002a5c: 687b ldr r3, [r7, #4] 8002a5e: 6a5b ldr r3, [r3, #36] @ 0x24 8002a60: 2b04 cmp r3, #4 8002a62: d107 bne.n 8002a74 { /* Get memory burst and peripheral burst */ registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; 8002a64: 687b ldr r3, [r7, #4] 8002a66: 6ada ldr r2, [r3, #44] @ 0x2c 8002a68: 687b ldr r3, [r7, #4] 8002a6a: 6b1b ldr r3, [r3, #48] @ 0x30 8002a6c: 4313 orrs r3, r2 8002a6e: 697a ldr r2, [r7, #20] 8002a70: 4313 orrs r3, r2 8002a72: 617b str r3, [r7, #20] } /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be lock when transferring data to/from USART/UART */ #if (STM32H7_DEV_ID == 0x450UL) if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U) 8002a74: 4b71 ldr r3, [pc, #452] @ (8002c3c ) 8002a76: 681a ldr r2, [r3, #0] 8002a78: 4b71 ldr r3, [pc, #452] @ (8002c40 ) 8002a7a: 4013 ands r3, r2 8002a7c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8002a80: d328 bcc.n 8002ad4 { #endif /* STM32H7_DEV_ID == 0x450UL */ if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U) 8002a82: 687b ldr r3, [r7, #4] 8002a84: 685b ldr r3, [r3, #4] 8002a86: 2b28 cmp r3, #40 @ 0x28 8002a88: d903 bls.n 8002a92 8002a8a: 687b ldr r3, [r7, #4] 8002a8c: 685b ldr r3, [r3, #4] 8002a8e: 2b2e cmp r3, #46 @ 0x2e 8002a90: d917 bls.n 8002ac2 8002a92: 687b ldr r3, [r7, #4] 8002a94: 685b ldr r3, [r3, #4] 8002a96: 2b3e cmp r3, #62 @ 0x3e 8002a98: d903 bls.n 8002aa2 8002a9a: 687b ldr r3, [r7, #4] 8002a9c: 685b ldr r3, [r3, #4] 8002a9e: 2b42 cmp r3, #66 @ 0x42 8002aa0: d90f bls.n 8002ac2 8002aa2: 687b ldr r3, [r7, #4] 8002aa4: 685b ldr r3, [r3, #4] 8002aa6: 2b46 cmp r3, #70 @ 0x46 8002aa8: d903 bls.n 8002ab2 8002aaa: 687b ldr r3, [r7, #4] 8002aac: 685b ldr r3, [r3, #4] 8002aae: 2b48 cmp r3, #72 @ 0x48 8002ab0: d907 bls.n 8002ac2 8002ab2: 687b ldr r3, [r7, #4] 8002ab4: 685b ldr r3, [r3, #4] 8002ab6: 2b4e cmp r3, #78 @ 0x4e 8002ab8: d905 bls.n 8002ac6 8002aba: 687b ldr r3, [r7, #4] 8002abc: 685b ldr r3, [r3, #4] 8002abe: 2b52 cmp r3, #82 @ 0x52 8002ac0: d801 bhi.n 8002ac6 8002ac2: 2301 movs r3, #1 8002ac4: e000 b.n 8002ac8 8002ac6: 2300 movs r3, #0 8002ac8: 2b00 cmp r3, #0 8002aca: d003 beq.n 8002ad4 { registerValue |= DMA_SxCR_TRBUFF; 8002acc: 697b ldr r3, [r7, #20] 8002ace: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8002ad2: 617b str r3, [r7, #20] #if (STM32H7_DEV_ID == 0x450UL) } #endif /* STM32H7_DEV_ID == 0x450UL */ /* Write to DMA Stream CR register */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; 8002ad4: 687b ldr r3, [r7, #4] 8002ad6: 681b ldr r3, [r3, #0] 8002ad8: 697a ldr r2, [r7, #20] 8002ada: 601a str r2, [r3, #0] /* Get the FCR register value */ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR; 8002adc: 687b ldr r3, [r7, #4] 8002ade: 681b ldr r3, [r3, #0] 8002ae0: 695b ldr r3, [r3, #20] 8002ae2: 617b str r3, [r7, #20] /* Clear Direct mode and FIFO threshold bits */ registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 8002ae4: 697b ldr r3, [r7, #20] 8002ae6: f023 0307 bic.w r3, r3, #7 8002aea: 617b str r3, [r7, #20] /* Prepare the DMA Stream FIFO configuration */ registerValue |= hdma->Init.FIFOMode; 8002aec: 687b ldr r3, [r7, #4] 8002aee: 6a5b ldr r3, [r3, #36] @ 0x24 8002af0: 697a ldr r2, [r7, #20] 8002af2: 4313 orrs r3, r2 8002af4: 617b str r3, [r7, #20] /* the FIFO threshold is not used when the FIFO mode is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8002af6: 687b ldr r3, [r7, #4] 8002af8: 6a5b ldr r3, [r3, #36] @ 0x24 8002afa: 2b04 cmp r3, #4 8002afc: d117 bne.n 8002b2e { /* Get the FIFO threshold */ registerValue |= hdma->Init.FIFOThreshold; 8002afe: 687b ldr r3, [r7, #4] 8002b00: 6a9b ldr r3, [r3, #40] @ 0x28 8002b02: 697a ldr r2, [r7, #20] 8002b04: 4313 orrs r3, r2 8002b06: 617b str r3, [r7, #20] /* Check compatibility between FIFO threshold level and size of the memory burst */ /* for INCR4, INCR8, INCR16 */ if(hdma->Init.MemBurst != DMA_MBURST_SINGLE) 8002b08: 687b ldr r3, [r7, #4] 8002b0a: 6adb ldr r3, [r3, #44] @ 0x2c 8002b0c: 2b00 cmp r3, #0 8002b0e: d00e beq.n 8002b2e { if (DMA_CheckFifoParam(hdma) != HAL_OK) 8002b10: 6878 ldr r0, [r7, #4] 8002b12: f001 ff1d bl 8004950 8002b16: 4603 mov r3, r0 8002b18: 2b00 cmp r3, #0 8002b1a: d008 beq.n 8002b2e { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8002b1c: 687b ldr r3, [r7, #4] 8002b1e: 2240 movs r2, #64 @ 0x40 8002b20: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002b22: 687b ldr r3, [r7, #4] 8002b24: 2201 movs r2, #1 8002b26: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 8002b2a: 2301 movs r3, #1 8002b2c: e197 b.n 8002e5e } } } /* Write to DMA Stream FCR */ ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue; 8002b2e: 687b ldr r3, [r7, #4] 8002b30: 681b ldr r3, [r3, #0] 8002b32: 697a ldr r2, [r7, #20] 8002b34: 615a str r2, [r3, #20] /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8002b36: 6878 ldr r0, [r7, #4] 8002b38: f001 fe58 bl 80047ec 8002b3c: 4603 mov r3, r0 8002b3e: 60bb str r3, [r7, #8] /* Clear all interrupt flags */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 8002b40: 687b ldr r3, [r7, #4] 8002b42: 6ddb ldr r3, [r3, #92] @ 0x5c 8002b44: f003 031f and.w r3, r3, #31 8002b48: 223f movs r2, #63 @ 0x3f 8002b4a: 409a lsls r2, r3 8002b4c: 68bb ldr r3, [r7, #8] 8002b4e: 609a str r2, [r3, #8] 8002b50: e0cd b.n 8002cee } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 8002b52: 687b ldr r3, [r7, #4] 8002b54: 681b ldr r3, [r3, #0] 8002b56: 4a3b ldr r2, [pc, #236] @ (8002c44 ) 8002b58: 4293 cmp r3, r2 8002b5a: d022 beq.n 8002ba2 8002b5c: 687b ldr r3, [r7, #4] 8002b5e: 681b ldr r3, [r3, #0] 8002b60: 4a39 ldr r2, [pc, #228] @ (8002c48 ) 8002b62: 4293 cmp r3, r2 8002b64: d01d beq.n 8002ba2 8002b66: 687b ldr r3, [r7, #4] 8002b68: 681b ldr r3, [r3, #0] 8002b6a: 4a38 ldr r2, [pc, #224] @ (8002c4c ) 8002b6c: 4293 cmp r3, r2 8002b6e: d018 beq.n 8002ba2 8002b70: 687b ldr r3, [r7, #4] 8002b72: 681b ldr r3, [r3, #0] 8002b74: 4a36 ldr r2, [pc, #216] @ (8002c50 ) 8002b76: 4293 cmp r3, r2 8002b78: d013 beq.n 8002ba2 8002b7a: 687b ldr r3, [r7, #4] 8002b7c: 681b ldr r3, [r3, #0] 8002b7e: 4a35 ldr r2, [pc, #212] @ (8002c54 ) 8002b80: 4293 cmp r3, r2 8002b82: d00e beq.n 8002ba2 8002b84: 687b ldr r3, [r7, #4] 8002b86: 681b ldr r3, [r3, #0] 8002b88: 4a33 ldr r2, [pc, #204] @ (8002c58 ) 8002b8a: 4293 cmp r3, r2 8002b8c: d009 beq.n 8002ba2 8002b8e: 687b ldr r3, [r7, #4] 8002b90: 681b ldr r3, [r3, #0] 8002b92: 4a32 ldr r2, [pc, #200] @ (8002c5c ) 8002b94: 4293 cmp r3, r2 8002b96: d004 beq.n 8002ba2 8002b98: 687b ldr r3, [r7, #4] 8002b9a: 681b ldr r3, [r3, #0] 8002b9c: 4a30 ldr r2, [pc, #192] @ (8002c60 ) 8002b9e: 4293 cmp r3, r2 8002ba0: d101 bne.n 8002ba6 8002ba2: 2301 movs r3, #1 8002ba4: e000 b.n 8002ba8 8002ba6: 2300 movs r3, #0 8002ba8: 2b00 cmp r3, #0 8002baa: f000 8097 beq.w 8002cdc { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 8002bae: 687b ldr r3, [r7, #4] 8002bb0: 681b ldr r3, [r3, #0] 8002bb2: 4a24 ldr r2, [pc, #144] @ (8002c44 ) 8002bb4: 4293 cmp r3, r2 8002bb6: d021 beq.n 8002bfc 8002bb8: 687b ldr r3, [r7, #4] 8002bba: 681b ldr r3, [r3, #0] 8002bbc: 4a22 ldr r2, [pc, #136] @ (8002c48 ) 8002bbe: 4293 cmp r3, r2 8002bc0: d01c beq.n 8002bfc 8002bc2: 687b ldr r3, [r7, #4] 8002bc4: 681b ldr r3, [r3, #0] 8002bc6: 4a21 ldr r2, [pc, #132] @ (8002c4c ) 8002bc8: 4293 cmp r3, r2 8002bca: d017 beq.n 8002bfc 8002bcc: 687b ldr r3, [r7, #4] 8002bce: 681b ldr r3, [r3, #0] 8002bd0: 4a1f ldr r2, [pc, #124] @ (8002c50 ) 8002bd2: 4293 cmp r3, r2 8002bd4: d012 beq.n 8002bfc 8002bd6: 687b ldr r3, [r7, #4] 8002bd8: 681b ldr r3, [r3, #0] 8002bda: 4a1e ldr r2, [pc, #120] @ (8002c54 ) 8002bdc: 4293 cmp r3, r2 8002bde: d00d beq.n 8002bfc 8002be0: 687b ldr r3, [r7, #4] 8002be2: 681b ldr r3, [r3, #0] 8002be4: 4a1c ldr r2, [pc, #112] @ (8002c58 ) 8002be6: 4293 cmp r3, r2 8002be8: d008 beq.n 8002bfc 8002bea: 687b ldr r3, [r7, #4] 8002bec: 681b ldr r3, [r3, #0] 8002bee: 4a1b ldr r2, [pc, #108] @ (8002c5c ) 8002bf0: 4293 cmp r3, r2 8002bf2: d003 beq.n 8002bfc 8002bf4: 687b ldr r3, [r7, #4] 8002bf6: 681b ldr r3, [r3, #0] 8002bf8: 4a19 ldr r2, [pc, #100] @ (8002c60 ) 8002bfa: 4293 cmp r3, r2 /* Check the request parameter */ assert_param(IS_BDMA_REQUEST(hdma->Init.Request)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8002bfc: 687b ldr r3, [r7, #4] 8002bfe: 2202 movs r2, #2 8002c00: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 8002c04: 687b ldr r3, [r7, #4] 8002c06: 2200 movs r2, #0 8002c08: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Get the CR register value */ registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR; 8002c0c: 687b ldr r3, [r7, #4] 8002c0e: 681b ldr r3, [r3, #0] 8002c10: 681b ldr r3, [r3, #0] 8002c12: 617b str r3, [r7, #20] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */ registerValue &= ((uint32_t)~(BDMA_CCR_PL | BDMA_CCR_MSIZE | BDMA_CCR_PSIZE | \ 8002c14: 697a ldr r2, [r7, #20] 8002c16: 4b13 ldr r3, [pc, #76] @ (8002c64 ) 8002c18: 4013 ands r3, r2 8002c1a: 617b str r3, [r7, #20] BDMA_CCR_MINC | BDMA_CCR_PINC | BDMA_CCR_CIRC | \ BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM | \ BDMA_CCR_CT)); /* Prepare the DMA Channel configuration */ registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 8002c1c: 687b ldr r3, [r7, #4] 8002c1e: 689b ldr r3, [r3, #8] 8002c20: 2b40 cmp r3, #64 @ 0x40 8002c22: d021 beq.n 8002c68 8002c24: 687b ldr r3, [r7, #4] 8002c26: 689b ldr r3, [r3, #8] 8002c28: 2b80 cmp r3, #128 @ 0x80 8002c2a: d102 bne.n 8002c32 8002c2c: f44f 4380 mov.w r3, #16384 @ 0x4000 8002c30: e01b b.n 8002c6a 8002c32: 2300 movs r3, #0 8002c34: e019 b.n 8002c6a 8002c36: bf00 nop 8002c38: fe10803f .word 0xfe10803f 8002c3c: 5c001000 .word 0x5c001000 8002c40: ffff0000 .word 0xffff0000 8002c44: 58025408 .word 0x58025408 8002c48: 5802541c .word 0x5802541c 8002c4c: 58025430 .word 0x58025430 8002c50: 58025444 .word 0x58025444 8002c54: 58025458 .word 0x58025458 8002c58: 5802546c .word 0x5802546c 8002c5c: 58025480 .word 0x58025480 8002c60: 58025494 .word 0x58025494 8002c64: fffe000f .word 0xfffe000f 8002c68: 2310 movs r3, #16 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 8002c6a: 687a ldr r2, [r7, #4] 8002c6c: 68d2 ldr r2, [r2, #12] 8002c6e: 08d2 lsrs r2, r2, #3 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 8002c70: 431a orrs r2, r3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 8002c72: 687b ldr r3, [r7, #4] 8002c74: 691b ldr r3, [r3, #16] 8002c76: 08db lsrs r3, r3, #3 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 8002c78: 431a orrs r2, r3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 8002c7a: 687b ldr r3, [r7, #4] 8002c7c: 695b ldr r3, [r3, #20] 8002c7e: 08db lsrs r3, r3, #3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 8002c80: 431a orrs r2, r3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 8002c82: 687b ldr r3, [r7, #4] 8002c84: 699b ldr r3, [r3, #24] 8002c86: 08db lsrs r3, r3, #3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 8002c88: 431a orrs r2, r3 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 8002c8a: 687b ldr r3, [r7, #4] 8002c8c: 69db ldr r3, [r3, #28] 8002c8e: 08db lsrs r3, r3, #3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 8002c90: 431a orrs r2, r3 DMA_TO_BDMA_PRIORITY(hdma->Init.Priority); 8002c92: 687b ldr r3, [r7, #4] 8002c94: 6a1b ldr r3, [r3, #32] 8002c96: 091b lsrs r3, r3, #4 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 8002c98: 4313 orrs r3, r2 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 8002c9a: 697a ldr r2, [r7, #20] 8002c9c: 4313 orrs r3, r2 8002c9e: 617b str r3, [r7, #20] /* Write to DMA Channel CR register */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue; 8002ca0: 687b ldr r3, [r7, #4] 8002ca2: 681b ldr r3, [r3, #0] 8002ca4: 697a ldr r2, [r7, #20] 8002ca6: 601a str r2, [r3, #0] /* calculation of the channel index */ hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U; 8002ca8: 687b ldr r3, [r7, #4] 8002caa: 681b ldr r3, [r3, #0] 8002cac: 461a mov r2, r3 8002cae: 4b6e ldr r3, [pc, #440] @ (8002e68 ) 8002cb0: 4413 add r3, r2 8002cb2: 4a6e ldr r2, [pc, #440] @ (8002e6c ) 8002cb4: fba2 2303 umull r2, r3, r2, r3 8002cb8: 091b lsrs r3, r3, #4 8002cba: 009a lsls r2, r3, #2 8002cbc: 687b ldr r3, [r7, #4] 8002cbe: 65da str r2, [r3, #92] @ 0x5c /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8002cc0: 6878 ldr r0, [r7, #4] 8002cc2: f001 fd93 bl 80047ec 8002cc6: 4603 mov r3, r0 8002cc8: 60fb str r3, [r7, #12] /* Clear all interrupt flags */ regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 8002cca: 687b ldr r3, [r7, #4] 8002ccc: 6ddb ldr r3, [r3, #92] @ 0x5c 8002cce: f003 031f and.w r3, r3, #31 8002cd2: 2201 movs r2, #1 8002cd4: 409a lsls r2, r3 8002cd6: 68fb ldr r3, [r7, #12] 8002cd8: 605a str r2, [r3, #4] 8002cda: e008 b.n 8002cee } else { hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8002cdc: 687b ldr r3, [r7, #4] 8002cde: 2240 movs r2, #64 @ 0x40 8002ce0: 655a str r2, [r3, #84] @ 0x54 hdma->State = HAL_DMA_STATE_ERROR; 8002ce2: 687b ldr r3, [r7, #4] 8002ce4: 2203 movs r2, #3 8002ce6: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 8002cea: 2301 movs r3, #1 8002cec: e0b7 b.n 8002e5e } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8002cee: 687b ldr r3, [r7, #4] 8002cf0: 681b ldr r3, [r3, #0] 8002cf2: 4a5f ldr r2, [pc, #380] @ (8002e70 ) 8002cf4: 4293 cmp r3, r2 8002cf6: d072 beq.n 8002dde 8002cf8: 687b ldr r3, [r7, #4] 8002cfa: 681b ldr r3, [r3, #0] 8002cfc: 4a5d ldr r2, [pc, #372] @ (8002e74 ) 8002cfe: 4293 cmp r3, r2 8002d00: d06d beq.n 8002dde 8002d02: 687b ldr r3, [r7, #4] 8002d04: 681b ldr r3, [r3, #0] 8002d06: 4a5c ldr r2, [pc, #368] @ (8002e78 ) 8002d08: 4293 cmp r3, r2 8002d0a: d068 beq.n 8002dde 8002d0c: 687b ldr r3, [r7, #4] 8002d0e: 681b ldr r3, [r3, #0] 8002d10: 4a5a ldr r2, [pc, #360] @ (8002e7c ) 8002d12: 4293 cmp r3, r2 8002d14: d063 beq.n 8002dde 8002d16: 687b ldr r3, [r7, #4] 8002d18: 681b ldr r3, [r3, #0] 8002d1a: 4a59 ldr r2, [pc, #356] @ (8002e80 ) 8002d1c: 4293 cmp r3, r2 8002d1e: d05e beq.n 8002dde 8002d20: 687b ldr r3, [r7, #4] 8002d22: 681b ldr r3, [r3, #0] 8002d24: 4a57 ldr r2, [pc, #348] @ (8002e84 ) 8002d26: 4293 cmp r3, r2 8002d28: d059 beq.n 8002dde 8002d2a: 687b ldr r3, [r7, #4] 8002d2c: 681b ldr r3, [r3, #0] 8002d2e: 4a56 ldr r2, [pc, #344] @ (8002e88 ) 8002d30: 4293 cmp r3, r2 8002d32: d054 beq.n 8002dde 8002d34: 687b ldr r3, [r7, #4] 8002d36: 681b ldr r3, [r3, #0] 8002d38: 4a54 ldr r2, [pc, #336] @ (8002e8c ) 8002d3a: 4293 cmp r3, r2 8002d3c: d04f beq.n 8002dde 8002d3e: 687b ldr r3, [r7, #4] 8002d40: 681b ldr r3, [r3, #0] 8002d42: 4a53 ldr r2, [pc, #332] @ (8002e90 ) 8002d44: 4293 cmp r3, r2 8002d46: d04a beq.n 8002dde 8002d48: 687b ldr r3, [r7, #4] 8002d4a: 681b ldr r3, [r3, #0] 8002d4c: 4a51 ldr r2, [pc, #324] @ (8002e94 ) 8002d4e: 4293 cmp r3, r2 8002d50: d045 beq.n 8002dde 8002d52: 687b ldr r3, [r7, #4] 8002d54: 681b ldr r3, [r3, #0] 8002d56: 4a50 ldr r2, [pc, #320] @ (8002e98 ) 8002d58: 4293 cmp r3, r2 8002d5a: d040 beq.n 8002dde 8002d5c: 687b ldr r3, [r7, #4] 8002d5e: 681b ldr r3, [r3, #0] 8002d60: 4a4e ldr r2, [pc, #312] @ (8002e9c ) 8002d62: 4293 cmp r3, r2 8002d64: d03b beq.n 8002dde 8002d66: 687b ldr r3, [r7, #4] 8002d68: 681b ldr r3, [r3, #0] 8002d6a: 4a4d ldr r2, [pc, #308] @ (8002ea0 ) 8002d6c: 4293 cmp r3, r2 8002d6e: d036 beq.n 8002dde 8002d70: 687b ldr r3, [r7, #4] 8002d72: 681b ldr r3, [r3, #0] 8002d74: 4a4b ldr r2, [pc, #300] @ (8002ea4 ) 8002d76: 4293 cmp r3, r2 8002d78: d031 beq.n 8002dde 8002d7a: 687b ldr r3, [r7, #4] 8002d7c: 681b ldr r3, [r3, #0] 8002d7e: 4a4a ldr r2, [pc, #296] @ (8002ea8 ) 8002d80: 4293 cmp r3, r2 8002d82: d02c beq.n 8002dde 8002d84: 687b ldr r3, [r7, #4] 8002d86: 681b ldr r3, [r3, #0] 8002d88: 4a48 ldr r2, [pc, #288] @ (8002eac ) 8002d8a: 4293 cmp r3, r2 8002d8c: d027 beq.n 8002dde 8002d8e: 687b ldr r3, [r7, #4] 8002d90: 681b ldr r3, [r3, #0] 8002d92: 4a47 ldr r2, [pc, #284] @ (8002eb0 ) 8002d94: 4293 cmp r3, r2 8002d96: d022 beq.n 8002dde 8002d98: 687b ldr r3, [r7, #4] 8002d9a: 681b ldr r3, [r3, #0] 8002d9c: 4a45 ldr r2, [pc, #276] @ (8002eb4 ) 8002d9e: 4293 cmp r3, r2 8002da0: d01d beq.n 8002dde 8002da2: 687b ldr r3, [r7, #4] 8002da4: 681b ldr r3, [r3, #0] 8002da6: 4a44 ldr r2, [pc, #272] @ (8002eb8 ) 8002da8: 4293 cmp r3, r2 8002daa: d018 beq.n 8002dde 8002dac: 687b ldr r3, [r7, #4] 8002dae: 681b ldr r3, [r3, #0] 8002db0: 4a42 ldr r2, [pc, #264] @ (8002ebc ) 8002db2: 4293 cmp r3, r2 8002db4: d013 beq.n 8002dde 8002db6: 687b ldr r3, [r7, #4] 8002db8: 681b ldr r3, [r3, #0] 8002dba: 4a41 ldr r2, [pc, #260] @ (8002ec0 ) 8002dbc: 4293 cmp r3, r2 8002dbe: d00e beq.n 8002dde 8002dc0: 687b ldr r3, [r7, #4] 8002dc2: 681b ldr r3, [r3, #0] 8002dc4: 4a3f ldr r2, [pc, #252] @ (8002ec4 ) 8002dc6: 4293 cmp r3, r2 8002dc8: d009 beq.n 8002dde 8002dca: 687b ldr r3, [r7, #4] 8002dcc: 681b ldr r3, [r3, #0] 8002dce: 4a3e ldr r2, [pc, #248] @ (8002ec8 ) 8002dd0: 4293 cmp r3, r2 8002dd2: d004 beq.n 8002dde 8002dd4: 687b ldr r3, [r7, #4] 8002dd6: 681b ldr r3, [r3, #0] 8002dd8: 4a3c ldr r2, [pc, #240] @ (8002ecc ) 8002dda: 4293 cmp r3, r2 8002ddc: d101 bne.n 8002de2 8002dde: 2301 movs r3, #1 8002de0: e000 b.n 8002de4 8002de2: 2300 movs r3, #0 8002de4: 2b00 cmp r3, #0 8002de6: d032 beq.n 8002e4e { /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); 8002de8: 6878 ldr r0, [r7, #4] 8002dea: f001 fe2d bl 8004a48 if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 8002dee: 687b ldr r3, [r7, #4] 8002df0: 689b ldr r3, [r3, #8] 8002df2: 2b80 cmp r3, #128 @ 0x80 8002df4: d102 bne.n 8002dfc { /* if memory to memory force the request to 0*/ hdma->Init.Request = DMA_REQUEST_MEM2MEM; 8002df6: 687b ldr r3, [r7, #4] 8002df8: 2200 movs r2, #0 8002dfa: 605a str r2, [r3, #4] } /* Set peripheral request to DMAMUX channel */ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 8002dfc: 687b ldr r3, [r7, #4] 8002dfe: 685a ldr r2, [r3, #4] 8002e00: 687b ldr r3, [r7, #4] 8002e02: 6e1b ldr r3, [r3, #96] @ 0x60 8002e04: b2d2 uxtb r2, r2 8002e06: 601a str r2, [r3, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8002e08: 687b ldr r3, [r7, #4] 8002e0a: 6e5b ldr r3, [r3, #100] @ 0x64 8002e0c: 687a ldr r2, [r7, #4] 8002e0e: 6e92 ldr r2, [r2, #104] @ 0x68 8002e10: 605a str r2, [r3, #4] /* Initialize parameters for DMAMUX request generator : if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7 */ if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) 8002e12: 687b ldr r3, [r7, #4] 8002e14: 685b ldr r3, [r3, #4] 8002e16: 2b00 cmp r3, #0 8002e18: d010 beq.n 8002e3c 8002e1a: 687b ldr r3, [r7, #4] 8002e1c: 685b ldr r3, [r3, #4] 8002e1e: 2b08 cmp r3, #8 8002e20: d80c bhi.n 8002e3c { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); 8002e22: 6878 ldr r0, [r7, #4] 8002e24: f001 feaa bl 8004b7c /* Reset the DMAMUX request generator register */ hdma->DMAmuxRequestGen->RGCR = 0U; 8002e28: 687b ldr r3, [r7, #4] 8002e2a: 6edb ldr r3, [r3, #108] @ 0x6c 8002e2c: 2200 movs r2, #0 8002e2e: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8002e30: 687b ldr r3, [r7, #4] 8002e32: 6f1b ldr r3, [r3, #112] @ 0x70 8002e34: 687a ldr r2, [r7, #4] 8002e36: 6f52 ldr r2, [r2, #116] @ 0x74 8002e38: 605a str r2, [r3, #4] 8002e3a: e008 b.n 8002e4e } else { hdma->DMAmuxRequestGen = 0U; 8002e3c: 687b ldr r3, [r7, #4] 8002e3e: 2200 movs r2, #0 8002e40: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = 0U; 8002e42: 687b ldr r3, [r7, #4] 8002e44: 2200 movs r2, #0 8002e46: 671a str r2, [r3, #112] @ 0x70 hdma->DMAmuxRequestGenStatusMask = 0U; 8002e48: 687b ldr r3, [r7, #4] 8002e4a: 2200 movs r2, #0 8002e4c: 675a str r2, [r3, #116] @ 0x74 } } /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8002e4e: 687b ldr r3, [r7, #4] 8002e50: 2200 movs r2, #0 8002e52: 655a str r2, [r3, #84] @ 0x54 /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002e54: 687b ldr r3, [r7, #4] 8002e56: 2201 movs r2, #1 8002e58: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_OK; 8002e5c: 2300 movs r3, #0 } 8002e5e: 4618 mov r0, r3 8002e60: 3718 adds r7, #24 8002e62: 46bd mov sp, r7 8002e64: bd80 pop {r7, pc} 8002e66: bf00 nop 8002e68: a7fdabf8 .word 0xa7fdabf8 8002e6c: cccccccd .word 0xcccccccd 8002e70: 40020010 .word 0x40020010 8002e74: 40020028 .word 0x40020028 8002e78: 40020040 .word 0x40020040 8002e7c: 40020058 .word 0x40020058 8002e80: 40020070 .word 0x40020070 8002e84: 40020088 .word 0x40020088 8002e88: 400200a0 .word 0x400200a0 8002e8c: 400200b8 .word 0x400200b8 8002e90: 40020410 .word 0x40020410 8002e94: 40020428 .word 0x40020428 8002e98: 40020440 .word 0x40020440 8002e9c: 40020458 .word 0x40020458 8002ea0: 40020470 .word 0x40020470 8002ea4: 40020488 .word 0x40020488 8002ea8: 400204a0 .word 0x400204a0 8002eac: 400204b8 .word 0x400204b8 8002eb0: 58025408 .word 0x58025408 8002eb4: 5802541c .word 0x5802541c 8002eb8: 58025430 .word 0x58025430 8002ebc: 58025444 .word 0x58025444 8002ec0: 58025458 .word 0x58025458 8002ec4: 5802546c .word 0x5802546c 8002ec8: 58025480 .word 0x58025480 8002ecc: 58025494 .word 0x58025494 08002ed0 : * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8002ed0: b580 push {r7, lr} 8002ed2: b086 sub sp, #24 8002ed4: af00 add r7, sp, #0 8002ed6: 6078 str r0, [r7, #4] /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma; BDMA_Base_Registers *regs_bdma; const __IO uint32_t *enableRegister; uint32_t tickstart = HAL_GetTick(); 8002ed8: f7fe fc04 bl 80016e4 8002edc: 6138 str r0, [r7, #16] /* Check the DMA peripheral handle */ if(hdma == NULL) 8002ede: 687b ldr r3, [r7, #4] 8002ee0: 2b00 cmp r3, #0 8002ee2: d101 bne.n 8002ee8 { return HAL_ERROR; 8002ee4: 2301 movs r3, #1 8002ee6: e2dc b.n 80034a2 } /* Check the DMA peripheral state */ if(hdma->State != HAL_DMA_STATE_BUSY) 8002ee8: 687b ldr r3, [r7, #4] 8002eea: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8002eee: b2db uxtb r3, r3 8002ef0: 2b02 cmp r3, #2 8002ef2: d008 beq.n 8002f06 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8002ef4: 687b ldr r3, [r7, #4] 8002ef6: 2280 movs r2, #128 @ 0x80 8002ef8: 655a str r2, [r3, #84] @ 0x54 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002efa: 687b ldr r3, [r7, #4] 8002efc: 2200 movs r2, #0 8002efe: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 8002f02: 2301 movs r3, #1 8002f04: e2cd b.n 80034a2 } else { /* Disable all the transfer interrupts */ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8002f06: 687b ldr r3, [r7, #4] 8002f08: 681b ldr r3, [r3, #0] 8002f0a: 4a76 ldr r2, [pc, #472] @ (80030e4 ) 8002f0c: 4293 cmp r3, r2 8002f0e: d04a beq.n 8002fa6 8002f10: 687b ldr r3, [r7, #4] 8002f12: 681b ldr r3, [r3, #0] 8002f14: 4a74 ldr r2, [pc, #464] @ (80030e8 ) 8002f16: 4293 cmp r3, r2 8002f18: d045 beq.n 8002fa6 8002f1a: 687b ldr r3, [r7, #4] 8002f1c: 681b ldr r3, [r3, #0] 8002f1e: 4a73 ldr r2, [pc, #460] @ (80030ec ) 8002f20: 4293 cmp r3, r2 8002f22: d040 beq.n 8002fa6 8002f24: 687b ldr r3, [r7, #4] 8002f26: 681b ldr r3, [r3, #0] 8002f28: 4a71 ldr r2, [pc, #452] @ (80030f0 ) 8002f2a: 4293 cmp r3, r2 8002f2c: d03b beq.n 8002fa6 8002f2e: 687b ldr r3, [r7, #4] 8002f30: 681b ldr r3, [r3, #0] 8002f32: 4a70 ldr r2, [pc, #448] @ (80030f4 ) 8002f34: 4293 cmp r3, r2 8002f36: d036 beq.n 8002fa6 8002f38: 687b ldr r3, [r7, #4] 8002f3a: 681b ldr r3, [r3, #0] 8002f3c: 4a6e ldr r2, [pc, #440] @ (80030f8 ) 8002f3e: 4293 cmp r3, r2 8002f40: d031 beq.n 8002fa6 8002f42: 687b ldr r3, [r7, #4] 8002f44: 681b ldr r3, [r3, #0] 8002f46: 4a6d ldr r2, [pc, #436] @ (80030fc ) 8002f48: 4293 cmp r3, r2 8002f4a: d02c beq.n 8002fa6 8002f4c: 687b ldr r3, [r7, #4] 8002f4e: 681b ldr r3, [r3, #0] 8002f50: 4a6b ldr r2, [pc, #428] @ (8003100 ) 8002f52: 4293 cmp r3, r2 8002f54: d027 beq.n 8002fa6 8002f56: 687b ldr r3, [r7, #4] 8002f58: 681b ldr r3, [r3, #0] 8002f5a: 4a6a ldr r2, [pc, #424] @ (8003104 ) 8002f5c: 4293 cmp r3, r2 8002f5e: d022 beq.n 8002fa6 8002f60: 687b ldr r3, [r7, #4] 8002f62: 681b ldr r3, [r3, #0] 8002f64: 4a68 ldr r2, [pc, #416] @ (8003108 ) 8002f66: 4293 cmp r3, r2 8002f68: d01d beq.n 8002fa6 8002f6a: 687b ldr r3, [r7, #4] 8002f6c: 681b ldr r3, [r3, #0] 8002f6e: 4a67 ldr r2, [pc, #412] @ (800310c ) 8002f70: 4293 cmp r3, r2 8002f72: d018 beq.n 8002fa6 8002f74: 687b ldr r3, [r7, #4] 8002f76: 681b ldr r3, [r3, #0] 8002f78: 4a65 ldr r2, [pc, #404] @ (8003110 ) 8002f7a: 4293 cmp r3, r2 8002f7c: d013 beq.n 8002fa6 8002f7e: 687b ldr r3, [r7, #4] 8002f80: 681b ldr r3, [r3, #0] 8002f82: 4a64 ldr r2, [pc, #400] @ (8003114 ) 8002f84: 4293 cmp r3, r2 8002f86: d00e beq.n 8002fa6 8002f88: 687b ldr r3, [r7, #4] 8002f8a: 681b ldr r3, [r3, #0] 8002f8c: 4a62 ldr r2, [pc, #392] @ (8003118 ) 8002f8e: 4293 cmp r3, r2 8002f90: d009 beq.n 8002fa6 8002f92: 687b ldr r3, [r7, #4] 8002f94: 681b ldr r3, [r3, #0] 8002f96: 4a61 ldr r2, [pc, #388] @ (800311c ) 8002f98: 4293 cmp r3, r2 8002f9a: d004 beq.n 8002fa6 8002f9c: 687b ldr r3, [r7, #4] 8002f9e: 681b ldr r3, [r3, #0] 8002fa0: 4a5f ldr r2, [pc, #380] @ (8003120 ) 8002fa2: 4293 cmp r3, r2 8002fa4: d101 bne.n 8002faa 8002fa6: 2301 movs r3, #1 8002fa8: e000 b.n 8002fac 8002faa: 2300 movs r3, #0 8002fac: 2b00 cmp r3, #0 8002fae: d013 beq.n 8002fd8 { /* Disable DMA All Interrupts */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); 8002fb0: 687b ldr r3, [r7, #4] 8002fb2: 681b ldr r3, [r3, #0] 8002fb4: 681a ldr r2, [r3, #0] 8002fb6: 687b ldr r3, [r7, #4] 8002fb8: 681b ldr r3, [r3, #0] 8002fba: f022 021e bic.w r2, r2, #30 8002fbe: 601a str r2, [r3, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 8002fc0: 687b ldr r3, [r7, #4] 8002fc2: 681b ldr r3, [r3, #0] 8002fc4: 695a ldr r2, [r3, #20] 8002fc6: 687b ldr r3, [r7, #4] 8002fc8: 681b ldr r3, [r3, #0] 8002fca: f022 0280 bic.w r2, r2, #128 @ 0x80 8002fce: 615a str r2, [r3, #20] enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef *)hdma->Instance)->CR)); 8002fd0: 687b ldr r3, [r7, #4] 8002fd2: 681b ldr r3, [r3, #0] 8002fd4: 617b str r3, [r7, #20] 8002fd6: e00a b.n 8002fee } else /* BDMA channel */ { /* Disable DMA All Interrupts */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 8002fd8: 687b ldr r3, [r7, #4] 8002fda: 681b ldr r3, [r3, #0] 8002fdc: 681a ldr r2, [r3, #0] 8002fde: 687b ldr r3, [r7, #4] 8002fe0: 681b ldr r3, [r3, #0] 8002fe2: f022 020e bic.w r2, r2, #14 8002fe6: 601a str r2, [r3, #0] enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR)); 8002fe8: 687b ldr r3, [r7, #4] 8002fea: 681b ldr r3, [r3, #0] 8002fec: 617b str r3, [r7, #20] } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8002fee: 687b ldr r3, [r7, #4] 8002ff0: 681b ldr r3, [r3, #0] 8002ff2: 4a3c ldr r2, [pc, #240] @ (80030e4 ) 8002ff4: 4293 cmp r3, r2 8002ff6: d072 beq.n 80030de 8002ff8: 687b ldr r3, [r7, #4] 8002ffa: 681b ldr r3, [r3, #0] 8002ffc: 4a3a ldr r2, [pc, #232] @ (80030e8 ) 8002ffe: 4293 cmp r3, r2 8003000: d06d beq.n 80030de 8003002: 687b ldr r3, [r7, #4] 8003004: 681b ldr r3, [r3, #0] 8003006: 4a39 ldr r2, [pc, #228] @ (80030ec ) 8003008: 4293 cmp r3, r2 800300a: d068 beq.n 80030de 800300c: 687b ldr r3, [r7, #4] 800300e: 681b ldr r3, [r3, #0] 8003010: 4a37 ldr r2, [pc, #220] @ (80030f0 ) 8003012: 4293 cmp r3, r2 8003014: d063 beq.n 80030de 8003016: 687b ldr r3, [r7, #4] 8003018: 681b ldr r3, [r3, #0] 800301a: 4a36 ldr r2, [pc, #216] @ (80030f4 ) 800301c: 4293 cmp r3, r2 800301e: d05e beq.n 80030de 8003020: 687b ldr r3, [r7, #4] 8003022: 681b ldr r3, [r3, #0] 8003024: 4a34 ldr r2, [pc, #208] @ (80030f8 ) 8003026: 4293 cmp r3, r2 8003028: d059 beq.n 80030de 800302a: 687b ldr r3, [r7, #4] 800302c: 681b ldr r3, [r3, #0] 800302e: 4a33 ldr r2, [pc, #204] @ (80030fc ) 8003030: 4293 cmp r3, r2 8003032: d054 beq.n 80030de 8003034: 687b ldr r3, [r7, #4] 8003036: 681b ldr r3, [r3, #0] 8003038: 4a31 ldr r2, [pc, #196] @ (8003100 ) 800303a: 4293 cmp r3, r2 800303c: d04f beq.n 80030de 800303e: 687b ldr r3, [r7, #4] 8003040: 681b ldr r3, [r3, #0] 8003042: 4a30 ldr r2, [pc, #192] @ (8003104 ) 8003044: 4293 cmp r3, r2 8003046: d04a beq.n 80030de 8003048: 687b ldr r3, [r7, #4] 800304a: 681b ldr r3, [r3, #0] 800304c: 4a2e ldr r2, [pc, #184] @ (8003108 ) 800304e: 4293 cmp r3, r2 8003050: d045 beq.n 80030de 8003052: 687b ldr r3, [r7, #4] 8003054: 681b ldr r3, [r3, #0] 8003056: 4a2d ldr r2, [pc, #180] @ (800310c ) 8003058: 4293 cmp r3, r2 800305a: d040 beq.n 80030de 800305c: 687b ldr r3, [r7, #4] 800305e: 681b ldr r3, [r3, #0] 8003060: 4a2b ldr r2, [pc, #172] @ (8003110 ) 8003062: 4293 cmp r3, r2 8003064: d03b beq.n 80030de 8003066: 687b ldr r3, [r7, #4] 8003068: 681b ldr r3, [r3, #0] 800306a: 4a2a ldr r2, [pc, #168] @ (8003114 ) 800306c: 4293 cmp r3, r2 800306e: d036 beq.n 80030de 8003070: 687b ldr r3, [r7, #4] 8003072: 681b ldr r3, [r3, #0] 8003074: 4a28 ldr r2, [pc, #160] @ (8003118 ) 8003076: 4293 cmp r3, r2 8003078: d031 beq.n 80030de 800307a: 687b ldr r3, [r7, #4] 800307c: 681b ldr r3, [r3, #0] 800307e: 4a27 ldr r2, [pc, #156] @ (800311c ) 8003080: 4293 cmp r3, r2 8003082: d02c beq.n 80030de 8003084: 687b ldr r3, [r7, #4] 8003086: 681b ldr r3, [r3, #0] 8003088: 4a25 ldr r2, [pc, #148] @ (8003120 ) 800308a: 4293 cmp r3, r2 800308c: d027 beq.n 80030de 800308e: 687b ldr r3, [r7, #4] 8003090: 681b ldr r3, [r3, #0] 8003092: 4a24 ldr r2, [pc, #144] @ (8003124 ) 8003094: 4293 cmp r3, r2 8003096: d022 beq.n 80030de 8003098: 687b ldr r3, [r7, #4] 800309a: 681b ldr r3, [r3, #0] 800309c: 4a22 ldr r2, [pc, #136] @ (8003128 ) 800309e: 4293 cmp r3, r2 80030a0: d01d beq.n 80030de 80030a2: 687b ldr r3, [r7, #4] 80030a4: 681b ldr r3, [r3, #0] 80030a6: 4a21 ldr r2, [pc, #132] @ (800312c ) 80030a8: 4293 cmp r3, r2 80030aa: d018 beq.n 80030de 80030ac: 687b ldr r3, [r7, #4] 80030ae: 681b ldr r3, [r3, #0] 80030b0: 4a1f ldr r2, [pc, #124] @ (8003130 ) 80030b2: 4293 cmp r3, r2 80030b4: d013 beq.n 80030de 80030b6: 687b ldr r3, [r7, #4] 80030b8: 681b ldr r3, [r3, #0] 80030ba: 4a1e ldr r2, [pc, #120] @ (8003134 ) 80030bc: 4293 cmp r3, r2 80030be: d00e beq.n 80030de 80030c0: 687b ldr r3, [r7, #4] 80030c2: 681b ldr r3, [r3, #0] 80030c4: 4a1c ldr r2, [pc, #112] @ (8003138 ) 80030c6: 4293 cmp r3, r2 80030c8: d009 beq.n 80030de 80030ca: 687b ldr r3, [r7, #4] 80030cc: 681b ldr r3, [r3, #0] 80030ce: 4a1b ldr r2, [pc, #108] @ (800313c ) 80030d0: 4293 cmp r3, r2 80030d2: d004 beq.n 80030de 80030d4: 687b ldr r3, [r7, #4] 80030d6: 681b ldr r3, [r3, #0] 80030d8: 4a19 ldr r2, [pc, #100] @ (8003140 ) 80030da: 4293 cmp r3, r2 80030dc: d132 bne.n 8003144 80030de: 2301 movs r3, #1 80030e0: e031 b.n 8003146 80030e2: bf00 nop 80030e4: 40020010 .word 0x40020010 80030e8: 40020028 .word 0x40020028 80030ec: 40020040 .word 0x40020040 80030f0: 40020058 .word 0x40020058 80030f4: 40020070 .word 0x40020070 80030f8: 40020088 .word 0x40020088 80030fc: 400200a0 .word 0x400200a0 8003100: 400200b8 .word 0x400200b8 8003104: 40020410 .word 0x40020410 8003108: 40020428 .word 0x40020428 800310c: 40020440 .word 0x40020440 8003110: 40020458 .word 0x40020458 8003114: 40020470 .word 0x40020470 8003118: 40020488 .word 0x40020488 800311c: 400204a0 .word 0x400204a0 8003120: 400204b8 .word 0x400204b8 8003124: 58025408 .word 0x58025408 8003128: 5802541c .word 0x5802541c 800312c: 58025430 .word 0x58025430 8003130: 58025444 .word 0x58025444 8003134: 58025458 .word 0x58025458 8003138: 5802546c .word 0x5802546c 800313c: 58025480 .word 0x58025480 8003140: 58025494 .word 0x58025494 8003144: 2300 movs r3, #0 8003146: 2b00 cmp r3, #0 8003148: d007 beq.n 800315a { /* disable the DMAMUX sync overrun IT */ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 800314a: 687b ldr r3, [r7, #4] 800314c: 6e1b ldr r3, [r3, #96] @ 0x60 800314e: 681a ldr r2, [r3, #0] 8003150: 687b ldr r3, [r7, #4] 8003152: 6e1b ldr r3, [r3, #96] @ 0x60 8003154: f422 7280 bic.w r2, r2, #256 @ 0x100 8003158: 601a str r2, [r3, #0] } /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 800315a: 687b ldr r3, [r7, #4] 800315c: 681b ldr r3, [r3, #0] 800315e: 4a6d ldr r2, [pc, #436] @ (8003314 ) 8003160: 4293 cmp r3, r2 8003162: d04a beq.n 80031fa 8003164: 687b ldr r3, [r7, #4] 8003166: 681b ldr r3, [r3, #0] 8003168: 4a6b ldr r2, [pc, #428] @ (8003318 ) 800316a: 4293 cmp r3, r2 800316c: d045 beq.n 80031fa 800316e: 687b ldr r3, [r7, #4] 8003170: 681b ldr r3, [r3, #0] 8003172: 4a6a ldr r2, [pc, #424] @ (800331c ) 8003174: 4293 cmp r3, r2 8003176: d040 beq.n 80031fa 8003178: 687b ldr r3, [r7, #4] 800317a: 681b ldr r3, [r3, #0] 800317c: 4a68 ldr r2, [pc, #416] @ (8003320 ) 800317e: 4293 cmp r3, r2 8003180: d03b beq.n 80031fa 8003182: 687b ldr r3, [r7, #4] 8003184: 681b ldr r3, [r3, #0] 8003186: 4a67 ldr r2, [pc, #412] @ (8003324 ) 8003188: 4293 cmp r3, r2 800318a: d036 beq.n 80031fa 800318c: 687b ldr r3, [r7, #4] 800318e: 681b ldr r3, [r3, #0] 8003190: 4a65 ldr r2, [pc, #404] @ (8003328 ) 8003192: 4293 cmp r3, r2 8003194: d031 beq.n 80031fa 8003196: 687b ldr r3, [r7, #4] 8003198: 681b ldr r3, [r3, #0] 800319a: 4a64 ldr r2, [pc, #400] @ (800332c ) 800319c: 4293 cmp r3, r2 800319e: d02c beq.n 80031fa 80031a0: 687b ldr r3, [r7, #4] 80031a2: 681b ldr r3, [r3, #0] 80031a4: 4a62 ldr r2, [pc, #392] @ (8003330 ) 80031a6: 4293 cmp r3, r2 80031a8: d027 beq.n 80031fa 80031aa: 687b ldr r3, [r7, #4] 80031ac: 681b ldr r3, [r3, #0] 80031ae: 4a61 ldr r2, [pc, #388] @ (8003334 ) 80031b0: 4293 cmp r3, r2 80031b2: d022 beq.n 80031fa 80031b4: 687b ldr r3, [r7, #4] 80031b6: 681b ldr r3, [r3, #0] 80031b8: 4a5f ldr r2, [pc, #380] @ (8003338 ) 80031ba: 4293 cmp r3, r2 80031bc: d01d beq.n 80031fa 80031be: 687b ldr r3, [r7, #4] 80031c0: 681b ldr r3, [r3, #0] 80031c2: 4a5e ldr r2, [pc, #376] @ (800333c ) 80031c4: 4293 cmp r3, r2 80031c6: d018 beq.n 80031fa 80031c8: 687b ldr r3, [r7, #4] 80031ca: 681b ldr r3, [r3, #0] 80031cc: 4a5c ldr r2, [pc, #368] @ (8003340 ) 80031ce: 4293 cmp r3, r2 80031d0: d013 beq.n 80031fa 80031d2: 687b ldr r3, [r7, #4] 80031d4: 681b ldr r3, [r3, #0] 80031d6: 4a5b ldr r2, [pc, #364] @ (8003344 ) 80031d8: 4293 cmp r3, r2 80031da: d00e beq.n 80031fa 80031dc: 687b ldr r3, [r7, #4] 80031de: 681b ldr r3, [r3, #0] 80031e0: 4a59 ldr r2, [pc, #356] @ (8003348 ) 80031e2: 4293 cmp r3, r2 80031e4: d009 beq.n 80031fa 80031e6: 687b ldr r3, [r7, #4] 80031e8: 681b ldr r3, [r3, #0] 80031ea: 4a58 ldr r2, [pc, #352] @ (800334c ) 80031ec: 4293 cmp r3, r2 80031ee: d004 beq.n 80031fa 80031f0: 687b ldr r3, [r7, #4] 80031f2: 681b ldr r3, [r3, #0] 80031f4: 4a56 ldr r2, [pc, #344] @ (8003350 ) 80031f6: 4293 cmp r3, r2 80031f8: d108 bne.n 800320c 80031fa: 687b ldr r3, [r7, #4] 80031fc: 681b ldr r3, [r3, #0] 80031fe: 681a ldr r2, [r3, #0] 8003200: 687b ldr r3, [r7, #4] 8003202: 681b ldr r3, [r3, #0] 8003204: f022 0201 bic.w r2, r2, #1 8003208: 601a str r2, [r3, #0] 800320a: e007 b.n 800321c 800320c: 687b ldr r3, [r7, #4] 800320e: 681b ldr r3, [r3, #0] 8003210: 681a ldr r2, [r3, #0] 8003212: 687b ldr r3, [r7, #4] 8003214: 681b ldr r3, [r3, #0] 8003216: f022 0201 bic.w r2, r2, #1 800321a: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while(((*enableRegister) & DMA_SxCR_EN) != 0U) 800321c: e013 b.n 8003246 { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 800321e: f7fe fa61 bl 80016e4 8003222: 4602 mov r2, r0 8003224: 693b ldr r3, [r7, #16] 8003226: 1ad3 subs r3, r2, r3 8003228: 2b05 cmp r3, #5 800322a: d90c bls.n 8003246 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 800322c: 687b ldr r3, [r7, #4] 800322e: 2220 movs r2, #32 8003230: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; 8003232: 687b ldr r3, [r7, #4] 8003234: 2203 movs r2, #3 8003236: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800323a: 687b ldr r3, [r7, #4] 800323c: 2200 movs r2, #0 800323e: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 8003242: 2301 movs r3, #1 8003244: e12d b.n 80034a2 while(((*enableRegister) & DMA_SxCR_EN) != 0U) 8003246: 697b ldr r3, [r7, #20] 8003248: 681b ldr r3, [r3, #0] 800324a: f003 0301 and.w r3, r3, #1 800324e: 2b00 cmp r3, #0 8003250: d1e5 bne.n 800321e } } /* Clear all interrupt flags at correct offset within the register */ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8003252: 687b ldr r3, [r7, #4] 8003254: 681b ldr r3, [r3, #0] 8003256: 4a2f ldr r2, [pc, #188] @ (8003314 ) 8003258: 4293 cmp r3, r2 800325a: d04a beq.n 80032f2 800325c: 687b ldr r3, [r7, #4] 800325e: 681b ldr r3, [r3, #0] 8003260: 4a2d ldr r2, [pc, #180] @ (8003318 ) 8003262: 4293 cmp r3, r2 8003264: d045 beq.n 80032f2 8003266: 687b ldr r3, [r7, #4] 8003268: 681b ldr r3, [r3, #0] 800326a: 4a2c ldr r2, [pc, #176] @ (800331c ) 800326c: 4293 cmp r3, r2 800326e: d040 beq.n 80032f2 8003270: 687b ldr r3, [r7, #4] 8003272: 681b ldr r3, [r3, #0] 8003274: 4a2a ldr r2, [pc, #168] @ (8003320 ) 8003276: 4293 cmp r3, r2 8003278: d03b beq.n 80032f2 800327a: 687b ldr r3, [r7, #4] 800327c: 681b ldr r3, [r3, #0] 800327e: 4a29 ldr r2, [pc, #164] @ (8003324 ) 8003280: 4293 cmp r3, r2 8003282: d036 beq.n 80032f2 8003284: 687b ldr r3, [r7, #4] 8003286: 681b ldr r3, [r3, #0] 8003288: 4a27 ldr r2, [pc, #156] @ (8003328 ) 800328a: 4293 cmp r3, r2 800328c: d031 beq.n 80032f2 800328e: 687b ldr r3, [r7, #4] 8003290: 681b ldr r3, [r3, #0] 8003292: 4a26 ldr r2, [pc, #152] @ (800332c ) 8003294: 4293 cmp r3, r2 8003296: d02c beq.n 80032f2 8003298: 687b ldr r3, [r7, #4] 800329a: 681b ldr r3, [r3, #0] 800329c: 4a24 ldr r2, [pc, #144] @ (8003330 ) 800329e: 4293 cmp r3, r2 80032a0: d027 beq.n 80032f2 80032a2: 687b ldr r3, [r7, #4] 80032a4: 681b ldr r3, [r3, #0] 80032a6: 4a23 ldr r2, [pc, #140] @ (8003334 ) 80032a8: 4293 cmp r3, r2 80032aa: d022 beq.n 80032f2 80032ac: 687b ldr r3, [r7, #4] 80032ae: 681b ldr r3, [r3, #0] 80032b0: 4a21 ldr r2, [pc, #132] @ (8003338 ) 80032b2: 4293 cmp r3, r2 80032b4: d01d beq.n 80032f2 80032b6: 687b ldr r3, [r7, #4] 80032b8: 681b ldr r3, [r3, #0] 80032ba: 4a20 ldr r2, [pc, #128] @ (800333c ) 80032bc: 4293 cmp r3, r2 80032be: d018 beq.n 80032f2 80032c0: 687b ldr r3, [r7, #4] 80032c2: 681b ldr r3, [r3, #0] 80032c4: 4a1e ldr r2, [pc, #120] @ (8003340 ) 80032c6: 4293 cmp r3, r2 80032c8: d013 beq.n 80032f2 80032ca: 687b ldr r3, [r7, #4] 80032cc: 681b ldr r3, [r3, #0] 80032ce: 4a1d ldr r2, [pc, #116] @ (8003344 ) 80032d0: 4293 cmp r3, r2 80032d2: d00e beq.n 80032f2 80032d4: 687b ldr r3, [r7, #4] 80032d6: 681b ldr r3, [r3, #0] 80032d8: 4a1b ldr r2, [pc, #108] @ (8003348 ) 80032da: 4293 cmp r3, r2 80032dc: d009 beq.n 80032f2 80032de: 687b ldr r3, [r7, #4] 80032e0: 681b ldr r3, [r3, #0] 80032e2: 4a1a ldr r2, [pc, #104] @ (800334c ) 80032e4: 4293 cmp r3, r2 80032e6: d004 beq.n 80032f2 80032e8: 687b ldr r3, [r7, #4] 80032ea: 681b ldr r3, [r3, #0] 80032ec: 4a18 ldr r2, [pc, #96] @ (8003350 ) 80032ee: 4293 cmp r3, r2 80032f0: d101 bne.n 80032f6 80032f2: 2301 movs r3, #1 80032f4: e000 b.n 80032f8 80032f6: 2300 movs r3, #0 80032f8: 2b00 cmp r3, #0 80032fa: d02b beq.n 8003354 { regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 80032fc: 687b ldr r3, [r7, #4] 80032fe: 6d9b ldr r3, [r3, #88] @ 0x58 8003300: 60bb str r3, [r7, #8] regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 8003302: 687b ldr r3, [r7, #4] 8003304: 6ddb ldr r3, [r3, #92] @ 0x5c 8003306: f003 031f and.w r3, r3, #31 800330a: 223f movs r2, #63 @ 0x3f 800330c: 409a lsls r2, r3 800330e: 68bb ldr r3, [r7, #8] 8003310: 609a str r2, [r3, #8] 8003312: e02a b.n 800336a 8003314: 40020010 .word 0x40020010 8003318: 40020028 .word 0x40020028 800331c: 40020040 .word 0x40020040 8003320: 40020058 .word 0x40020058 8003324: 40020070 .word 0x40020070 8003328: 40020088 .word 0x40020088 800332c: 400200a0 .word 0x400200a0 8003330: 400200b8 .word 0x400200b8 8003334: 40020410 .word 0x40020410 8003338: 40020428 .word 0x40020428 800333c: 40020440 .word 0x40020440 8003340: 40020458 .word 0x40020458 8003344: 40020470 .word 0x40020470 8003348: 40020488 .word 0x40020488 800334c: 400204a0 .word 0x400204a0 8003350: 400204b8 .word 0x400204b8 } else /* BDMA channel */ { regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 8003354: 687b ldr r3, [r7, #4] 8003356: 6d9b ldr r3, [r3, #88] @ 0x58 8003358: 60fb str r3, [r7, #12] regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 800335a: 687b ldr r3, [r7, #4] 800335c: 6ddb ldr r3, [r3, #92] @ 0x5c 800335e: f003 031f and.w r3, r3, #31 8003362: 2201 movs r2, #1 8003364: 409a lsls r2, r3 8003366: 68fb ldr r3, [r7, #12] 8003368: 605a str r2, [r3, #4] } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 800336a: 687b ldr r3, [r7, #4] 800336c: 681b ldr r3, [r3, #0] 800336e: 4a4f ldr r2, [pc, #316] @ (80034ac ) 8003370: 4293 cmp r3, r2 8003372: d072 beq.n 800345a 8003374: 687b ldr r3, [r7, #4] 8003376: 681b ldr r3, [r3, #0] 8003378: 4a4d ldr r2, [pc, #308] @ (80034b0 ) 800337a: 4293 cmp r3, r2 800337c: d06d beq.n 800345a 800337e: 687b ldr r3, [r7, #4] 8003380: 681b ldr r3, [r3, #0] 8003382: 4a4c ldr r2, [pc, #304] @ (80034b4 ) 8003384: 4293 cmp r3, r2 8003386: d068 beq.n 800345a 8003388: 687b ldr r3, [r7, #4] 800338a: 681b ldr r3, [r3, #0] 800338c: 4a4a ldr r2, [pc, #296] @ (80034b8 ) 800338e: 4293 cmp r3, r2 8003390: d063 beq.n 800345a 8003392: 687b ldr r3, [r7, #4] 8003394: 681b ldr r3, [r3, #0] 8003396: 4a49 ldr r2, [pc, #292] @ (80034bc ) 8003398: 4293 cmp r3, r2 800339a: d05e beq.n 800345a 800339c: 687b ldr r3, [r7, #4] 800339e: 681b ldr r3, [r3, #0] 80033a0: 4a47 ldr r2, [pc, #284] @ (80034c0 ) 80033a2: 4293 cmp r3, r2 80033a4: d059 beq.n 800345a 80033a6: 687b ldr r3, [r7, #4] 80033a8: 681b ldr r3, [r3, #0] 80033aa: 4a46 ldr r2, [pc, #280] @ (80034c4 ) 80033ac: 4293 cmp r3, r2 80033ae: d054 beq.n 800345a 80033b0: 687b ldr r3, [r7, #4] 80033b2: 681b ldr r3, [r3, #0] 80033b4: 4a44 ldr r2, [pc, #272] @ (80034c8 ) 80033b6: 4293 cmp r3, r2 80033b8: d04f beq.n 800345a 80033ba: 687b ldr r3, [r7, #4] 80033bc: 681b ldr r3, [r3, #0] 80033be: 4a43 ldr r2, [pc, #268] @ (80034cc ) 80033c0: 4293 cmp r3, r2 80033c2: d04a beq.n 800345a 80033c4: 687b ldr r3, [r7, #4] 80033c6: 681b ldr r3, [r3, #0] 80033c8: 4a41 ldr r2, [pc, #260] @ (80034d0 ) 80033ca: 4293 cmp r3, r2 80033cc: d045 beq.n 800345a 80033ce: 687b ldr r3, [r7, #4] 80033d0: 681b ldr r3, [r3, #0] 80033d2: 4a40 ldr r2, [pc, #256] @ (80034d4 ) 80033d4: 4293 cmp r3, r2 80033d6: d040 beq.n 800345a 80033d8: 687b ldr r3, [r7, #4] 80033da: 681b ldr r3, [r3, #0] 80033dc: 4a3e ldr r2, [pc, #248] @ (80034d8 ) 80033de: 4293 cmp r3, r2 80033e0: d03b beq.n 800345a 80033e2: 687b ldr r3, [r7, #4] 80033e4: 681b ldr r3, [r3, #0] 80033e6: 4a3d ldr r2, [pc, #244] @ (80034dc ) 80033e8: 4293 cmp r3, r2 80033ea: d036 beq.n 800345a 80033ec: 687b ldr r3, [r7, #4] 80033ee: 681b ldr r3, [r3, #0] 80033f0: 4a3b ldr r2, [pc, #236] @ (80034e0 ) 80033f2: 4293 cmp r3, r2 80033f4: d031 beq.n 800345a 80033f6: 687b ldr r3, [r7, #4] 80033f8: 681b ldr r3, [r3, #0] 80033fa: 4a3a ldr r2, [pc, #232] @ (80034e4 ) 80033fc: 4293 cmp r3, r2 80033fe: d02c beq.n 800345a 8003400: 687b ldr r3, [r7, #4] 8003402: 681b ldr r3, [r3, #0] 8003404: 4a38 ldr r2, [pc, #224] @ (80034e8 ) 8003406: 4293 cmp r3, r2 8003408: d027 beq.n 800345a 800340a: 687b ldr r3, [r7, #4] 800340c: 681b ldr r3, [r3, #0] 800340e: 4a37 ldr r2, [pc, #220] @ (80034ec ) 8003410: 4293 cmp r3, r2 8003412: d022 beq.n 800345a 8003414: 687b ldr r3, [r7, #4] 8003416: 681b ldr r3, [r3, #0] 8003418: 4a35 ldr r2, [pc, #212] @ (80034f0 ) 800341a: 4293 cmp r3, r2 800341c: d01d beq.n 800345a 800341e: 687b ldr r3, [r7, #4] 8003420: 681b ldr r3, [r3, #0] 8003422: 4a34 ldr r2, [pc, #208] @ (80034f4 ) 8003424: 4293 cmp r3, r2 8003426: d018 beq.n 800345a 8003428: 687b ldr r3, [r7, #4] 800342a: 681b ldr r3, [r3, #0] 800342c: 4a32 ldr r2, [pc, #200] @ (80034f8 ) 800342e: 4293 cmp r3, r2 8003430: d013 beq.n 800345a 8003432: 687b ldr r3, [r7, #4] 8003434: 681b ldr r3, [r3, #0] 8003436: 4a31 ldr r2, [pc, #196] @ (80034fc ) 8003438: 4293 cmp r3, r2 800343a: d00e beq.n 800345a 800343c: 687b ldr r3, [r7, #4] 800343e: 681b ldr r3, [r3, #0] 8003440: 4a2f ldr r2, [pc, #188] @ (8003500 ) 8003442: 4293 cmp r3, r2 8003444: d009 beq.n 800345a 8003446: 687b ldr r3, [r7, #4] 8003448: 681b ldr r3, [r3, #0] 800344a: 4a2e ldr r2, [pc, #184] @ (8003504 ) 800344c: 4293 cmp r3, r2 800344e: d004 beq.n 800345a 8003450: 687b ldr r3, [r7, #4] 8003452: 681b ldr r3, [r3, #0] 8003454: 4a2c ldr r2, [pc, #176] @ (8003508 ) 8003456: 4293 cmp r3, r2 8003458: d101 bne.n 800345e 800345a: 2301 movs r3, #1 800345c: e000 b.n 8003460 800345e: 2300 movs r3, #0 8003460: 2b00 cmp r3, #0 8003462: d015 beq.n 8003490 { /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8003464: 687b ldr r3, [r7, #4] 8003466: 6e5b ldr r3, [r3, #100] @ 0x64 8003468: 687a ldr r2, [r7, #4] 800346a: 6e92 ldr r2, [r2, #104] @ 0x68 800346c: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 800346e: 687b ldr r3, [r7, #4] 8003470: 6edb ldr r3, [r3, #108] @ 0x6c 8003472: 2b00 cmp r3, #0 8003474: d00c beq.n 8003490 { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */ /* disable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8003476: 687b ldr r3, [r7, #4] 8003478: 6edb ldr r3, [r3, #108] @ 0x6c 800347a: 681a ldr r2, [r3, #0] 800347c: 687b ldr r3, [r7, #4] 800347e: 6edb ldr r3, [r3, #108] @ 0x6c 8003480: f422 7280 bic.w r2, r2, #256 @ 0x100 8003484: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8003486: 687b ldr r3, [r7, #4] 8003488: 6f1b ldr r3, [r3, #112] @ 0x70 800348a: 687a ldr r2, [r7, #4] 800348c: 6f52 ldr r2, [r2, #116] @ 0x74 800348e: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8003490: 687b ldr r3, [r7, #4] 8003492: 2201 movs r2, #1 8003494: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8003498: 687b ldr r3, [r7, #4] 800349a: 2200 movs r2, #0 800349c: f883 2034 strb.w r2, [r3, #52] @ 0x34 } return HAL_OK; 80034a0: 2300 movs r3, #0 } 80034a2: 4618 mov r0, r3 80034a4: 3718 adds r7, #24 80034a6: 46bd mov sp, r7 80034a8: bd80 pop {r7, pc} 80034aa: bf00 nop 80034ac: 40020010 .word 0x40020010 80034b0: 40020028 .word 0x40020028 80034b4: 40020040 .word 0x40020040 80034b8: 40020058 .word 0x40020058 80034bc: 40020070 .word 0x40020070 80034c0: 40020088 .word 0x40020088 80034c4: 400200a0 .word 0x400200a0 80034c8: 400200b8 .word 0x400200b8 80034cc: 40020410 .word 0x40020410 80034d0: 40020428 .word 0x40020428 80034d4: 40020440 .word 0x40020440 80034d8: 40020458 .word 0x40020458 80034dc: 40020470 .word 0x40020470 80034e0: 40020488 .word 0x40020488 80034e4: 400204a0 .word 0x400204a0 80034e8: 400204b8 .word 0x400204b8 80034ec: 58025408 .word 0x58025408 80034f0: 5802541c .word 0x5802541c 80034f4: 58025430 .word 0x58025430 80034f8: 58025444 .word 0x58025444 80034fc: 58025458 .word 0x58025458 8003500: 5802546c .word 0x5802546c 8003504: 58025480 .word 0x58025480 8003508: 58025494 .word 0x58025494 0800350c : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 800350c: b580 push {r7, lr} 800350e: b084 sub sp, #16 8003510: af00 add r7, sp, #0 8003512: 6078 str r0, [r7, #4] BDMA_Base_Registers *regs_bdma; /* Check the DMA peripheral handle */ if(hdma == NULL) 8003514: 687b ldr r3, [r7, #4] 8003516: 2b00 cmp r3, #0 8003518: d101 bne.n 800351e { return HAL_ERROR; 800351a: 2301 movs r3, #1 800351c: e237 b.n 800398e } if(hdma->State != HAL_DMA_STATE_BUSY) 800351e: 687b ldr r3, [r7, #4] 8003520: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8003524: b2db uxtb r3, r3 8003526: 2b02 cmp r3, #2 8003528: d004 beq.n 8003534 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800352a: 687b ldr r3, [r7, #4] 800352c: 2280 movs r2, #128 @ 0x80 800352e: 655a str r2, [r3, #84] @ 0x54 return HAL_ERROR; 8003530: 2301 movs r3, #1 8003532: e22c b.n 800398e } else { if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8003534: 687b ldr r3, [r7, #4] 8003536: 681b ldr r3, [r3, #0] 8003538: 4a5c ldr r2, [pc, #368] @ (80036ac ) 800353a: 4293 cmp r3, r2 800353c: d04a beq.n 80035d4 800353e: 687b ldr r3, [r7, #4] 8003540: 681b ldr r3, [r3, #0] 8003542: 4a5b ldr r2, [pc, #364] @ (80036b0 ) 8003544: 4293 cmp r3, r2 8003546: d045 beq.n 80035d4 8003548: 687b ldr r3, [r7, #4] 800354a: 681b ldr r3, [r3, #0] 800354c: 4a59 ldr r2, [pc, #356] @ (80036b4 ) 800354e: 4293 cmp r3, r2 8003550: d040 beq.n 80035d4 8003552: 687b ldr r3, [r7, #4] 8003554: 681b ldr r3, [r3, #0] 8003556: 4a58 ldr r2, [pc, #352] @ (80036b8 ) 8003558: 4293 cmp r3, r2 800355a: d03b beq.n 80035d4 800355c: 687b ldr r3, [r7, #4] 800355e: 681b ldr r3, [r3, #0] 8003560: 4a56 ldr r2, [pc, #344] @ (80036bc ) 8003562: 4293 cmp r3, r2 8003564: d036 beq.n 80035d4 8003566: 687b ldr r3, [r7, #4] 8003568: 681b ldr r3, [r3, #0] 800356a: 4a55 ldr r2, [pc, #340] @ (80036c0 ) 800356c: 4293 cmp r3, r2 800356e: d031 beq.n 80035d4 8003570: 687b ldr r3, [r7, #4] 8003572: 681b ldr r3, [r3, #0] 8003574: 4a53 ldr r2, [pc, #332] @ (80036c4 ) 8003576: 4293 cmp r3, r2 8003578: d02c beq.n 80035d4 800357a: 687b ldr r3, [r7, #4] 800357c: 681b ldr r3, [r3, #0] 800357e: 4a52 ldr r2, [pc, #328] @ (80036c8 ) 8003580: 4293 cmp r3, r2 8003582: d027 beq.n 80035d4 8003584: 687b ldr r3, [r7, #4] 8003586: 681b ldr r3, [r3, #0] 8003588: 4a50 ldr r2, [pc, #320] @ (80036cc ) 800358a: 4293 cmp r3, r2 800358c: d022 beq.n 80035d4 800358e: 687b ldr r3, [r7, #4] 8003590: 681b ldr r3, [r3, #0] 8003592: 4a4f ldr r2, [pc, #316] @ (80036d0 ) 8003594: 4293 cmp r3, r2 8003596: d01d beq.n 80035d4 8003598: 687b ldr r3, [r7, #4] 800359a: 681b ldr r3, [r3, #0] 800359c: 4a4d ldr r2, [pc, #308] @ (80036d4 ) 800359e: 4293 cmp r3, r2 80035a0: d018 beq.n 80035d4 80035a2: 687b ldr r3, [r7, #4] 80035a4: 681b ldr r3, [r3, #0] 80035a6: 4a4c ldr r2, [pc, #304] @ (80036d8 ) 80035a8: 4293 cmp r3, r2 80035aa: d013 beq.n 80035d4 80035ac: 687b ldr r3, [r7, #4] 80035ae: 681b ldr r3, [r3, #0] 80035b0: 4a4a ldr r2, [pc, #296] @ (80036dc ) 80035b2: 4293 cmp r3, r2 80035b4: d00e beq.n 80035d4 80035b6: 687b ldr r3, [r7, #4] 80035b8: 681b ldr r3, [r3, #0] 80035ba: 4a49 ldr r2, [pc, #292] @ (80036e0 ) 80035bc: 4293 cmp r3, r2 80035be: d009 beq.n 80035d4 80035c0: 687b ldr r3, [r7, #4] 80035c2: 681b ldr r3, [r3, #0] 80035c4: 4a47 ldr r2, [pc, #284] @ (80036e4 ) 80035c6: 4293 cmp r3, r2 80035c8: d004 beq.n 80035d4 80035ca: 687b ldr r3, [r7, #4] 80035cc: 681b ldr r3, [r3, #0] 80035ce: 4a46 ldr r2, [pc, #280] @ (80036e8 ) 80035d0: 4293 cmp r3, r2 80035d2: d101 bne.n 80035d8 80035d4: 2301 movs r3, #1 80035d6: e000 b.n 80035da 80035d8: 2300 movs r3, #0 80035da: 2b00 cmp r3, #0 80035dc: f000 8086 beq.w 80036ec { /* Set Abort State */ hdma->State = HAL_DMA_STATE_ABORT; 80035e0: 687b ldr r3, [r7, #4] 80035e2: 2204 movs r2, #4 80035e4: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 80035e8: 687b ldr r3, [r7, #4] 80035ea: 681b ldr r3, [r3, #0] 80035ec: 4a2f ldr r2, [pc, #188] @ (80036ac ) 80035ee: 4293 cmp r3, r2 80035f0: d04a beq.n 8003688 80035f2: 687b ldr r3, [r7, #4] 80035f4: 681b ldr r3, [r3, #0] 80035f6: 4a2e ldr r2, [pc, #184] @ (80036b0 ) 80035f8: 4293 cmp r3, r2 80035fa: d045 beq.n 8003688 80035fc: 687b ldr r3, [r7, #4] 80035fe: 681b ldr r3, [r3, #0] 8003600: 4a2c ldr r2, [pc, #176] @ (80036b4 ) 8003602: 4293 cmp r3, r2 8003604: d040 beq.n 8003688 8003606: 687b ldr r3, [r7, #4] 8003608: 681b ldr r3, [r3, #0] 800360a: 4a2b ldr r2, [pc, #172] @ (80036b8 ) 800360c: 4293 cmp r3, r2 800360e: d03b beq.n 8003688 8003610: 687b ldr r3, [r7, #4] 8003612: 681b ldr r3, [r3, #0] 8003614: 4a29 ldr r2, [pc, #164] @ (80036bc ) 8003616: 4293 cmp r3, r2 8003618: d036 beq.n 8003688 800361a: 687b ldr r3, [r7, #4] 800361c: 681b ldr r3, [r3, #0] 800361e: 4a28 ldr r2, [pc, #160] @ (80036c0 ) 8003620: 4293 cmp r3, r2 8003622: d031 beq.n 8003688 8003624: 687b ldr r3, [r7, #4] 8003626: 681b ldr r3, [r3, #0] 8003628: 4a26 ldr r2, [pc, #152] @ (80036c4 ) 800362a: 4293 cmp r3, r2 800362c: d02c beq.n 8003688 800362e: 687b ldr r3, [r7, #4] 8003630: 681b ldr r3, [r3, #0] 8003632: 4a25 ldr r2, [pc, #148] @ (80036c8 ) 8003634: 4293 cmp r3, r2 8003636: d027 beq.n 8003688 8003638: 687b ldr r3, [r7, #4] 800363a: 681b ldr r3, [r3, #0] 800363c: 4a23 ldr r2, [pc, #140] @ (80036cc ) 800363e: 4293 cmp r3, r2 8003640: d022 beq.n 8003688 8003642: 687b ldr r3, [r7, #4] 8003644: 681b ldr r3, [r3, #0] 8003646: 4a22 ldr r2, [pc, #136] @ (80036d0 ) 8003648: 4293 cmp r3, r2 800364a: d01d beq.n 8003688 800364c: 687b ldr r3, [r7, #4] 800364e: 681b ldr r3, [r3, #0] 8003650: 4a20 ldr r2, [pc, #128] @ (80036d4 ) 8003652: 4293 cmp r3, r2 8003654: d018 beq.n 8003688 8003656: 687b ldr r3, [r7, #4] 8003658: 681b ldr r3, [r3, #0] 800365a: 4a1f ldr r2, [pc, #124] @ (80036d8 ) 800365c: 4293 cmp r3, r2 800365e: d013 beq.n 8003688 8003660: 687b ldr r3, [r7, #4] 8003662: 681b ldr r3, [r3, #0] 8003664: 4a1d ldr r2, [pc, #116] @ (80036dc ) 8003666: 4293 cmp r3, r2 8003668: d00e beq.n 8003688 800366a: 687b ldr r3, [r7, #4] 800366c: 681b ldr r3, [r3, #0] 800366e: 4a1c ldr r2, [pc, #112] @ (80036e0 ) 8003670: 4293 cmp r3, r2 8003672: d009 beq.n 8003688 8003674: 687b ldr r3, [r7, #4] 8003676: 681b ldr r3, [r3, #0] 8003678: 4a1a ldr r2, [pc, #104] @ (80036e4 ) 800367a: 4293 cmp r3, r2 800367c: d004 beq.n 8003688 800367e: 687b ldr r3, [r7, #4] 8003680: 681b ldr r3, [r3, #0] 8003682: 4a19 ldr r2, [pc, #100] @ (80036e8 ) 8003684: 4293 cmp r3, r2 8003686: d108 bne.n 800369a 8003688: 687b ldr r3, [r7, #4] 800368a: 681b ldr r3, [r3, #0] 800368c: 681a ldr r2, [r3, #0] 800368e: 687b ldr r3, [r7, #4] 8003690: 681b ldr r3, [r3, #0] 8003692: f022 0201 bic.w r2, r2, #1 8003696: 601a str r2, [r3, #0] 8003698: e178 b.n 800398c 800369a: 687b ldr r3, [r7, #4] 800369c: 681b ldr r3, [r3, #0] 800369e: 681a ldr r2, [r3, #0] 80036a0: 687b ldr r3, [r7, #4] 80036a2: 681b ldr r3, [r3, #0] 80036a4: f022 0201 bic.w r2, r2, #1 80036a8: 601a str r2, [r3, #0] 80036aa: e16f b.n 800398c 80036ac: 40020010 .word 0x40020010 80036b0: 40020028 .word 0x40020028 80036b4: 40020040 .word 0x40020040 80036b8: 40020058 .word 0x40020058 80036bc: 40020070 .word 0x40020070 80036c0: 40020088 .word 0x40020088 80036c4: 400200a0 .word 0x400200a0 80036c8: 400200b8 .word 0x400200b8 80036cc: 40020410 .word 0x40020410 80036d0: 40020428 .word 0x40020428 80036d4: 40020440 .word 0x40020440 80036d8: 40020458 .word 0x40020458 80036dc: 40020470 .word 0x40020470 80036e0: 40020488 .word 0x40020488 80036e4: 400204a0 .word 0x400204a0 80036e8: 400204b8 .word 0x400204b8 } else /* BDMA channel */ { /* Disable DMA All Interrupts */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 80036ec: 687b ldr r3, [r7, #4] 80036ee: 681b ldr r3, [r3, #0] 80036f0: 681a ldr r2, [r3, #0] 80036f2: 687b ldr r3, [r7, #4] 80036f4: 681b ldr r3, [r3, #0] 80036f6: f022 020e bic.w r2, r2, #14 80036fa: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 80036fc: 687b ldr r3, [r7, #4] 80036fe: 681b ldr r3, [r3, #0] 8003700: 4a6c ldr r2, [pc, #432] @ (80038b4 ) 8003702: 4293 cmp r3, r2 8003704: d04a beq.n 800379c 8003706: 687b ldr r3, [r7, #4] 8003708: 681b ldr r3, [r3, #0] 800370a: 4a6b ldr r2, [pc, #428] @ (80038b8 ) 800370c: 4293 cmp r3, r2 800370e: d045 beq.n 800379c 8003710: 687b ldr r3, [r7, #4] 8003712: 681b ldr r3, [r3, #0] 8003714: 4a69 ldr r2, [pc, #420] @ (80038bc ) 8003716: 4293 cmp r3, r2 8003718: d040 beq.n 800379c 800371a: 687b ldr r3, [r7, #4] 800371c: 681b ldr r3, [r3, #0] 800371e: 4a68 ldr r2, [pc, #416] @ (80038c0 ) 8003720: 4293 cmp r3, r2 8003722: d03b beq.n 800379c 8003724: 687b ldr r3, [r7, #4] 8003726: 681b ldr r3, [r3, #0] 8003728: 4a66 ldr r2, [pc, #408] @ (80038c4 ) 800372a: 4293 cmp r3, r2 800372c: d036 beq.n 800379c 800372e: 687b ldr r3, [r7, #4] 8003730: 681b ldr r3, [r3, #0] 8003732: 4a65 ldr r2, [pc, #404] @ (80038c8 ) 8003734: 4293 cmp r3, r2 8003736: d031 beq.n 800379c 8003738: 687b ldr r3, [r7, #4] 800373a: 681b ldr r3, [r3, #0] 800373c: 4a63 ldr r2, [pc, #396] @ (80038cc ) 800373e: 4293 cmp r3, r2 8003740: d02c beq.n 800379c 8003742: 687b ldr r3, [r7, #4] 8003744: 681b ldr r3, [r3, #0] 8003746: 4a62 ldr r2, [pc, #392] @ (80038d0 ) 8003748: 4293 cmp r3, r2 800374a: d027 beq.n 800379c 800374c: 687b ldr r3, [r7, #4] 800374e: 681b ldr r3, [r3, #0] 8003750: 4a60 ldr r2, [pc, #384] @ (80038d4 ) 8003752: 4293 cmp r3, r2 8003754: d022 beq.n 800379c 8003756: 687b ldr r3, [r7, #4] 8003758: 681b ldr r3, [r3, #0] 800375a: 4a5f ldr r2, [pc, #380] @ (80038d8 ) 800375c: 4293 cmp r3, r2 800375e: d01d beq.n 800379c 8003760: 687b ldr r3, [r7, #4] 8003762: 681b ldr r3, [r3, #0] 8003764: 4a5d ldr r2, [pc, #372] @ (80038dc ) 8003766: 4293 cmp r3, r2 8003768: d018 beq.n 800379c 800376a: 687b ldr r3, [r7, #4] 800376c: 681b ldr r3, [r3, #0] 800376e: 4a5c ldr r2, [pc, #368] @ (80038e0 ) 8003770: 4293 cmp r3, r2 8003772: d013 beq.n 800379c 8003774: 687b ldr r3, [r7, #4] 8003776: 681b ldr r3, [r3, #0] 8003778: 4a5a ldr r2, [pc, #360] @ (80038e4 ) 800377a: 4293 cmp r3, r2 800377c: d00e beq.n 800379c 800377e: 687b ldr r3, [r7, #4] 8003780: 681b ldr r3, [r3, #0] 8003782: 4a59 ldr r2, [pc, #356] @ (80038e8 ) 8003784: 4293 cmp r3, r2 8003786: d009 beq.n 800379c 8003788: 687b ldr r3, [r7, #4] 800378a: 681b ldr r3, [r3, #0] 800378c: 4a57 ldr r2, [pc, #348] @ (80038ec ) 800378e: 4293 cmp r3, r2 8003790: d004 beq.n 800379c 8003792: 687b ldr r3, [r7, #4] 8003794: 681b ldr r3, [r3, #0] 8003796: 4a56 ldr r2, [pc, #344] @ (80038f0 ) 8003798: 4293 cmp r3, r2 800379a: d108 bne.n 80037ae 800379c: 687b ldr r3, [r7, #4] 800379e: 681b ldr r3, [r3, #0] 80037a0: 681a ldr r2, [r3, #0] 80037a2: 687b ldr r3, [r7, #4] 80037a4: 681b ldr r3, [r3, #0] 80037a6: f022 0201 bic.w r2, r2, #1 80037aa: 601a str r2, [r3, #0] 80037ac: e007 b.n 80037be 80037ae: 687b ldr r3, [r7, #4] 80037b0: 681b ldr r3, [r3, #0] 80037b2: 681a ldr r2, [r3, #0] 80037b4: 687b ldr r3, [r7, #4] 80037b6: 681b ldr r3, [r3, #0] 80037b8: f022 0201 bic.w r2, r2, #1 80037bc: 601a str r2, [r3, #0] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80037be: 687b ldr r3, [r7, #4] 80037c0: 681b ldr r3, [r3, #0] 80037c2: 4a3c ldr r2, [pc, #240] @ (80038b4 ) 80037c4: 4293 cmp r3, r2 80037c6: d072 beq.n 80038ae 80037c8: 687b ldr r3, [r7, #4] 80037ca: 681b ldr r3, [r3, #0] 80037cc: 4a3a ldr r2, [pc, #232] @ (80038b8 ) 80037ce: 4293 cmp r3, r2 80037d0: d06d beq.n 80038ae 80037d2: 687b ldr r3, [r7, #4] 80037d4: 681b ldr r3, [r3, #0] 80037d6: 4a39 ldr r2, [pc, #228] @ (80038bc ) 80037d8: 4293 cmp r3, r2 80037da: d068 beq.n 80038ae 80037dc: 687b ldr r3, [r7, #4] 80037de: 681b ldr r3, [r3, #0] 80037e0: 4a37 ldr r2, [pc, #220] @ (80038c0 ) 80037e2: 4293 cmp r3, r2 80037e4: d063 beq.n 80038ae 80037e6: 687b ldr r3, [r7, #4] 80037e8: 681b ldr r3, [r3, #0] 80037ea: 4a36 ldr r2, [pc, #216] @ (80038c4 ) 80037ec: 4293 cmp r3, r2 80037ee: d05e beq.n 80038ae 80037f0: 687b ldr r3, [r7, #4] 80037f2: 681b ldr r3, [r3, #0] 80037f4: 4a34 ldr r2, [pc, #208] @ (80038c8 ) 80037f6: 4293 cmp r3, r2 80037f8: d059 beq.n 80038ae 80037fa: 687b ldr r3, [r7, #4] 80037fc: 681b ldr r3, [r3, #0] 80037fe: 4a33 ldr r2, [pc, #204] @ (80038cc ) 8003800: 4293 cmp r3, r2 8003802: d054 beq.n 80038ae 8003804: 687b ldr r3, [r7, #4] 8003806: 681b ldr r3, [r3, #0] 8003808: 4a31 ldr r2, [pc, #196] @ (80038d0 ) 800380a: 4293 cmp r3, r2 800380c: d04f beq.n 80038ae 800380e: 687b ldr r3, [r7, #4] 8003810: 681b ldr r3, [r3, #0] 8003812: 4a30 ldr r2, [pc, #192] @ (80038d4 ) 8003814: 4293 cmp r3, r2 8003816: d04a beq.n 80038ae 8003818: 687b ldr r3, [r7, #4] 800381a: 681b ldr r3, [r3, #0] 800381c: 4a2e ldr r2, [pc, #184] @ (80038d8 ) 800381e: 4293 cmp r3, r2 8003820: d045 beq.n 80038ae 8003822: 687b ldr r3, [r7, #4] 8003824: 681b ldr r3, [r3, #0] 8003826: 4a2d ldr r2, [pc, #180] @ (80038dc ) 8003828: 4293 cmp r3, r2 800382a: d040 beq.n 80038ae 800382c: 687b ldr r3, [r7, #4] 800382e: 681b ldr r3, [r3, #0] 8003830: 4a2b ldr r2, [pc, #172] @ (80038e0 ) 8003832: 4293 cmp r3, r2 8003834: d03b beq.n 80038ae 8003836: 687b ldr r3, [r7, #4] 8003838: 681b ldr r3, [r3, #0] 800383a: 4a2a ldr r2, [pc, #168] @ (80038e4 ) 800383c: 4293 cmp r3, r2 800383e: d036 beq.n 80038ae 8003840: 687b ldr r3, [r7, #4] 8003842: 681b ldr r3, [r3, #0] 8003844: 4a28 ldr r2, [pc, #160] @ (80038e8 ) 8003846: 4293 cmp r3, r2 8003848: d031 beq.n 80038ae 800384a: 687b ldr r3, [r7, #4] 800384c: 681b ldr r3, [r3, #0] 800384e: 4a27 ldr r2, [pc, #156] @ (80038ec ) 8003850: 4293 cmp r3, r2 8003852: d02c beq.n 80038ae 8003854: 687b ldr r3, [r7, #4] 8003856: 681b ldr r3, [r3, #0] 8003858: 4a25 ldr r2, [pc, #148] @ (80038f0 ) 800385a: 4293 cmp r3, r2 800385c: d027 beq.n 80038ae 800385e: 687b ldr r3, [r7, #4] 8003860: 681b ldr r3, [r3, #0] 8003862: 4a24 ldr r2, [pc, #144] @ (80038f4 ) 8003864: 4293 cmp r3, r2 8003866: d022 beq.n 80038ae 8003868: 687b ldr r3, [r7, #4] 800386a: 681b ldr r3, [r3, #0] 800386c: 4a22 ldr r2, [pc, #136] @ (80038f8 ) 800386e: 4293 cmp r3, r2 8003870: d01d beq.n 80038ae 8003872: 687b ldr r3, [r7, #4] 8003874: 681b ldr r3, [r3, #0] 8003876: 4a21 ldr r2, [pc, #132] @ (80038fc ) 8003878: 4293 cmp r3, r2 800387a: d018 beq.n 80038ae 800387c: 687b ldr r3, [r7, #4] 800387e: 681b ldr r3, [r3, #0] 8003880: 4a1f ldr r2, [pc, #124] @ (8003900 ) 8003882: 4293 cmp r3, r2 8003884: d013 beq.n 80038ae 8003886: 687b ldr r3, [r7, #4] 8003888: 681b ldr r3, [r3, #0] 800388a: 4a1e ldr r2, [pc, #120] @ (8003904 ) 800388c: 4293 cmp r3, r2 800388e: d00e beq.n 80038ae 8003890: 687b ldr r3, [r7, #4] 8003892: 681b ldr r3, [r3, #0] 8003894: 4a1c ldr r2, [pc, #112] @ (8003908 ) 8003896: 4293 cmp r3, r2 8003898: d009 beq.n 80038ae 800389a: 687b ldr r3, [r7, #4] 800389c: 681b ldr r3, [r3, #0] 800389e: 4a1b ldr r2, [pc, #108] @ (800390c ) 80038a0: 4293 cmp r3, r2 80038a2: d004 beq.n 80038ae 80038a4: 687b ldr r3, [r7, #4] 80038a6: 681b ldr r3, [r3, #0] 80038a8: 4a19 ldr r2, [pc, #100] @ (8003910 ) 80038aa: 4293 cmp r3, r2 80038ac: d132 bne.n 8003914 80038ae: 2301 movs r3, #1 80038b0: e031 b.n 8003916 80038b2: bf00 nop 80038b4: 40020010 .word 0x40020010 80038b8: 40020028 .word 0x40020028 80038bc: 40020040 .word 0x40020040 80038c0: 40020058 .word 0x40020058 80038c4: 40020070 .word 0x40020070 80038c8: 40020088 .word 0x40020088 80038cc: 400200a0 .word 0x400200a0 80038d0: 400200b8 .word 0x400200b8 80038d4: 40020410 .word 0x40020410 80038d8: 40020428 .word 0x40020428 80038dc: 40020440 .word 0x40020440 80038e0: 40020458 .word 0x40020458 80038e4: 40020470 .word 0x40020470 80038e8: 40020488 .word 0x40020488 80038ec: 400204a0 .word 0x400204a0 80038f0: 400204b8 .word 0x400204b8 80038f4: 58025408 .word 0x58025408 80038f8: 5802541c .word 0x5802541c 80038fc: 58025430 .word 0x58025430 8003900: 58025444 .word 0x58025444 8003904: 58025458 .word 0x58025458 8003908: 5802546c .word 0x5802546c 800390c: 58025480 .word 0x58025480 8003910: 58025494 .word 0x58025494 8003914: 2300 movs r3, #0 8003916: 2b00 cmp r3, #0 8003918: d028 beq.n 800396c { /* disable the DMAMUX sync overrun IT */ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 800391a: 687b ldr r3, [r7, #4] 800391c: 6e1b ldr r3, [r3, #96] @ 0x60 800391e: 681a ldr r2, [r3, #0] 8003920: 687b ldr r3, [r7, #4] 8003922: 6e1b ldr r3, [r3, #96] @ 0x60 8003924: f422 7280 bic.w r2, r2, #256 @ 0x100 8003928: 601a str r2, [r3, #0] /* Clear all flags */ regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 800392a: 687b ldr r3, [r7, #4] 800392c: 6d9b ldr r3, [r3, #88] @ 0x58 800392e: 60fb str r3, [r7, #12] regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 8003930: 687b ldr r3, [r7, #4] 8003932: 6ddb ldr r3, [r3, #92] @ 0x5c 8003934: f003 031f and.w r3, r3, #31 8003938: 2201 movs r2, #1 800393a: 409a lsls r2, r3 800393c: 68fb ldr r3, [r7, #12] 800393e: 605a str r2, [r3, #4] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8003940: 687b ldr r3, [r7, #4] 8003942: 6e5b ldr r3, [r3, #100] @ 0x64 8003944: 687a ldr r2, [r7, #4] 8003946: 6e92 ldr r2, [r2, #104] @ 0x68 8003948: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 800394a: 687b ldr r3, [r7, #4] 800394c: 6edb ldr r3, [r3, #108] @ 0x6c 800394e: 2b00 cmp r3, #0 8003950: d00c beq.n 800396c { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8003952: 687b ldr r3, [r7, #4] 8003954: 6edb ldr r3, [r3, #108] @ 0x6c 8003956: 681a ldr r2, [r3, #0] 8003958: 687b ldr r3, [r7, #4] 800395a: 6edb ldr r3, [r3, #108] @ 0x6c 800395c: f422 7280 bic.w r2, r2, #256 @ 0x100 8003960: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8003962: 687b ldr r3, [r7, #4] 8003964: 6f1b ldr r3, [r3, #112] @ 0x70 8003966: 687a ldr r2, [r7, #4] 8003968: 6f52 ldr r2, [r2, #116] @ 0x74 800396a: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800396c: 687b ldr r3, [r7, #4] 800396e: 2201 movs r2, #1 8003970: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8003974: 687b ldr r3, [r7, #4] 8003976: 2200 movs r2, #0 8003978: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 800397c: 687b ldr r3, [r7, #4] 800397e: 6d1b ldr r3, [r3, #80] @ 0x50 8003980: 2b00 cmp r3, #0 8003982: d003 beq.n 800398c { hdma->XferAbortCallback(hdma); 8003984: 687b ldr r3, [r7, #4] 8003986: 6d1b ldr r3, [r3, #80] @ 0x50 8003988: 6878 ldr r0, [r7, #4] 800398a: 4798 blx r3 } } } return HAL_OK; 800398c: 2300 movs r3, #0 } 800398e: 4618 mov r0, r3 8003990: 3710 adds r7, #16 8003992: 46bd mov sp, r7 8003994: bd80 pop {r7, pc} 8003996: bf00 nop 08003998 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8003998: b580 push {r7, lr} 800399a: b08a sub sp, #40 @ 0x28 800399c: af00 add r7, sp, #0 800399e: 6078 str r0, [r7, #4] uint32_t tmpisr_dma, tmpisr_bdma; uint32_t ccr_reg; __IO uint32_t count = 0U; 80039a0: 2300 movs r3, #0 80039a2: 60fb str r3, [r7, #12] uint32_t timeout = SystemCoreClock / 9600U; 80039a4: 4b67 ldr r3, [pc, #412] @ (8003b44 ) 80039a6: 681b ldr r3, [r3, #0] 80039a8: 4a67 ldr r2, [pc, #412] @ (8003b48 ) 80039aa: fba2 2303 umull r2, r3, r2, r3 80039ae: 0a9b lsrs r3, r3, #10 80039b0: 627b str r3, [r7, #36] @ 0x24 /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 80039b2: 687b ldr r3, [r7, #4] 80039b4: 6d9b ldr r3, [r3, #88] @ 0x58 80039b6: 623b str r3, [r7, #32] BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 80039b8: 687b ldr r3, [r7, #4] 80039ba: 6d9b ldr r3, [r3, #88] @ 0x58 80039bc: 61fb str r3, [r7, #28] tmpisr_dma = regs_dma->ISR; 80039be: 6a3b ldr r3, [r7, #32] 80039c0: 681b ldr r3, [r3, #0] 80039c2: 61bb str r3, [r7, #24] tmpisr_bdma = regs_bdma->ISR; 80039c4: 69fb ldr r3, [r7, #28] 80039c6: 681b ldr r3, [r3, #0] 80039c8: 617b str r3, [r7, #20] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80039ca: 687b ldr r3, [r7, #4] 80039cc: 681b ldr r3, [r3, #0] 80039ce: 4a5f ldr r2, [pc, #380] @ (8003b4c ) 80039d0: 4293 cmp r3, r2 80039d2: d04a beq.n 8003a6a 80039d4: 687b ldr r3, [r7, #4] 80039d6: 681b ldr r3, [r3, #0] 80039d8: 4a5d ldr r2, [pc, #372] @ (8003b50 ) 80039da: 4293 cmp r3, r2 80039dc: d045 beq.n 8003a6a 80039de: 687b ldr r3, [r7, #4] 80039e0: 681b ldr r3, [r3, #0] 80039e2: 4a5c ldr r2, [pc, #368] @ (8003b54 ) 80039e4: 4293 cmp r3, r2 80039e6: d040 beq.n 8003a6a 80039e8: 687b ldr r3, [r7, #4] 80039ea: 681b ldr r3, [r3, #0] 80039ec: 4a5a ldr r2, [pc, #360] @ (8003b58 ) 80039ee: 4293 cmp r3, r2 80039f0: d03b beq.n 8003a6a 80039f2: 687b ldr r3, [r7, #4] 80039f4: 681b ldr r3, [r3, #0] 80039f6: 4a59 ldr r2, [pc, #356] @ (8003b5c ) 80039f8: 4293 cmp r3, r2 80039fa: d036 beq.n 8003a6a 80039fc: 687b ldr r3, [r7, #4] 80039fe: 681b ldr r3, [r3, #0] 8003a00: 4a57 ldr r2, [pc, #348] @ (8003b60 ) 8003a02: 4293 cmp r3, r2 8003a04: d031 beq.n 8003a6a 8003a06: 687b ldr r3, [r7, #4] 8003a08: 681b ldr r3, [r3, #0] 8003a0a: 4a56 ldr r2, [pc, #344] @ (8003b64 ) 8003a0c: 4293 cmp r3, r2 8003a0e: d02c beq.n 8003a6a 8003a10: 687b ldr r3, [r7, #4] 8003a12: 681b ldr r3, [r3, #0] 8003a14: 4a54 ldr r2, [pc, #336] @ (8003b68 ) 8003a16: 4293 cmp r3, r2 8003a18: d027 beq.n 8003a6a 8003a1a: 687b ldr r3, [r7, #4] 8003a1c: 681b ldr r3, [r3, #0] 8003a1e: 4a53 ldr r2, [pc, #332] @ (8003b6c ) 8003a20: 4293 cmp r3, r2 8003a22: d022 beq.n 8003a6a 8003a24: 687b ldr r3, [r7, #4] 8003a26: 681b ldr r3, [r3, #0] 8003a28: 4a51 ldr r2, [pc, #324] @ (8003b70 ) 8003a2a: 4293 cmp r3, r2 8003a2c: d01d beq.n 8003a6a 8003a2e: 687b ldr r3, [r7, #4] 8003a30: 681b ldr r3, [r3, #0] 8003a32: 4a50 ldr r2, [pc, #320] @ (8003b74 ) 8003a34: 4293 cmp r3, r2 8003a36: d018 beq.n 8003a6a 8003a38: 687b ldr r3, [r7, #4] 8003a3a: 681b ldr r3, [r3, #0] 8003a3c: 4a4e ldr r2, [pc, #312] @ (8003b78 ) 8003a3e: 4293 cmp r3, r2 8003a40: d013 beq.n 8003a6a 8003a42: 687b ldr r3, [r7, #4] 8003a44: 681b ldr r3, [r3, #0] 8003a46: 4a4d ldr r2, [pc, #308] @ (8003b7c ) 8003a48: 4293 cmp r3, r2 8003a4a: d00e beq.n 8003a6a 8003a4c: 687b ldr r3, [r7, #4] 8003a4e: 681b ldr r3, [r3, #0] 8003a50: 4a4b ldr r2, [pc, #300] @ (8003b80 ) 8003a52: 4293 cmp r3, r2 8003a54: d009 beq.n 8003a6a 8003a56: 687b ldr r3, [r7, #4] 8003a58: 681b ldr r3, [r3, #0] 8003a5a: 4a4a ldr r2, [pc, #296] @ (8003b84 ) 8003a5c: 4293 cmp r3, r2 8003a5e: d004 beq.n 8003a6a 8003a60: 687b ldr r3, [r7, #4] 8003a62: 681b ldr r3, [r3, #0] 8003a64: 4a48 ldr r2, [pc, #288] @ (8003b88 ) 8003a66: 4293 cmp r3, r2 8003a68: d101 bne.n 8003a6e 8003a6a: 2301 movs r3, #1 8003a6c: e000 b.n 8003a70 8003a6e: 2300 movs r3, #0 8003a70: 2b00 cmp r3, #0 8003a72: f000 842b beq.w 80042cc { /* Transfer Error Interrupt management ***************************************/ if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8003a76: 687b ldr r3, [r7, #4] 8003a78: 6ddb ldr r3, [r3, #92] @ 0x5c 8003a7a: f003 031f and.w r3, r3, #31 8003a7e: 2208 movs r2, #8 8003a80: 409a lsls r2, r3 8003a82: 69bb ldr r3, [r7, #24] 8003a84: 4013 ands r3, r2 8003a86: 2b00 cmp r3, #0 8003a88: f000 80a2 beq.w 8003bd0 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U) 8003a8c: 687b ldr r3, [r7, #4] 8003a8e: 681b ldr r3, [r3, #0] 8003a90: 4a2e ldr r2, [pc, #184] @ (8003b4c ) 8003a92: 4293 cmp r3, r2 8003a94: d04a beq.n 8003b2c 8003a96: 687b ldr r3, [r7, #4] 8003a98: 681b ldr r3, [r3, #0] 8003a9a: 4a2d ldr r2, [pc, #180] @ (8003b50 ) 8003a9c: 4293 cmp r3, r2 8003a9e: d045 beq.n 8003b2c 8003aa0: 687b ldr r3, [r7, #4] 8003aa2: 681b ldr r3, [r3, #0] 8003aa4: 4a2b ldr r2, [pc, #172] @ (8003b54 ) 8003aa6: 4293 cmp r3, r2 8003aa8: d040 beq.n 8003b2c 8003aaa: 687b ldr r3, [r7, #4] 8003aac: 681b ldr r3, [r3, #0] 8003aae: 4a2a ldr r2, [pc, #168] @ (8003b58 ) 8003ab0: 4293 cmp r3, r2 8003ab2: d03b beq.n 8003b2c 8003ab4: 687b ldr r3, [r7, #4] 8003ab6: 681b ldr r3, [r3, #0] 8003ab8: 4a28 ldr r2, [pc, #160] @ (8003b5c ) 8003aba: 4293 cmp r3, r2 8003abc: d036 beq.n 8003b2c 8003abe: 687b ldr r3, [r7, #4] 8003ac0: 681b ldr r3, [r3, #0] 8003ac2: 4a27 ldr r2, [pc, #156] @ (8003b60 ) 8003ac4: 4293 cmp r3, r2 8003ac6: d031 beq.n 8003b2c 8003ac8: 687b ldr r3, [r7, #4] 8003aca: 681b ldr r3, [r3, #0] 8003acc: 4a25 ldr r2, [pc, #148] @ (8003b64 ) 8003ace: 4293 cmp r3, r2 8003ad0: d02c beq.n 8003b2c 8003ad2: 687b ldr r3, [r7, #4] 8003ad4: 681b ldr r3, [r3, #0] 8003ad6: 4a24 ldr r2, [pc, #144] @ (8003b68 ) 8003ad8: 4293 cmp r3, r2 8003ada: d027 beq.n 8003b2c 8003adc: 687b ldr r3, [r7, #4] 8003ade: 681b ldr r3, [r3, #0] 8003ae0: 4a22 ldr r2, [pc, #136] @ (8003b6c ) 8003ae2: 4293 cmp r3, r2 8003ae4: d022 beq.n 8003b2c 8003ae6: 687b ldr r3, [r7, #4] 8003ae8: 681b ldr r3, [r3, #0] 8003aea: 4a21 ldr r2, [pc, #132] @ (8003b70 ) 8003aec: 4293 cmp r3, r2 8003aee: d01d beq.n 8003b2c 8003af0: 687b ldr r3, [r7, #4] 8003af2: 681b ldr r3, [r3, #0] 8003af4: 4a1f ldr r2, [pc, #124] @ (8003b74 ) 8003af6: 4293 cmp r3, r2 8003af8: d018 beq.n 8003b2c 8003afa: 687b ldr r3, [r7, #4] 8003afc: 681b ldr r3, [r3, #0] 8003afe: 4a1e ldr r2, [pc, #120] @ (8003b78 ) 8003b00: 4293 cmp r3, r2 8003b02: d013 beq.n 8003b2c 8003b04: 687b ldr r3, [r7, #4] 8003b06: 681b ldr r3, [r3, #0] 8003b08: 4a1c ldr r2, [pc, #112] @ (8003b7c ) 8003b0a: 4293 cmp r3, r2 8003b0c: d00e beq.n 8003b2c 8003b0e: 687b ldr r3, [r7, #4] 8003b10: 681b ldr r3, [r3, #0] 8003b12: 4a1b ldr r2, [pc, #108] @ (8003b80 ) 8003b14: 4293 cmp r3, r2 8003b16: d009 beq.n 8003b2c 8003b18: 687b ldr r3, [r7, #4] 8003b1a: 681b ldr r3, [r3, #0] 8003b1c: 4a19 ldr r2, [pc, #100] @ (8003b84 ) 8003b1e: 4293 cmp r3, r2 8003b20: d004 beq.n 8003b2c 8003b22: 687b ldr r3, [r7, #4] 8003b24: 681b ldr r3, [r3, #0] 8003b26: 4a18 ldr r2, [pc, #96] @ (8003b88 ) 8003b28: 4293 cmp r3, r2 8003b2a: d12f bne.n 8003b8c 8003b2c: 687b ldr r3, [r7, #4] 8003b2e: 681b ldr r3, [r3, #0] 8003b30: 681b ldr r3, [r3, #0] 8003b32: f003 0304 and.w r3, r3, #4 8003b36: 2b00 cmp r3, #0 8003b38: bf14 ite ne 8003b3a: 2301 movne r3, #1 8003b3c: 2300 moveq r3, #0 8003b3e: b2db uxtb r3, r3 8003b40: e02e b.n 8003ba0 8003b42: bf00 nop 8003b44: 24000000 .word 0x24000000 8003b48: 1b4e81b5 .word 0x1b4e81b5 8003b4c: 40020010 .word 0x40020010 8003b50: 40020028 .word 0x40020028 8003b54: 40020040 .word 0x40020040 8003b58: 40020058 .word 0x40020058 8003b5c: 40020070 .word 0x40020070 8003b60: 40020088 .word 0x40020088 8003b64: 400200a0 .word 0x400200a0 8003b68: 400200b8 .word 0x400200b8 8003b6c: 40020410 .word 0x40020410 8003b70: 40020428 .word 0x40020428 8003b74: 40020440 .word 0x40020440 8003b78: 40020458 .word 0x40020458 8003b7c: 40020470 .word 0x40020470 8003b80: 40020488 .word 0x40020488 8003b84: 400204a0 .word 0x400204a0 8003b88: 400204b8 .word 0x400204b8 8003b8c: 687b ldr r3, [r7, #4] 8003b8e: 681b ldr r3, [r3, #0] 8003b90: 681b ldr r3, [r3, #0] 8003b92: f003 0308 and.w r3, r3, #8 8003b96: 2b00 cmp r3, #0 8003b98: bf14 ite ne 8003b9a: 2301 movne r3, #1 8003b9c: 2300 moveq r3, #0 8003b9e: b2db uxtb r3, r3 8003ba0: 2b00 cmp r3, #0 8003ba2: d015 beq.n 8003bd0 { /* Disable the transfer error interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE); 8003ba4: 687b ldr r3, [r7, #4] 8003ba6: 681b ldr r3, [r3, #0] 8003ba8: 681a ldr r2, [r3, #0] 8003baa: 687b ldr r3, [r7, #4] 8003bac: 681b ldr r3, [r3, #0] 8003bae: f022 0204 bic.w r2, r2, #4 8003bb2: 601a str r2, [r3, #0] /* Clear the transfer error flag */ regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); 8003bb4: 687b ldr r3, [r7, #4] 8003bb6: 6ddb ldr r3, [r3, #92] @ 0x5c 8003bb8: f003 031f and.w r3, r3, #31 8003bbc: 2208 movs r2, #8 8003bbe: 409a lsls r2, r3 8003bc0: 6a3b ldr r3, [r7, #32] 8003bc2: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; 8003bc4: 687b ldr r3, [r7, #4] 8003bc6: 6d5b ldr r3, [r3, #84] @ 0x54 8003bc8: f043 0201 orr.w r2, r3, #1 8003bcc: 687b ldr r3, [r7, #4] 8003bce: 655a str r2, [r3, #84] @ 0x54 } } /* FIFO Error Interrupt management ******************************************/ if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8003bd0: 687b ldr r3, [r7, #4] 8003bd2: 6ddb ldr r3, [r3, #92] @ 0x5c 8003bd4: f003 031f and.w r3, r3, #31 8003bd8: 69ba ldr r2, [r7, #24] 8003bda: fa22 f303 lsr.w r3, r2, r3 8003bde: f003 0301 and.w r3, r3, #1 8003be2: 2b00 cmp r3, #0 8003be4: d06e beq.n 8003cc4 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U) 8003be6: 687b ldr r3, [r7, #4] 8003be8: 681b ldr r3, [r3, #0] 8003bea: 4a69 ldr r2, [pc, #420] @ (8003d90 ) 8003bec: 4293 cmp r3, r2 8003bee: d04a beq.n 8003c86 8003bf0: 687b ldr r3, [r7, #4] 8003bf2: 681b ldr r3, [r3, #0] 8003bf4: 4a67 ldr r2, [pc, #412] @ (8003d94 ) 8003bf6: 4293 cmp r3, r2 8003bf8: d045 beq.n 8003c86 8003bfa: 687b ldr r3, [r7, #4] 8003bfc: 681b ldr r3, [r3, #0] 8003bfe: 4a66 ldr r2, [pc, #408] @ (8003d98 ) 8003c00: 4293 cmp r3, r2 8003c02: d040 beq.n 8003c86 8003c04: 687b ldr r3, [r7, #4] 8003c06: 681b ldr r3, [r3, #0] 8003c08: 4a64 ldr r2, [pc, #400] @ (8003d9c ) 8003c0a: 4293 cmp r3, r2 8003c0c: d03b beq.n 8003c86 8003c0e: 687b ldr r3, [r7, #4] 8003c10: 681b ldr r3, [r3, #0] 8003c12: 4a63 ldr r2, [pc, #396] @ (8003da0 ) 8003c14: 4293 cmp r3, r2 8003c16: d036 beq.n 8003c86 8003c18: 687b ldr r3, [r7, #4] 8003c1a: 681b ldr r3, [r3, #0] 8003c1c: 4a61 ldr r2, [pc, #388] @ (8003da4 ) 8003c1e: 4293 cmp r3, r2 8003c20: d031 beq.n 8003c86 8003c22: 687b ldr r3, [r7, #4] 8003c24: 681b ldr r3, [r3, #0] 8003c26: 4a60 ldr r2, [pc, #384] @ (8003da8 ) 8003c28: 4293 cmp r3, r2 8003c2a: d02c beq.n 8003c86 8003c2c: 687b ldr r3, [r7, #4] 8003c2e: 681b ldr r3, [r3, #0] 8003c30: 4a5e ldr r2, [pc, #376] @ (8003dac ) 8003c32: 4293 cmp r3, r2 8003c34: d027 beq.n 8003c86 8003c36: 687b ldr r3, [r7, #4] 8003c38: 681b ldr r3, [r3, #0] 8003c3a: 4a5d ldr r2, [pc, #372] @ (8003db0 ) 8003c3c: 4293 cmp r3, r2 8003c3e: d022 beq.n 8003c86 8003c40: 687b ldr r3, [r7, #4] 8003c42: 681b ldr r3, [r3, #0] 8003c44: 4a5b ldr r2, [pc, #364] @ (8003db4 ) 8003c46: 4293 cmp r3, r2 8003c48: d01d beq.n 8003c86 8003c4a: 687b ldr r3, [r7, #4] 8003c4c: 681b ldr r3, [r3, #0] 8003c4e: 4a5a ldr r2, [pc, #360] @ (8003db8 ) 8003c50: 4293 cmp r3, r2 8003c52: d018 beq.n 8003c86 8003c54: 687b ldr r3, [r7, #4] 8003c56: 681b ldr r3, [r3, #0] 8003c58: 4a58 ldr r2, [pc, #352] @ (8003dbc ) 8003c5a: 4293 cmp r3, r2 8003c5c: d013 beq.n 8003c86 8003c5e: 687b ldr r3, [r7, #4] 8003c60: 681b ldr r3, [r3, #0] 8003c62: 4a57 ldr r2, [pc, #348] @ (8003dc0 ) 8003c64: 4293 cmp r3, r2 8003c66: d00e beq.n 8003c86 8003c68: 687b ldr r3, [r7, #4] 8003c6a: 681b ldr r3, [r3, #0] 8003c6c: 4a55 ldr r2, [pc, #340] @ (8003dc4 ) 8003c6e: 4293 cmp r3, r2 8003c70: d009 beq.n 8003c86 8003c72: 687b ldr r3, [r7, #4] 8003c74: 681b ldr r3, [r3, #0] 8003c76: 4a54 ldr r2, [pc, #336] @ (8003dc8 ) 8003c78: 4293 cmp r3, r2 8003c7a: d004 beq.n 8003c86 8003c7c: 687b ldr r3, [r7, #4] 8003c7e: 681b ldr r3, [r3, #0] 8003c80: 4a52 ldr r2, [pc, #328] @ (8003dcc ) 8003c82: 4293 cmp r3, r2 8003c84: d10a bne.n 8003c9c 8003c86: 687b ldr r3, [r7, #4] 8003c88: 681b ldr r3, [r3, #0] 8003c8a: 695b ldr r3, [r3, #20] 8003c8c: f003 0380 and.w r3, r3, #128 @ 0x80 8003c90: 2b00 cmp r3, #0 8003c92: bf14 ite ne 8003c94: 2301 movne r3, #1 8003c96: 2300 moveq r3, #0 8003c98: b2db uxtb r3, r3 8003c9a: e003 b.n 8003ca4 8003c9c: 687b ldr r3, [r7, #4] 8003c9e: 681b ldr r3, [r3, #0] 8003ca0: 681b ldr r3, [r3, #0] 8003ca2: 2300 movs r3, #0 8003ca4: 2b00 cmp r3, #0 8003ca6: d00d beq.n 8003cc4 { /* Clear the FIFO error flag */ regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); 8003ca8: 687b ldr r3, [r7, #4] 8003caa: 6ddb ldr r3, [r3, #92] @ 0x5c 8003cac: f003 031f and.w r3, r3, #31 8003cb0: 2201 movs r2, #1 8003cb2: 409a lsls r2, r3 8003cb4: 6a3b ldr r3, [r7, #32] 8003cb6: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; 8003cb8: 687b ldr r3, [r7, #4] 8003cba: 6d5b ldr r3, [r3, #84] @ 0x54 8003cbc: f043 0202 orr.w r2, r3, #2 8003cc0: 687b ldr r3, [r7, #4] 8003cc2: 655a str r2, [r3, #84] @ 0x54 } } /* Direct Mode Error Interrupt management ***********************************/ if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8003cc4: 687b ldr r3, [r7, #4] 8003cc6: 6ddb ldr r3, [r3, #92] @ 0x5c 8003cc8: f003 031f and.w r3, r3, #31 8003ccc: 2204 movs r2, #4 8003cce: 409a lsls r2, r3 8003cd0: 69bb ldr r3, [r7, #24] 8003cd2: 4013 ands r3, r2 8003cd4: 2b00 cmp r3, #0 8003cd6: f000 808f beq.w 8003df8 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U) 8003cda: 687b ldr r3, [r7, #4] 8003cdc: 681b ldr r3, [r3, #0] 8003cde: 4a2c ldr r2, [pc, #176] @ (8003d90 ) 8003ce0: 4293 cmp r3, r2 8003ce2: d04a beq.n 8003d7a 8003ce4: 687b ldr r3, [r7, #4] 8003ce6: 681b ldr r3, [r3, #0] 8003ce8: 4a2a ldr r2, [pc, #168] @ (8003d94 ) 8003cea: 4293 cmp r3, r2 8003cec: d045 beq.n 8003d7a 8003cee: 687b ldr r3, [r7, #4] 8003cf0: 681b ldr r3, [r3, #0] 8003cf2: 4a29 ldr r2, [pc, #164] @ (8003d98 ) 8003cf4: 4293 cmp r3, r2 8003cf6: d040 beq.n 8003d7a 8003cf8: 687b ldr r3, [r7, #4] 8003cfa: 681b ldr r3, [r3, #0] 8003cfc: 4a27 ldr r2, [pc, #156] @ (8003d9c ) 8003cfe: 4293 cmp r3, r2 8003d00: d03b beq.n 8003d7a 8003d02: 687b ldr r3, [r7, #4] 8003d04: 681b ldr r3, [r3, #0] 8003d06: 4a26 ldr r2, [pc, #152] @ (8003da0 ) 8003d08: 4293 cmp r3, r2 8003d0a: d036 beq.n 8003d7a 8003d0c: 687b ldr r3, [r7, #4] 8003d0e: 681b ldr r3, [r3, #0] 8003d10: 4a24 ldr r2, [pc, #144] @ (8003da4 ) 8003d12: 4293 cmp r3, r2 8003d14: d031 beq.n 8003d7a 8003d16: 687b ldr r3, [r7, #4] 8003d18: 681b ldr r3, [r3, #0] 8003d1a: 4a23 ldr r2, [pc, #140] @ (8003da8 ) 8003d1c: 4293 cmp r3, r2 8003d1e: d02c beq.n 8003d7a 8003d20: 687b ldr r3, [r7, #4] 8003d22: 681b ldr r3, [r3, #0] 8003d24: 4a21 ldr r2, [pc, #132] @ (8003dac ) 8003d26: 4293 cmp r3, r2 8003d28: d027 beq.n 8003d7a 8003d2a: 687b ldr r3, [r7, #4] 8003d2c: 681b ldr r3, [r3, #0] 8003d2e: 4a20 ldr r2, [pc, #128] @ (8003db0 ) 8003d30: 4293 cmp r3, r2 8003d32: d022 beq.n 8003d7a 8003d34: 687b ldr r3, [r7, #4] 8003d36: 681b ldr r3, [r3, #0] 8003d38: 4a1e ldr r2, [pc, #120] @ (8003db4 ) 8003d3a: 4293 cmp r3, r2 8003d3c: d01d beq.n 8003d7a 8003d3e: 687b ldr r3, [r7, #4] 8003d40: 681b ldr r3, [r3, #0] 8003d42: 4a1d ldr r2, [pc, #116] @ (8003db8 ) 8003d44: 4293 cmp r3, r2 8003d46: d018 beq.n 8003d7a 8003d48: 687b ldr r3, [r7, #4] 8003d4a: 681b ldr r3, [r3, #0] 8003d4c: 4a1b ldr r2, [pc, #108] @ (8003dbc ) 8003d4e: 4293 cmp r3, r2 8003d50: d013 beq.n 8003d7a 8003d52: 687b ldr r3, [r7, #4] 8003d54: 681b ldr r3, [r3, #0] 8003d56: 4a1a ldr r2, [pc, #104] @ (8003dc0 ) 8003d58: 4293 cmp r3, r2 8003d5a: d00e beq.n 8003d7a 8003d5c: 687b ldr r3, [r7, #4] 8003d5e: 681b ldr r3, [r3, #0] 8003d60: 4a18 ldr r2, [pc, #96] @ (8003dc4 ) 8003d62: 4293 cmp r3, r2 8003d64: d009 beq.n 8003d7a 8003d66: 687b ldr r3, [r7, #4] 8003d68: 681b ldr r3, [r3, #0] 8003d6a: 4a17 ldr r2, [pc, #92] @ (8003dc8 ) 8003d6c: 4293 cmp r3, r2 8003d6e: d004 beq.n 8003d7a 8003d70: 687b ldr r3, [r7, #4] 8003d72: 681b ldr r3, [r3, #0] 8003d74: 4a15 ldr r2, [pc, #84] @ (8003dcc ) 8003d76: 4293 cmp r3, r2 8003d78: d12a bne.n 8003dd0 8003d7a: 687b ldr r3, [r7, #4] 8003d7c: 681b ldr r3, [r3, #0] 8003d7e: 681b ldr r3, [r3, #0] 8003d80: f003 0302 and.w r3, r3, #2 8003d84: 2b00 cmp r3, #0 8003d86: bf14 ite ne 8003d88: 2301 movne r3, #1 8003d8a: 2300 moveq r3, #0 8003d8c: b2db uxtb r3, r3 8003d8e: e023 b.n 8003dd8 8003d90: 40020010 .word 0x40020010 8003d94: 40020028 .word 0x40020028 8003d98: 40020040 .word 0x40020040 8003d9c: 40020058 .word 0x40020058 8003da0: 40020070 .word 0x40020070 8003da4: 40020088 .word 0x40020088 8003da8: 400200a0 .word 0x400200a0 8003dac: 400200b8 .word 0x400200b8 8003db0: 40020410 .word 0x40020410 8003db4: 40020428 .word 0x40020428 8003db8: 40020440 .word 0x40020440 8003dbc: 40020458 .word 0x40020458 8003dc0: 40020470 .word 0x40020470 8003dc4: 40020488 .word 0x40020488 8003dc8: 400204a0 .word 0x400204a0 8003dcc: 400204b8 .word 0x400204b8 8003dd0: 687b ldr r3, [r7, #4] 8003dd2: 681b ldr r3, [r3, #0] 8003dd4: 681b ldr r3, [r3, #0] 8003dd6: 2300 movs r3, #0 8003dd8: 2b00 cmp r3, #0 8003dda: d00d beq.n 8003df8 { /* Clear the direct mode error flag */ regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); 8003ddc: 687b ldr r3, [r7, #4] 8003dde: 6ddb ldr r3, [r3, #92] @ 0x5c 8003de0: f003 031f and.w r3, r3, #31 8003de4: 2204 movs r2, #4 8003de6: 409a lsls r2, r3 8003de8: 6a3b ldr r3, [r7, #32] 8003dea: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; 8003dec: 687b ldr r3, [r7, #4] 8003dee: 6d5b ldr r3, [r3, #84] @ 0x54 8003df0: f043 0204 orr.w r2, r3, #4 8003df4: 687b ldr r3, [r7, #4] 8003df6: 655a str r2, [r3, #84] @ 0x54 } } /* Half Transfer Complete Interrupt management ******************************/ if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8003df8: 687b ldr r3, [r7, #4] 8003dfa: 6ddb ldr r3, [r3, #92] @ 0x5c 8003dfc: f003 031f and.w r3, r3, #31 8003e00: 2210 movs r2, #16 8003e02: 409a lsls r2, r3 8003e04: 69bb ldr r3, [r7, #24] 8003e06: 4013 ands r3, r2 8003e08: 2b00 cmp r3, #0 8003e0a: f000 80a6 beq.w 8003f5a { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) 8003e0e: 687b ldr r3, [r7, #4] 8003e10: 681b ldr r3, [r3, #0] 8003e12: 4a85 ldr r2, [pc, #532] @ (8004028 ) 8003e14: 4293 cmp r3, r2 8003e16: d04a beq.n 8003eae 8003e18: 687b ldr r3, [r7, #4] 8003e1a: 681b ldr r3, [r3, #0] 8003e1c: 4a83 ldr r2, [pc, #524] @ (800402c ) 8003e1e: 4293 cmp r3, r2 8003e20: d045 beq.n 8003eae 8003e22: 687b ldr r3, [r7, #4] 8003e24: 681b ldr r3, [r3, #0] 8003e26: 4a82 ldr r2, [pc, #520] @ (8004030 ) 8003e28: 4293 cmp r3, r2 8003e2a: d040 beq.n 8003eae 8003e2c: 687b ldr r3, [r7, #4] 8003e2e: 681b ldr r3, [r3, #0] 8003e30: 4a80 ldr r2, [pc, #512] @ (8004034 ) 8003e32: 4293 cmp r3, r2 8003e34: d03b beq.n 8003eae 8003e36: 687b ldr r3, [r7, #4] 8003e38: 681b ldr r3, [r3, #0] 8003e3a: 4a7f ldr r2, [pc, #508] @ (8004038 ) 8003e3c: 4293 cmp r3, r2 8003e3e: d036 beq.n 8003eae 8003e40: 687b ldr r3, [r7, #4] 8003e42: 681b ldr r3, [r3, #0] 8003e44: 4a7d ldr r2, [pc, #500] @ (800403c ) 8003e46: 4293 cmp r3, r2 8003e48: d031 beq.n 8003eae 8003e4a: 687b ldr r3, [r7, #4] 8003e4c: 681b ldr r3, [r3, #0] 8003e4e: 4a7c ldr r2, [pc, #496] @ (8004040 ) 8003e50: 4293 cmp r3, r2 8003e52: d02c beq.n 8003eae 8003e54: 687b ldr r3, [r7, #4] 8003e56: 681b ldr r3, [r3, #0] 8003e58: 4a7a ldr r2, [pc, #488] @ (8004044 ) 8003e5a: 4293 cmp r3, r2 8003e5c: d027 beq.n 8003eae 8003e5e: 687b ldr r3, [r7, #4] 8003e60: 681b ldr r3, [r3, #0] 8003e62: 4a79 ldr r2, [pc, #484] @ (8004048 ) 8003e64: 4293 cmp r3, r2 8003e66: d022 beq.n 8003eae 8003e68: 687b ldr r3, [r7, #4] 8003e6a: 681b ldr r3, [r3, #0] 8003e6c: 4a77 ldr r2, [pc, #476] @ (800404c ) 8003e6e: 4293 cmp r3, r2 8003e70: d01d beq.n 8003eae 8003e72: 687b ldr r3, [r7, #4] 8003e74: 681b ldr r3, [r3, #0] 8003e76: 4a76 ldr r2, [pc, #472] @ (8004050 ) 8003e78: 4293 cmp r3, r2 8003e7a: d018 beq.n 8003eae 8003e7c: 687b ldr r3, [r7, #4] 8003e7e: 681b ldr r3, [r3, #0] 8003e80: 4a74 ldr r2, [pc, #464] @ (8004054 ) 8003e82: 4293 cmp r3, r2 8003e84: d013 beq.n 8003eae 8003e86: 687b ldr r3, [r7, #4] 8003e88: 681b ldr r3, [r3, #0] 8003e8a: 4a73 ldr r2, [pc, #460] @ (8004058 ) 8003e8c: 4293 cmp r3, r2 8003e8e: d00e beq.n 8003eae 8003e90: 687b ldr r3, [r7, #4] 8003e92: 681b ldr r3, [r3, #0] 8003e94: 4a71 ldr r2, [pc, #452] @ (800405c ) 8003e96: 4293 cmp r3, r2 8003e98: d009 beq.n 8003eae 8003e9a: 687b ldr r3, [r7, #4] 8003e9c: 681b ldr r3, [r3, #0] 8003e9e: 4a70 ldr r2, [pc, #448] @ (8004060 ) 8003ea0: 4293 cmp r3, r2 8003ea2: d004 beq.n 8003eae 8003ea4: 687b ldr r3, [r7, #4] 8003ea6: 681b ldr r3, [r3, #0] 8003ea8: 4a6e ldr r2, [pc, #440] @ (8004064 ) 8003eaa: 4293 cmp r3, r2 8003eac: d10a bne.n 8003ec4 8003eae: 687b ldr r3, [r7, #4] 8003eb0: 681b ldr r3, [r3, #0] 8003eb2: 681b ldr r3, [r3, #0] 8003eb4: f003 0308 and.w r3, r3, #8 8003eb8: 2b00 cmp r3, #0 8003eba: bf14 ite ne 8003ebc: 2301 movne r3, #1 8003ebe: 2300 moveq r3, #0 8003ec0: b2db uxtb r3, r3 8003ec2: e009 b.n 8003ed8 8003ec4: 687b ldr r3, [r7, #4] 8003ec6: 681b ldr r3, [r3, #0] 8003ec8: 681b ldr r3, [r3, #0] 8003eca: f003 0304 and.w r3, r3, #4 8003ece: 2b00 cmp r3, #0 8003ed0: bf14 ite ne 8003ed2: 2301 movne r3, #1 8003ed4: 2300 moveq r3, #0 8003ed6: b2db uxtb r3, r3 8003ed8: 2b00 cmp r3, #0 8003eda: d03e beq.n 8003f5a { /* Clear the half transfer complete flag */ regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); 8003edc: 687b ldr r3, [r7, #4] 8003ede: 6ddb ldr r3, [r3, #92] @ 0x5c 8003ee0: f003 031f and.w r3, r3, #31 8003ee4: 2210 movs r2, #16 8003ee6: 409a lsls r2, r3 8003ee8: 6a3b ldr r3, [r7, #32] 8003eea: 609a str r2, [r3, #8] /* Multi_Buffering mode enabled */ if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 8003eec: 687b ldr r3, [r7, #4] 8003eee: 681b ldr r3, [r3, #0] 8003ef0: 681b ldr r3, [r3, #0] 8003ef2: f403 2380 and.w r3, r3, #262144 @ 0x40000 8003ef6: 2b00 cmp r3, #0 8003ef8: d018 beq.n 8003f2c { /* Current memory buffer used is Memory 0 */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 8003efa: 687b ldr r3, [r7, #4] 8003efc: 681b ldr r3, [r3, #0] 8003efe: 681b ldr r3, [r3, #0] 8003f00: f403 2300 and.w r3, r3, #524288 @ 0x80000 8003f04: 2b00 cmp r3, #0 8003f06: d108 bne.n 8003f1a { if(hdma->XferHalfCpltCallback != NULL) 8003f08: 687b ldr r3, [r7, #4] 8003f0a: 6c1b ldr r3, [r3, #64] @ 0x40 8003f0c: 2b00 cmp r3, #0 8003f0e: d024 beq.n 8003f5a { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8003f10: 687b ldr r3, [r7, #4] 8003f12: 6c1b ldr r3, [r3, #64] @ 0x40 8003f14: 6878 ldr r0, [r7, #4] 8003f16: 4798 blx r3 8003f18: e01f b.n 8003f5a } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferM1HalfCpltCallback != NULL) 8003f1a: 687b ldr r3, [r7, #4] 8003f1c: 6c9b ldr r3, [r3, #72] @ 0x48 8003f1e: 2b00 cmp r3, #0 8003f20: d01b beq.n 8003f5a { /* Half transfer callback */ hdma->XferM1HalfCpltCallback(hdma); 8003f22: 687b ldr r3, [r7, #4] 8003f24: 6c9b ldr r3, [r3, #72] @ 0x48 8003f26: 6878 ldr r0, [r7, #4] 8003f28: 4798 blx r3 8003f2a: e016 b.n 8003f5a } } else { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 8003f2c: 687b ldr r3, [r7, #4] 8003f2e: 681b ldr r3, [r3, #0] 8003f30: 681b ldr r3, [r3, #0] 8003f32: f403 7380 and.w r3, r3, #256 @ 0x100 8003f36: 2b00 cmp r3, #0 8003f38: d107 bne.n 8003f4a { /* Disable the half transfer interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 8003f3a: 687b ldr r3, [r7, #4] 8003f3c: 681b ldr r3, [r3, #0] 8003f3e: 681a ldr r2, [r3, #0] 8003f40: 687b ldr r3, [r7, #4] 8003f42: 681b ldr r3, [r3, #0] 8003f44: f022 0208 bic.w r2, r2, #8 8003f48: 601a str r2, [r3, #0] } if(hdma->XferHalfCpltCallback != NULL) 8003f4a: 687b ldr r3, [r7, #4] 8003f4c: 6c1b ldr r3, [r3, #64] @ 0x40 8003f4e: 2b00 cmp r3, #0 8003f50: d003 beq.n 8003f5a { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8003f52: 687b ldr r3, [r7, #4] 8003f54: 6c1b ldr r3, [r3, #64] @ 0x40 8003f56: 6878 ldr r0, [r7, #4] 8003f58: 4798 blx r3 } } } } /* Transfer Complete Interrupt management ***********************************/ if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8003f5a: 687b ldr r3, [r7, #4] 8003f5c: 6ddb ldr r3, [r3, #92] @ 0x5c 8003f5e: f003 031f and.w r3, r3, #31 8003f62: 2220 movs r2, #32 8003f64: 409a lsls r2, r3 8003f66: 69bb ldr r3, [r7, #24] 8003f68: 4013 ands r3, r2 8003f6a: 2b00 cmp r3, #0 8003f6c: f000 8110 beq.w 8004190 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) 8003f70: 687b ldr r3, [r7, #4] 8003f72: 681b ldr r3, [r3, #0] 8003f74: 4a2c ldr r2, [pc, #176] @ (8004028 ) 8003f76: 4293 cmp r3, r2 8003f78: d04a beq.n 8004010 8003f7a: 687b ldr r3, [r7, #4] 8003f7c: 681b ldr r3, [r3, #0] 8003f7e: 4a2b ldr r2, [pc, #172] @ (800402c ) 8003f80: 4293 cmp r3, r2 8003f82: d045 beq.n 8004010 8003f84: 687b ldr r3, [r7, #4] 8003f86: 681b ldr r3, [r3, #0] 8003f88: 4a29 ldr r2, [pc, #164] @ (8004030 ) 8003f8a: 4293 cmp r3, r2 8003f8c: d040 beq.n 8004010 8003f8e: 687b ldr r3, [r7, #4] 8003f90: 681b ldr r3, [r3, #0] 8003f92: 4a28 ldr r2, [pc, #160] @ (8004034 ) 8003f94: 4293 cmp r3, r2 8003f96: d03b beq.n 8004010 8003f98: 687b ldr r3, [r7, #4] 8003f9a: 681b ldr r3, [r3, #0] 8003f9c: 4a26 ldr r2, [pc, #152] @ (8004038 ) 8003f9e: 4293 cmp r3, r2 8003fa0: d036 beq.n 8004010 8003fa2: 687b ldr r3, [r7, #4] 8003fa4: 681b ldr r3, [r3, #0] 8003fa6: 4a25 ldr r2, [pc, #148] @ (800403c ) 8003fa8: 4293 cmp r3, r2 8003faa: d031 beq.n 8004010 8003fac: 687b ldr r3, [r7, #4] 8003fae: 681b ldr r3, [r3, #0] 8003fb0: 4a23 ldr r2, [pc, #140] @ (8004040 ) 8003fb2: 4293 cmp r3, r2 8003fb4: d02c beq.n 8004010 8003fb6: 687b ldr r3, [r7, #4] 8003fb8: 681b ldr r3, [r3, #0] 8003fba: 4a22 ldr r2, [pc, #136] @ (8004044 ) 8003fbc: 4293 cmp r3, r2 8003fbe: d027 beq.n 8004010 8003fc0: 687b ldr r3, [r7, #4] 8003fc2: 681b ldr r3, [r3, #0] 8003fc4: 4a20 ldr r2, [pc, #128] @ (8004048 ) 8003fc6: 4293 cmp r3, r2 8003fc8: d022 beq.n 8004010 8003fca: 687b ldr r3, [r7, #4] 8003fcc: 681b ldr r3, [r3, #0] 8003fce: 4a1f ldr r2, [pc, #124] @ (800404c ) 8003fd0: 4293 cmp r3, r2 8003fd2: d01d beq.n 8004010 8003fd4: 687b ldr r3, [r7, #4] 8003fd6: 681b ldr r3, [r3, #0] 8003fd8: 4a1d ldr r2, [pc, #116] @ (8004050 ) 8003fda: 4293 cmp r3, r2 8003fdc: d018 beq.n 8004010 8003fde: 687b ldr r3, [r7, #4] 8003fe0: 681b ldr r3, [r3, #0] 8003fe2: 4a1c ldr r2, [pc, #112] @ (8004054 ) 8003fe4: 4293 cmp r3, r2 8003fe6: d013 beq.n 8004010 8003fe8: 687b ldr r3, [r7, #4] 8003fea: 681b ldr r3, [r3, #0] 8003fec: 4a1a ldr r2, [pc, #104] @ (8004058 ) 8003fee: 4293 cmp r3, r2 8003ff0: d00e beq.n 8004010 8003ff2: 687b ldr r3, [r7, #4] 8003ff4: 681b ldr r3, [r3, #0] 8003ff6: 4a19 ldr r2, [pc, #100] @ (800405c ) 8003ff8: 4293 cmp r3, r2 8003ffa: d009 beq.n 8004010 8003ffc: 687b ldr r3, [r7, #4] 8003ffe: 681b ldr r3, [r3, #0] 8004000: 4a17 ldr r2, [pc, #92] @ (8004060 ) 8004002: 4293 cmp r3, r2 8004004: d004 beq.n 8004010 8004006: 687b ldr r3, [r7, #4] 8004008: 681b ldr r3, [r3, #0] 800400a: 4a16 ldr r2, [pc, #88] @ (8004064 ) 800400c: 4293 cmp r3, r2 800400e: d12b bne.n 8004068 8004010: 687b ldr r3, [r7, #4] 8004012: 681b ldr r3, [r3, #0] 8004014: 681b ldr r3, [r3, #0] 8004016: f003 0310 and.w r3, r3, #16 800401a: 2b00 cmp r3, #0 800401c: bf14 ite ne 800401e: 2301 movne r3, #1 8004020: 2300 moveq r3, #0 8004022: b2db uxtb r3, r3 8004024: e02a b.n 800407c 8004026: bf00 nop 8004028: 40020010 .word 0x40020010 800402c: 40020028 .word 0x40020028 8004030: 40020040 .word 0x40020040 8004034: 40020058 .word 0x40020058 8004038: 40020070 .word 0x40020070 800403c: 40020088 .word 0x40020088 8004040: 400200a0 .word 0x400200a0 8004044: 400200b8 .word 0x400200b8 8004048: 40020410 .word 0x40020410 800404c: 40020428 .word 0x40020428 8004050: 40020440 .word 0x40020440 8004054: 40020458 .word 0x40020458 8004058: 40020470 .word 0x40020470 800405c: 40020488 .word 0x40020488 8004060: 400204a0 .word 0x400204a0 8004064: 400204b8 .word 0x400204b8 8004068: 687b ldr r3, [r7, #4] 800406a: 681b ldr r3, [r3, #0] 800406c: 681b ldr r3, [r3, #0] 800406e: f003 0302 and.w r3, r3, #2 8004072: 2b00 cmp r3, #0 8004074: bf14 ite ne 8004076: 2301 movne r3, #1 8004078: 2300 moveq r3, #0 800407a: b2db uxtb r3, r3 800407c: 2b00 cmp r3, #0 800407e: f000 8087 beq.w 8004190 { /* Clear the transfer complete flag */ regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); 8004082: 687b ldr r3, [r7, #4] 8004084: 6ddb ldr r3, [r3, #92] @ 0x5c 8004086: f003 031f and.w r3, r3, #31 800408a: 2220 movs r2, #32 800408c: 409a lsls r2, r3 800408e: 6a3b ldr r3, [r7, #32] 8004090: 609a str r2, [r3, #8] if(HAL_DMA_STATE_ABORT == hdma->State) 8004092: 687b ldr r3, [r7, #4] 8004094: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8004098: b2db uxtb r3, r3 800409a: 2b04 cmp r3, #4 800409c: d139 bne.n 8004112 { /* Disable all the transfer interrupts */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 800409e: 687b ldr r3, [r7, #4] 80040a0: 681b ldr r3, [r3, #0] 80040a2: 681a ldr r2, [r3, #0] 80040a4: 687b ldr r3, [r7, #4] 80040a6: 681b ldr r3, [r3, #0] 80040a8: f022 0216 bic.w r2, r2, #22 80040ac: 601a str r2, [r3, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 80040ae: 687b ldr r3, [r7, #4] 80040b0: 681b ldr r3, [r3, #0] 80040b2: 695a ldr r2, [r3, #20] 80040b4: 687b ldr r3, [r7, #4] 80040b6: 681b ldr r3, [r3, #0] 80040b8: f022 0280 bic.w r2, r2, #128 @ 0x80 80040bc: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 80040be: 687b ldr r3, [r7, #4] 80040c0: 6c1b ldr r3, [r3, #64] @ 0x40 80040c2: 2b00 cmp r3, #0 80040c4: d103 bne.n 80040ce 80040c6: 687b ldr r3, [r7, #4] 80040c8: 6c9b ldr r3, [r3, #72] @ 0x48 80040ca: 2b00 cmp r3, #0 80040cc: d007 beq.n 80040de { ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 80040ce: 687b ldr r3, [r7, #4] 80040d0: 681b ldr r3, [r3, #0] 80040d2: 681a ldr r2, [r3, #0] 80040d4: 687b ldr r3, [r7, #4] 80040d6: 681b ldr r3, [r3, #0] 80040d8: f022 0208 bic.w r2, r2, #8 80040dc: 601a str r2, [r3, #0] } /* Clear all interrupt flags at correct offset within the register */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 80040de: 687b ldr r3, [r7, #4] 80040e0: 6ddb ldr r3, [r3, #92] @ 0x5c 80040e2: f003 031f and.w r3, r3, #31 80040e6: 223f movs r2, #63 @ 0x3f 80040e8: 409a lsls r2, r3 80040ea: 6a3b ldr r3, [r7, #32] 80040ec: 609a str r2, [r3, #8] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80040ee: 687b ldr r3, [r7, #4] 80040f0: 2201 movs r2, #1 80040f2: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80040f6: 687b ldr r3, [r7, #4] 80040f8: 2200 movs r2, #0 80040fa: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(hdma->XferAbortCallback != NULL) 80040fe: 687b ldr r3, [r7, #4] 8004100: 6d1b ldr r3, [r3, #80] @ 0x50 8004102: 2b00 cmp r3, #0 8004104: f000 834a beq.w 800479c { hdma->XferAbortCallback(hdma); 8004108: 687b ldr r3, [r7, #4] 800410a: 6d1b ldr r3, [r3, #80] @ 0x50 800410c: 6878 ldr r0, [r7, #4] 800410e: 4798 blx r3 } return; 8004110: e344 b.n 800479c } if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 8004112: 687b ldr r3, [r7, #4] 8004114: 681b ldr r3, [r3, #0] 8004116: 681b ldr r3, [r3, #0] 8004118: f403 2380 and.w r3, r3, #262144 @ 0x40000 800411c: 2b00 cmp r3, #0 800411e: d018 beq.n 8004152 { /* Current memory buffer used is Memory 0 */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 8004120: 687b ldr r3, [r7, #4] 8004122: 681b ldr r3, [r3, #0] 8004124: 681b ldr r3, [r3, #0] 8004126: f403 2300 and.w r3, r3, #524288 @ 0x80000 800412a: 2b00 cmp r3, #0 800412c: d108 bne.n 8004140 { if(hdma->XferM1CpltCallback != NULL) 800412e: 687b ldr r3, [r7, #4] 8004130: 6c5b ldr r3, [r3, #68] @ 0x44 8004132: 2b00 cmp r3, #0 8004134: d02c beq.n 8004190 { /* Transfer complete Callback for memory1 */ hdma->XferM1CpltCallback(hdma); 8004136: 687b ldr r3, [r7, #4] 8004138: 6c5b ldr r3, [r3, #68] @ 0x44 800413a: 6878 ldr r0, [r7, #4] 800413c: 4798 blx r3 800413e: e027 b.n 8004190 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 8004140: 687b ldr r3, [r7, #4] 8004142: 6bdb ldr r3, [r3, #60] @ 0x3c 8004144: 2b00 cmp r3, #0 8004146: d023 beq.n 8004190 { /* Transfer complete Callback for memory0 */ hdma->XferCpltCallback(hdma); 8004148: 687b ldr r3, [r7, #4] 800414a: 6bdb ldr r3, [r3, #60] @ 0x3c 800414c: 6878 ldr r0, [r7, #4] 800414e: 4798 blx r3 8004150: e01e b.n 8004190 } } /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 8004152: 687b ldr r3, [r7, #4] 8004154: 681b ldr r3, [r3, #0] 8004156: 681b ldr r3, [r3, #0] 8004158: f403 7380 and.w r3, r3, #256 @ 0x100 800415c: 2b00 cmp r3, #0 800415e: d10f bne.n 8004180 { /* Disable the transfer complete interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC); 8004160: 687b ldr r3, [r7, #4] 8004162: 681b ldr r3, [r3, #0] 8004164: 681a ldr r2, [r3, #0] 8004166: 687b ldr r3, [r7, #4] 8004168: 681b ldr r3, [r3, #0] 800416a: f022 0210 bic.w r2, r2, #16 800416e: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8004170: 687b ldr r3, [r7, #4] 8004172: 2201 movs r2, #1 8004174: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8004178: 687b ldr r3, [r7, #4] 800417a: 2200 movs r2, #0 800417c: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 8004180: 687b ldr r3, [r7, #4] 8004182: 6bdb ldr r3, [r3, #60] @ 0x3c 8004184: 2b00 cmp r3, #0 8004186: d003 beq.n 8004190 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8004188: 687b ldr r3, [r7, #4] 800418a: 6bdb ldr r3, [r3, #60] @ 0x3c 800418c: 6878 ldr r0, [r7, #4] 800418e: 4798 blx r3 } } } /* manage error case */ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) 8004190: 687b ldr r3, [r7, #4] 8004192: 6d5b ldr r3, [r3, #84] @ 0x54 8004194: 2b00 cmp r3, #0 8004196: f000 8306 beq.w 80047a6 { if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U) 800419a: 687b ldr r3, [r7, #4] 800419c: 6d5b ldr r3, [r3, #84] @ 0x54 800419e: f003 0301 and.w r3, r3, #1 80041a2: 2b00 cmp r3, #0 80041a4: f000 8088 beq.w 80042b8 { hdma->State = HAL_DMA_STATE_ABORT; 80041a8: 687b ldr r3, [r7, #4] 80041aa: 2204 movs r2, #4 80041ac: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 80041b0: 687b ldr r3, [r7, #4] 80041b2: 681b ldr r3, [r3, #0] 80041b4: 4a7a ldr r2, [pc, #488] @ (80043a0 ) 80041b6: 4293 cmp r3, r2 80041b8: d04a beq.n 8004250 80041ba: 687b ldr r3, [r7, #4] 80041bc: 681b ldr r3, [r3, #0] 80041be: 4a79 ldr r2, [pc, #484] @ (80043a4 ) 80041c0: 4293 cmp r3, r2 80041c2: d045 beq.n 8004250 80041c4: 687b ldr r3, [r7, #4] 80041c6: 681b ldr r3, [r3, #0] 80041c8: 4a77 ldr r2, [pc, #476] @ (80043a8 ) 80041ca: 4293 cmp r3, r2 80041cc: d040 beq.n 8004250 80041ce: 687b ldr r3, [r7, #4] 80041d0: 681b ldr r3, [r3, #0] 80041d2: 4a76 ldr r2, [pc, #472] @ (80043ac ) 80041d4: 4293 cmp r3, r2 80041d6: d03b beq.n 8004250 80041d8: 687b ldr r3, [r7, #4] 80041da: 681b ldr r3, [r3, #0] 80041dc: 4a74 ldr r2, [pc, #464] @ (80043b0 ) 80041de: 4293 cmp r3, r2 80041e0: d036 beq.n 8004250 80041e2: 687b ldr r3, [r7, #4] 80041e4: 681b ldr r3, [r3, #0] 80041e6: 4a73 ldr r2, [pc, #460] @ (80043b4 ) 80041e8: 4293 cmp r3, r2 80041ea: d031 beq.n 8004250 80041ec: 687b ldr r3, [r7, #4] 80041ee: 681b ldr r3, [r3, #0] 80041f0: 4a71 ldr r2, [pc, #452] @ (80043b8 ) 80041f2: 4293 cmp r3, r2 80041f4: d02c beq.n 8004250 80041f6: 687b ldr r3, [r7, #4] 80041f8: 681b ldr r3, [r3, #0] 80041fa: 4a70 ldr r2, [pc, #448] @ (80043bc ) 80041fc: 4293 cmp r3, r2 80041fe: d027 beq.n 8004250 8004200: 687b ldr r3, [r7, #4] 8004202: 681b ldr r3, [r3, #0] 8004204: 4a6e ldr r2, [pc, #440] @ (80043c0 ) 8004206: 4293 cmp r3, r2 8004208: d022 beq.n 8004250 800420a: 687b ldr r3, [r7, #4] 800420c: 681b ldr r3, [r3, #0] 800420e: 4a6d ldr r2, [pc, #436] @ (80043c4 ) 8004210: 4293 cmp r3, r2 8004212: d01d beq.n 8004250 8004214: 687b ldr r3, [r7, #4] 8004216: 681b ldr r3, [r3, #0] 8004218: 4a6b ldr r2, [pc, #428] @ (80043c8 ) 800421a: 4293 cmp r3, r2 800421c: d018 beq.n 8004250 800421e: 687b ldr r3, [r7, #4] 8004220: 681b ldr r3, [r3, #0] 8004222: 4a6a ldr r2, [pc, #424] @ (80043cc ) 8004224: 4293 cmp r3, r2 8004226: d013 beq.n 8004250 8004228: 687b ldr r3, [r7, #4] 800422a: 681b ldr r3, [r3, #0] 800422c: 4a68 ldr r2, [pc, #416] @ (80043d0 ) 800422e: 4293 cmp r3, r2 8004230: d00e beq.n 8004250 8004232: 687b ldr r3, [r7, #4] 8004234: 681b ldr r3, [r3, #0] 8004236: 4a67 ldr r2, [pc, #412] @ (80043d4 ) 8004238: 4293 cmp r3, r2 800423a: d009 beq.n 8004250 800423c: 687b ldr r3, [r7, #4] 800423e: 681b ldr r3, [r3, #0] 8004240: 4a65 ldr r2, [pc, #404] @ (80043d8 ) 8004242: 4293 cmp r3, r2 8004244: d004 beq.n 8004250 8004246: 687b ldr r3, [r7, #4] 8004248: 681b ldr r3, [r3, #0] 800424a: 4a64 ldr r2, [pc, #400] @ (80043dc ) 800424c: 4293 cmp r3, r2 800424e: d108 bne.n 8004262 8004250: 687b ldr r3, [r7, #4] 8004252: 681b ldr r3, [r3, #0] 8004254: 681a ldr r2, [r3, #0] 8004256: 687b ldr r3, [r7, #4] 8004258: 681b ldr r3, [r3, #0] 800425a: f022 0201 bic.w r2, r2, #1 800425e: 601a str r2, [r3, #0] 8004260: e007 b.n 8004272 8004262: 687b ldr r3, [r7, #4] 8004264: 681b ldr r3, [r3, #0] 8004266: 681a ldr r2, [r3, #0] 8004268: 687b ldr r3, [r7, #4] 800426a: 681b ldr r3, [r3, #0] 800426c: f022 0201 bic.w r2, r2, #1 8004270: 601a str r2, [r3, #0] do { if (++count > timeout) 8004272: 68fb ldr r3, [r7, #12] 8004274: 3301 adds r3, #1 8004276: 60fb str r3, [r7, #12] 8004278: 6a7a ldr r2, [r7, #36] @ 0x24 800427a: 429a cmp r2, r3 800427c: d307 bcc.n 800428e { break; } } while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); 800427e: 687b ldr r3, [r7, #4] 8004280: 681b ldr r3, [r3, #0] 8004282: 681b ldr r3, [r3, #0] 8004284: f003 0301 and.w r3, r3, #1 8004288: 2b00 cmp r3, #0 800428a: d1f2 bne.n 8004272 800428c: e000 b.n 8004290 break; 800428e: bf00 nop if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 8004290: 687b ldr r3, [r7, #4] 8004292: 681b ldr r3, [r3, #0] 8004294: 681b ldr r3, [r3, #0] 8004296: f003 0301 and.w r3, r3, #1 800429a: 2b00 cmp r3, #0 800429c: d004 beq.n 80042a8 { /* Change the DMA state to error if DMA disable fails */ hdma->State = HAL_DMA_STATE_ERROR; 800429e: 687b ldr r3, [r7, #4] 80042a0: 2203 movs r2, #3 80042a2: f883 2035 strb.w r2, [r3, #53] @ 0x35 80042a6: e003 b.n 80042b0 } else { /* Change the DMA state to Ready if DMA disable success */ hdma->State = HAL_DMA_STATE_READY; 80042a8: 687b ldr r3, [r7, #4] 80042aa: 2201 movs r2, #1 80042ac: f883 2035 strb.w r2, [r3, #53] @ 0x35 } /* Process Unlocked */ __HAL_UNLOCK(hdma); 80042b0: 687b ldr r3, [r7, #4] 80042b2: 2200 movs r2, #0 80042b4: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferErrorCallback != NULL) 80042b8: 687b ldr r3, [r7, #4] 80042ba: 6cdb ldr r3, [r3, #76] @ 0x4c 80042bc: 2b00 cmp r3, #0 80042be: f000 8272 beq.w 80047a6 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 80042c2: 687b ldr r3, [r7, #4] 80042c4: 6cdb ldr r3, [r3, #76] @ 0x4c 80042c6: 6878 ldr r0, [r7, #4] 80042c8: 4798 blx r3 80042ca: e26c b.n 80047a6 } } } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 80042cc: 687b ldr r3, [r7, #4] 80042ce: 681b ldr r3, [r3, #0] 80042d0: 4a43 ldr r2, [pc, #268] @ (80043e0 ) 80042d2: 4293 cmp r3, r2 80042d4: d022 beq.n 800431c 80042d6: 687b ldr r3, [r7, #4] 80042d8: 681b ldr r3, [r3, #0] 80042da: 4a42 ldr r2, [pc, #264] @ (80043e4 ) 80042dc: 4293 cmp r3, r2 80042de: d01d beq.n 800431c 80042e0: 687b ldr r3, [r7, #4] 80042e2: 681b ldr r3, [r3, #0] 80042e4: 4a40 ldr r2, [pc, #256] @ (80043e8 ) 80042e6: 4293 cmp r3, r2 80042e8: d018 beq.n 800431c 80042ea: 687b ldr r3, [r7, #4] 80042ec: 681b ldr r3, [r3, #0] 80042ee: 4a3f ldr r2, [pc, #252] @ (80043ec ) 80042f0: 4293 cmp r3, r2 80042f2: d013 beq.n 800431c 80042f4: 687b ldr r3, [r7, #4] 80042f6: 681b ldr r3, [r3, #0] 80042f8: 4a3d ldr r2, [pc, #244] @ (80043f0 ) 80042fa: 4293 cmp r3, r2 80042fc: d00e beq.n 800431c 80042fe: 687b ldr r3, [r7, #4] 8004300: 681b ldr r3, [r3, #0] 8004302: 4a3c ldr r2, [pc, #240] @ (80043f4 ) 8004304: 4293 cmp r3, r2 8004306: d009 beq.n 800431c 8004308: 687b ldr r3, [r7, #4] 800430a: 681b ldr r3, [r3, #0] 800430c: 4a3a ldr r2, [pc, #232] @ (80043f8 ) 800430e: 4293 cmp r3, r2 8004310: d004 beq.n 800431c 8004312: 687b ldr r3, [r7, #4] 8004314: 681b ldr r3, [r3, #0] 8004316: 4a39 ldr r2, [pc, #228] @ (80043fc ) 8004318: 4293 cmp r3, r2 800431a: d101 bne.n 8004320 800431c: 2301 movs r3, #1 800431e: e000 b.n 8004322 8004320: 2300 movs r3, #0 8004322: 2b00 cmp r3, #0 8004324: f000 823f beq.w 80047a6 { ccr_reg = (((BDMA_Channel_TypeDef *)hdma->Instance)->CCR); 8004328: 687b ldr r3, [r7, #4] 800432a: 681b ldr r3, [r3, #0] 800432c: 681b ldr r3, [r3, #0] 800432e: 613b str r3, [r7, #16] /* Half Transfer Complete Interrupt management ******************************/ if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U)) 8004330: 687b ldr r3, [r7, #4] 8004332: 6ddb ldr r3, [r3, #92] @ 0x5c 8004334: f003 031f and.w r3, r3, #31 8004338: 2204 movs r2, #4 800433a: 409a lsls r2, r3 800433c: 697b ldr r3, [r7, #20] 800433e: 4013 ands r3, r2 8004340: 2b00 cmp r3, #0 8004342: f000 80cd beq.w 80044e0 8004346: 693b ldr r3, [r7, #16] 8004348: f003 0304 and.w r3, r3, #4 800434c: 2b00 cmp r3, #0 800434e: f000 80c7 beq.w 80044e0 { /* Clear the half transfer complete flag */ regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU)); 8004352: 687b ldr r3, [r7, #4] 8004354: 6ddb ldr r3, [r3, #92] @ 0x5c 8004356: f003 031f and.w r3, r3, #31 800435a: 2204 movs r2, #4 800435c: 409a lsls r2, r3 800435e: 69fb ldr r3, [r7, #28] 8004360: 605a str r2, [r3, #4] /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ if((ccr_reg & BDMA_CCR_DBM) != 0U) 8004362: 693b ldr r3, [r7, #16] 8004364: f403 4300 and.w r3, r3, #32768 @ 0x8000 8004368: 2b00 cmp r3, #0 800436a: d049 beq.n 8004400 { /* Current memory buffer used is Memory 0 */ if((ccr_reg & BDMA_CCR_CT) == 0U) 800436c: 693b ldr r3, [r7, #16] 800436e: f403 3380 and.w r3, r3, #65536 @ 0x10000 8004372: 2b00 cmp r3, #0 8004374: d109 bne.n 800438a { if(hdma->XferM1HalfCpltCallback != NULL) 8004376: 687b ldr r3, [r7, #4] 8004378: 6c9b ldr r3, [r3, #72] @ 0x48 800437a: 2b00 cmp r3, #0 800437c: f000 8210 beq.w 80047a0 { /* Half transfer Callback for Memory 1 */ hdma->XferM1HalfCpltCallback(hdma); 8004380: 687b ldr r3, [r7, #4] 8004382: 6c9b ldr r3, [r3, #72] @ 0x48 8004384: 6878 ldr r0, [r7, #4] 8004386: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8004388: e20a b.n 80047a0 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferHalfCpltCallback != NULL) 800438a: 687b ldr r3, [r7, #4] 800438c: 6c1b ldr r3, [r3, #64] @ 0x40 800438e: 2b00 cmp r3, #0 8004390: f000 8206 beq.w 80047a0 { /* Half transfer Callback for Memory 0 */ hdma->XferHalfCpltCallback(hdma); 8004394: 687b ldr r3, [r7, #4] 8004396: 6c1b ldr r3, [r3, #64] @ 0x40 8004398: 6878 ldr r0, [r7, #4] 800439a: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800439c: e200 b.n 80047a0 800439e: bf00 nop 80043a0: 40020010 .word 0x40020010 80043a4: 40020028 .word 0x40020028 80043a8: 40020040 .word 0x40020040 80043ac: 40020058 .word 0x40020058 80043b0: 40020070 .word 0x40020070 80043b4: 40020088 .word 0x40020088 80043b8: 400200a0 .word 0x400200a0 80043bc: 400200b8 .word 0x400200b8 80043c0: 40020410 .word 0x40020410 80043c4: 40020428 .word 0x40020428 80043c8: 40020440 .word 0x40020440 80043cc: 40020458 .word 0x40020458 80043d0: 40020470 .word 0x40020470 80043d4: 40020488 .word 0x40020488 80043d8: 400204a0 .word 0x400204a0 80043dc: 400204b8 .word 0x400204b8 80043e0: 58025408 .word 0x58025408 80043e4: 5802541c .word 0x5802541c 80043e8: 58025430 .word 0x58025430 80043ec: 58025444 .word 0x58025444 80043f0: 58025458 .word 0x58025458 80043f4: 5802546c .word 0x5802546c 80043f8: 58025480 .word 0x58025480 80043fc: 58025494 .word 0x58025494 } } } else { if((ccr_reg & BDMA_CCR_CIRC) == 0U) 8004400: 693b ldr r3, [r7, #16] 8004402: f003 0320 and.w r3, r3, #32 8004406: 2b00 cmp r3, #0 8004408: d160 bne.n 80044cc { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 800440a: 687b ldr r3, [r7, #4] 800440c: 681b ldr r3, [r3, #0] 800440e: 4a7f ldr r2, [pc, #508] @ (800460c ) 8004410: 4293 cmp r3, r2 8004412: d04a beq.n 80044aa 8004414: 687b ldr r3, [r7, #4] 8004416: 681b ldr r3, [r3, #0] 8004418: 4a7d ldr r2, [pc, #500] @ (8004610 ) 800441a: 4293 cmp r3, r2 800441c: d045 beq.n 80044aa 800441e: 687b ldr r3, [r7, #4] 8004420: 681b ldr r3, [r3, #0] 8004422: 4a7c ldr r2, [pc, #496] @ (8004614 ) 8004424: 4293 cmp r3, r2 8004426: d040 beq.n 80044aa 8004428: 687b ldr r3, [r7, #4] 800442a: 681b ldr r3, [r3, #0] 800442c: 4a7a ldr r2, [pc, #488] @ (8004618 ) 800442e: 4293 cmp r3, r2 8004430: d03b beq.n 80044aa 8004432: 687b ldr r3, [r7, #4] 8004434: 681b ldr r3, [r3, #0] 8004436: 4a79 ldr r2, [pc, #484] @ (800461c ) 8004438: 4293 cmp r3, r2 800443a: d036 beq.n 80044aa 800443c: 687b ldr r3, [r7, #4] 800443e: 681b ldr r3, [r3, #0] 8004440: 4a77 ldr r2, [pc, #476] @ (8004620 ) 8004442: 4293 cmp r3, r2 8004444: d031 beq.n 80044aa 8004446: 687b ldr r3, [r7, #4] 8004448: 681b ldr r3, [r3, #0] 800444a: 4a76 ldr r2, [pc, #472] @ (8004624 ) 800444c: 4293 cmp r3, r2 800444e: d02c beq.n 80044aa 8004450: 687b ldr r3, [r7, #4] 8004452: 681b ldr r3, [r3, #0] 8004454: 4a74 ldr r2, [pc, #464] @ (8004628 ) 8004456: 4293 cmp r3, r2 8004458: d027 beq.n 80044aa 800445a: 687b ldr r3, [r7, #4] 800445c: 681b ldr r3, [r3, #0] 800445e: 4a73 ldr r2, [pc, #460] @ (800462c ) 8004460: 4293 cmp r3, r2 8004462: d022 beq.n 80044aa 8004464: 687b ldr r3, [r7, #4] 8004466: 681b ldr r3, [r3, #0] 8004468: 4a71 ldr r2, [pc, #452] @ (8004630 ) 800446a: 4293 cmp r3, r2 800446c: d01d beq.n 80044aa 800446e: 687b ldr r3, [r7, #4] 8004470: 681b ldr r3, [r3, #0] 8004472: 4a70 ldr r2, [pc, #448] @ (8004634 ) 8004474: 4293 cmp r3, r2 8004476: d018 beq.n 80044aa 8004478: 687b ldr r3, [r7, #4] 800447a: 681b ldr r3, [r3, #0] 800447c: 4a6e ldr r2, [pc, #440] @ (8004638 ) 800447e: 4293 cmp r3, r2 8004480: d013 beq.n 80044aa 8004482: 687b ldr r3, [r7, #4] 8004484: 681b ldr r3, [r3, #0] 8004486: 4a6d ldr r2, [pc, #436] @ (800463c ) 8004488: 4293 cmp r3, r2 800448a: d00e beq.n 80044aa 800448c: 687b ldr r3, [r7, #4] 800448e: 681b ldr r3, [r3, #0] 8004490: 4a6b ldr r2, [pc, #428] @ (8004640 ) 8004492: 4293 cmp r3, r2 8004494: d009 beq.n 80044aa 8004496: 687b ldr r3, [r7, #4] 8004498: 681b ldr r3, [r3, #0] 800449a: 4a6a ldr r2, [pc, #424] @ (8004644 ) 800449c: 4293 cmp r3, r2 800449e: d004 beq.n 80044aa 80044a0: 687b ldr r3, [r7, #4] 80044a2: 681b ldr r3, [r3, #0] 80044a4: 4a68 ldr r2, [pc, #416] @ (8004648 ) 80044a6: 4293 cmp r3, r2 80044a8: d108 bne.n 80044bc 80044aa: 687b ldr r3, [r7, #4] 80044ac: 681b ldr r3, [r3, #0] 80044ae: 681a ldr r2, [r3, #0] 80044b0: 687b ldr r3, [r7, #4] 80044b2: 681b ldr r3, [r3, #0] 80044b4: f022 0208 bic.w r2, r2, #8 80044b8: 601a str r2, [r3, #0] 80044ba: e007 b.n 80044cc 80044bc: 687b ldr r3, [r7, #4] 80044be: 681b ldr r3, [r3, #0] 80044c0: 681a ldr r2, [r3, #0] 80044c2: 687b ldr r3, [r7, #4] 80044c4: 681b ldr r3, [r3, #0] 80044c6: f022 0204 bic.w r2, r2, #4 80044ca: 601a str r2, [r3, #0] } /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) 80044cc: 687b ldr r3, [r7, #4] 80044ce: 6c1b ldr r3, [r3, #64] @ 0x40 80044d0: 2b00 cmp r3, #0 80044d2: f000 8165 beq.w 80047a0 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 80044d6: 687b ldr r3, [r7, #4] 80044d8: 6c1b ldr r3, [r3, #64] @ 0x40 80044da: 6878 ldr r0, [r7, #4] 80044dc: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 80044de: e15f b.n 80047a0 } } } /* Transfer Complete Interrupt management ***********************************/ else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U)) 80044e0: 687b ldr r3, [r7, #4] 80044e2: 6ddb ldr r3, [r3, #92] @ 0x5c 80044e4: f003 031f and.w r3, r3, #31 80044e8: 2202 movs r2, #2 80044ea: 409a lsls r2, r3 80044ec: 697b ldr r3, [r7, #20] 80044ee: 4013 ands r3, r2 80044f0: 2b00 cmp r3, #0 80044f2: f000 80c5 beq.w 8004680 80044f6: 693b ldr r3, [r7, #16] 80044f8: f003 0302 and.w r3, r3, #2 80044fc: 2b00 cmp r3, #0 80044fe: f000 80bf beq.w 8004680 { /* Clear the transfer complete flag */ regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU); 8004502: 687b ldr r3, [r7, #4] 8004504: 6ddb ldr r3, [r3, #92] @ 0x5c 8004506: f003 031f and.w r3, r3, #31 800450a: 2202 movs r2, #2 800450c: 409a lsls r2, r3 800450e: 69fb ldr r3, [r7, #28] 8004510: 605a str r2, [r3, #4] /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ if((ccr_reg & BDMA_CCR_DBM) != 0U) 8004512: 693b ldr r3, [r7, #16] 8004514: f403 4300 and.w r3, r3, #32768 @ 0x8000 8004518: 2b00 cmp r3, #0 800451a: d018 beq.n 800454e { /* Current memory buffer used is Memory 0 */ if((ccr_reg & BDMA_CCR_CT) == 0U) 800451c: 693b ldr r3, [r7, #16] 800451e: f403 3380 and.w r3, r3, #65536 @ 0x10000 8004522: 2b00 cmp r3, #0 8004524: d109 bne.n 800453a { if(hdma->XferM1CpltCallback != NULL) 8004526: 687b ldr r3, [r7, #4] 8004528: 6c5b ldr r3, [r3, #68] @ 0x44 800452a: 2b00 cmp r3, #0 800452c: f000 813a beq.w 80047a4 { /* Transfer complete Callback for Memory 1 */ hdma->XferM1CpltCallback(hdma); 8004530: 687b ldr r3, [r7, #4] 8004532: 6c5b ldr r3, [r3, #68] @ 0x44 8004534: 6878 ldr r0, [r7, #4] 8004536: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8004538: e134 b.n 80047a4 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 800453a: 687b ldr r3, [r7, #4] 800453c: 6bdb ldr r3, [r3, #60] @ 0x3c 800453e: 2b00 cmp r3, #0 8004540: f000 8130 beq.w 80047a4 { /* Transfer complete Callback for Memory 0 */ hdma->XferCpltCallback(hdma); 8004544: 687b ldr r3, [r7, #4] 8004546: 6bdb ldr r3, [r3, #60] @ 0x3c 8004548: 6878 ldr r0, [r7, #4] 800454a: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800454c: e12a b.n 80047a4 } } } else { if((ccr_reg & BDMA_CCR_CIRC) == 0U) 800454e: 693b ldr r3, [r7, #16] 8004550: f003 0320 and.w r3, r3, #32 8004554: 2b00 cmp r3, #0 8004556: f040 8089 bne.w 800466c { /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 800455a: 687b ldr r3, [r7, #4] 800455c: 681b ldr r3, [r3, #0] 800455e: 4a2b ldr r2, [pc, #172] @ (800460c ) 8004560: 4293 cmp r3, r2 8004562: d04a beq.n 80045fa 8004564: 687b ldr r3, [r7, #4] 8004566: 681b ldr r3, [r3, #0] 8004568: 4a29 ldr r2, [pc, #164] @ (8004610 ) 800456a: 4293 cmp r3, r2 800456c: d045 beq.n 80045fa 800456e: 687b ldr r3, [r7, #4] 8004570: 681b ldr r3, [r3, #0] 8004572: 4a28 ldr r2, [pc, #160] @ (8004614 ) 8004574: 4293 cmp r3, r2 8004576: d040 beq.n 80045fa 8004578: 687b ldr r3, [r7, #4] 800457a: 681b ldr r3, [r3, #0] 800457c: 4a26 ldr r2, [pc, #152] @ (8004618 ) 800457e: 4293 cmp r3, r2 8004580: d03b beq.n 80045fa 8004582: 687b ldr r3, [r7, #4] 8004584: 681b ldr r3, [r3, #0] 8004586: 4a25 ldr r2, [pc, #148] @ (800461c ) 8004588: 4293 cmp r3, r2 800458a: d036 beq.n 80045fa 800458c: 687b ldr r3, [r7, #4] 800458e: 681b ldr r3, [r3, #0] 8004590: 4a23 ldr r2, [pc, #140] @ (8004620 ) 8004592: 4293 cmp r3, r2 8004594: d031 beq.n 80045fa 8004596: 687b ldr r3, [r7, #4] 8004598: 681b ldr r3, [r3, #0] 800459a: 4a22 ldr r2, [pc, #136] @ (8004624 ) 800459c: 4293 cmp r3, r2 800459e: d02c beq.n 80045fa 80045a0: 687b ldr r3, [r7, #4] 80045a2: 681b ldr r3, [r3, #0] 80045a4: 4a20 ldr r2, [pc, #128] @ (8004628 ) 80045a6: 4293 cmp r3, r2 80045a8: d027 beq.n 80045fa 80045aa: 687b ldr r3, [r7, #4] 80045ac: 681b ldr r3, [r3, #0] 80045ae: 4a1f ldr r2, [pc, #124] @ (800462c ) 80045b0: 4293 cmp r3, r2 80045b2: d022 beq.n 80045fa 80045b4: 687b ldr r3, [r7, #4] 80045b6: 681b ldr r3, [r3, #0] 80045b8: 4a1d ldr r2, [pc, #116] @ (8004630 ) 80045ba: 4293 cmp r3, r2 80045bc: d01d beq.n 80045fa 80045be: 687b ldr r3, [r7, #4] 80045c0: 681b ldr r3, [r3, #0] 80045c2: 4a1c ldr r2, [pc, #112] @ (8004634 ) 80045c4: 4293 cmp r3, r2 80045c6: d018 beq.n 80045fa 80045c8: 687b ldr r3, [r7, #4] 80045ca: 681b ldr r3, [r3, #0] 80045cc: 4a1a ldr r2, [pc, #104] @ (8004638 ) 80045ce: 4293 cmp r3, r2 80045d0: d013 beq.n 80045fa 80045d2: 687b ldr r3, [r7, #4] 80045d4: 681b ldr r3, [r3, #0] 80045d6: 4a19 ldr r2, [pc, #100] @ (800463c ) 80045d8: 4293 cmp r3, r2 80045da: d00e beq.n 80045fa 80045dc: 687b ldr r3, [r7, #4] 80045de: 681b ldr r3, [r3, #0] 80045e0: 4a17 ldr r2, [pc, #92] @ (8004640 ) 80045e2: 4293 cmp r3, r2 80045e4: d009 beq.n 80045fa 80045e6: 687b ldr r3, [r7, #4] 80045e8: 681b ldr r3, [r3, #0] 80045ea: 4a16 ldr r2, [pc, #88] @ (8004644 ) 80045ec: 4293 cmp r3, r2 80045ee: d004 beq.n 80045fa 80045f0: 687b ldr r3, [r7, #4] 80045f2: 681b ldr r3, [r3, #0] 80045f4: 4a14 ldr r2, [pc, #80] @ (8004648 ) 80045f6: 4293 cmp r3, r2 80045f8: d128 bne.n 800464c 80045fa: 687b ldr r3, [r7, #4] 80045fc: 681b ldr r3, [r3, #0] 80045fe: 681a ldr r2, [r3, #0] 8004600: 687b ldr r3, [r7, #4] 8004602: 681b ldr r3, [r3, #0] 8004604: f022 0214 bic.w r2, r2, #20 8004608: 601a str r2, [r3, #0] 800460a: e027 b.n 800465c 800460c: 40020010 .word 0x40020010 8004610: 40020028 .word 0x40020028 8004614: 40020040 .word 0x40020040 8004618: 40020058 .word 0x40020058 800461c: 40020070 .word 0x40020070 8004620: 40020088 .word 0x40020088 8004624: 400200a0 .word 0x400200a0 8004628: 400200b8 .word 0x400200b8 800462c: 40020410 .word 0x40020410 8004630: 40020428 .word 0x40020428 8004634: 40020440 .word 0x40020440 8004638: 40020458 .word 0x40020458 800463c: 40020470 .word 0x40020470 8004640: 40020488 .word 0x40020488 8004644: 400204a0 .word 0x400204a0 8004648: 400204b8 .word 0x400204b8 800464c: 687b ldr r3, [r7, #4] 800464e: 681b ldr r3, [r3, #0] 8004650: 681a ldr r2, [r3, #0] 8004652: 687b ldr r3, [r7, #4] 8004654: 681b ldr r3, [r3, #0] 8004656: f022 020a bic.w r2, r2, #10 800465a: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800465c: 687b ldr r3, [r7, #4] 800465e: 2201 movs r2, #1 8004660: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8004664: 687b ldr r3, [r7, #4] 8004666: 2200 movs r2, #0 8004668: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 800466c: 687b ldr r3, [r7, #4] 800466e: 6bdb ldr r3, [r3, #60] @ 0x3c 8004670: 2b00 cmp r3, #0 8004672: f000 8097 beq.w 80047a4 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8004676: 687b ldr r3, [r7, #4] 8004678: 6bdb ldr r3, [r3, #60] @ 0x3c 800467a: 6878 ldr r0, [r7, #4] 800467c: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800467e: e091 b.n 80047a4 } } } /* Transfer Error Interrupt management **************************************/ else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U)) 8004680: 687b ldr r3, [r7, #4] 8004682: 6ddb ldr r3, [r3, #92] @ 0x5c 8004684: f003 031f and.w r3, r3, #31 8004688: 2208 movs r2, #8 800468a: 409a lsls r2, r3 800468c: 697b ldr r3, [r7, #20] 800468e: 4013 ands r3, r2 8004690: 2b00 cmp r3, #0 8004692: f000 8088 beq.w 80047a6 8004696: 693b ldr r3, [r7, #16] 8004698: f003 0308 and.w r3, r3, #8 800469c: 2b00 cmp r3, #0 800469e: f000 8082 beq.w 80047a6 { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 80046a2: 687b ldr r3, [r7, #4] 80046a4: 681b ldr r3, [r3, #0] 80046a6: 4a41 ldr r2, [pc, #260] @ (80047ac ) 80046a8: 4293 cmp r3, r2 80046aa: d04a beq.n 8004742 80046ac: 687b ldr r3, [r7, #4] 80046ae: 681b ldr r3, [r3, #0] 80046b0: 4a3f ldr r2, [pc, #252] @ (80047b0 ) 80046b2: 4293 cmp r3, r2 80046b4: d045 beq.n 8004742 80046b6: 687b ldr r3, [r7, #4] 80046b8: 681b ldr r3, [r3, #0] 80046ba: 4a3e ldr r2, [pc, #248] @ (80047b4 ) 80046bc: 4293 cmp r3, r2 80046be: d040 beq.n 8004742 80046c0: 687b ldr r3, [r7, #4] 80046c2: 681b ldr r3, [r3, #0] 80046c4: 4a3c ldr r2, [pc, #240] @ (80047b8 ) 80046c6: 4293 cmp r3, r2 80046c8: d03b beq.n 8004742 80046ca: 687b ldr r3, [r7, #4] 80046cc: 681b ldr r3, [r3, #0] 80046ce: 4a3b ldr r2, [pc, #236] @ (80047bc ) 80046d0: 4293 cmp r3, r2 80046d2: d036 beq.n 8004742 80046d4: 687b ldr r3, [r7, #4] 80046d6: 681b ldr r3, [r3, #0] 80046d8: 4a39 ldr r2, [pc, #228] @ (80047c0 ) 80046da: 4293 cmp r3, r2 80046dc: d031 beq.n 8004742 80046de: 687b ldr r3, [r7, #4] 80046e0: 681b ldr r3, [r3, #0] 80046e2: 4a38 ldr r2, [pc, #224] @ (80047c4 ) 80046e4: 4293 cmp r3, r2 80046e6: d02c beq.n 8004742 80046e8: 687b ldr r3, [r7, #4] 80046ea: 681b ldr r3, [r3, #0] 80046ec: 4a36 ldr r2, [pc, #216] @ (80047c8 ) 80046ee: 4293 cmp r3, r2 80046f0: d027 beq.n 8004742 80046f2: 687b ldr r3, [r7, #4] 80046f4: 681b ldr r3, [r3, #0] 80046f6: 4a35 ldr r2, [pc, #212] @ (80047cc ) 80046f8: 4293 cmp r3, r2 80046fa: d022 beq.n 8004742 80046fc: 687b ldr r3, [r7, #4] 80046fe: 681b ldr r3, [r3, #0] 8004700: 4a33 ldr r2, [pc, #204] @ (80047d0 ) 8004702: 4293 cmp r3, r2 8004704: d01d beq.n 8004742 8004706: 687b ldr r3, [r7, #4] 8004708: 681b ldr r3, [r3, #0] 800470a: 4a32 ldr r2, [pc, #200] @ (80047d4 ) 800470c: 4293 cmp r3, r2 800470e: d018 beq.n 8004742 8004710: 687b ldr r3, [r7, #4] 8004712: 681b ldr r3, [r3, #0] 8004714: 4a30 ldr r2, [pc, #192] @ (80047d8 ) 8004716: 4293 cmp r3, r2 8004718: d013 beq.n 8004742 800471a: 687b ldr r3, [r7, #4] 800471c: 681b ldr r3, [r3, #0] 800471e: 4a2f ldr r2, [pc, #188] @ (80047dc ) 8004720: 4293 cmp r3, r2 8004722: d00e beq.n 8004742 8004724: 687b ldr r3, [r7, #4] 8004726: 681b ldr r3, [r3, #0] 8004728: 4a2d ldr r2, [pc, #180] @ (80047e0 ) 800472a: 4293 cmp r3, r2 800472c: d009 beq.n 8004742 800472e: 687b ldr r3, [r7, #4] 8004730: 681b ldr r3, [r3, #0] 8004732: 4a2c ldr r2, [pc, #176] @ (80047e4 ) 8004734: 4293 cmp r3, r2 8004736: d004 beq.n 8004742 8004738: 687b ldr r3, [r7, #4] 800473a: 681b ldr r3, [r3, #0] 800473c: 4a2a ldr r2, [pc, #168] @ (80047e8 ) 800473e: 4293 cmp r3, r2 8004740: d108 bne.n 8004754 8004742: 687b ldr r3, [r7, #4] 8004744: 681b ldr r3, [r3, #0] 8004746: 681a ldr r2, [r3, #0] 8004748: 687b ldr r3, [r7, #4] 800474a: 681b ldr r3, [r3, #0] 800474c: f022 021c bic.w r2, r2, #28 8004750: 601a str r2, [r3, #0] 8004752: e007 b.n 8004764 8004754: 687b ldr r3, [r7, #4] 8004756: 681b ldr r3, [r3, #0] 8004758: 681a ldr r2, [r3, #0] 800475a: 687b ldr r3, [r7, #4] 800475c: 681b ldr r3, [r3, #0] 800475e: f022 020e bic.w r2, r2, #14 8004762: 601a str r2, [r3, #0] /* Clear all flags */ regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); 8004764: 687b ldr r3, [r7, #4] 8004766: 6ddb ldr r3, [r3, #92] @ 0x5c 8004768: f003 031f and.w r3, r3, #31 800476c: 2201 movs r2, #1 800476e: 409a lsls r2, r3 8004770: 69fb ldr r3, [r7, #28] 8004772: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 8004774: 687b ldr r3, [r7, #4] 8004776: 2201 movs r2, #1 8004778: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800477a: 687b ldr r3, [r7, #4] 800477c: 2201 movs r2, #1 800477e: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8004782: 687b ldr r3, [r7, #4] 8004784: 2200 movs r2, #0 8004786: f883 2034 strb.w r2, [r3, #52] @ 0x34 if (hdma->XferErrorCallback != NULL) 800478a: 687b ldr r3, [r7, #4] 800478c: 6cdb ldr r3, [r3, #76] @ 0x4c 800478e: 2b00 cmp r3, #0 8004790: d009 beq.n 80047a6 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 8004792: 687b ldr r3, [r7, #4] 8004794: 6cdb ldr r3, [r3, #76] @ 0x4c 8004796: 6878 ldr r0, [r7, #4] 8004798: 4798 blx r3 800479a: e004 b.n 80047a6 return; 800479c: bf00 nop 800479e: e002 b.n 80047a6 if((ccr_reg & BDMA_CCR_DBM) != 0U) 80047a0: bf00 nop 80047a2: e000 b.n 80047a6 if((ccr_reg & BDMA_CCR_DBM) != 0U) 80047a4: bf00 nop } else { /* Nothing To Do */ } } 80047a6: 3728 adds r7, #40 @ 0x28 80047a8: 46bd mov sp, r7 80047aa: bd80 pop {r7, pc} 80047ac: 40020010 .word 0x40020010 80047b0: 40020028 .word 0x40020028 80047b4: 40020040 .word 0x40020040 80047b8: 40020058 .word 0x40020058 80047bc: 40020070 .word 0x40020070 80047c0: 40020088 .word 0x40020088 80047c4: 400200a0 .word 0x400200a0 80047c8: 400200b8 .word 0x400200b8 80047cc: 40020410 .word 0x40020410 80047d0: 40020428 .word 0x40020428 80047d4: 40020440 .word 0x40020440 80047d8: 40020458 .word 0x40020458 80047dc: 40020470 .word 0x40020470 80047e0: 40020488 .word 0x40020488 80047e4: 400204a0 .word 0x400204a0 80047e8: 400204b8 .word 0x400204b8 080047ec : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { 80047ec: b480 push {r7} 80047ee: b085 sub sp, #20 80047f0: af00 add r7, sp, #0 80047f2: 6078 str r0, [r7, #4] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80047f4: 687b ldr r3, [r7, #4] 80047f6: 681b ldr r3, [r3, #0] 80047f8: 4a42 ldr r2, [pc, #264] @ (8004904 ) 80047fa: 4293 cmp r3, r2 80047fc: d04a beq.n 8004894 80047fe: 687b ldr r3, [r7, #4] 8004800: 681b ldr r3, [r3, #0] 8004802: 4a41 ldr r2, [pc, #260] @ (8004908 ) 8004804: 4293 cmp r3, r2 8004806: d045 beq.n 8004894 8004808: 687b ldr r3, [r7, #4] 800480a: 681b ldr r3, [r3, #0] 800480c: 4a3f ldr r2, [pc, #252] @ (800490c ) 800480e: 4293 cmp r3, r2 8004810: d040 beq.n 8004894 8004812: 687b ldr r3, [r7, #4] 8004814: 681b ldr r3, [r3, #0] 8004816: 4a3e ldr r2, [pc, #248] @ (8004910 ) 8004818: 4293 cmp r3, r2 800481a: d03b beq.n 8004894 800481c: 687b ldr r3, [r7, #4] 800481e: 681b ldr r3, [r3, #0] 8004820: 4a3c ldr r2, [pc, #240] @ (8004914 ) 8004822: 4293 cmp r3, r2 8004824: d036 beq.n 8004894 8004826: 687b ldr r3, [r7, #4] 8004828: 681b ldr r3, [r3, #0] 800482a: 4a3b ldr r2, [pc, #236] @ (8004918 ) 800482c: 4293 cmp r3, r2 800482e: d031 beq.n 8004894 8004830: 687b ldr r3, [r7, #4] 8004832: 681b ldr r3, [r3, #0] 8004834: 4a39 ldr r2, [pc, #228] @ (800491c ) 8004836: 4293 cmp r3, r2 8004838: d02c beq.n 8004894 800483a: 687b ldr r3, [r7, #4] 800483c: 681b ldr r3, [r3, #0] 800483e: 4a38 ldr r2, [pc, #224] @ (8004920 ) 8004840: 4293 cmp r3, r2 8004842: d027 beq.n 8004894 8004844: 687b ldr r3, [r7, #4] 8004846: 681b ldr r3, [r3, #0] 8004848: 4a36 ldr r2, [pc, #216] @ (8004924 ) 800484a: 4293 cmp r3, r2 800484c: d022 beq.n 8004894 800484e: 687b ldr r3, [r7, #4] 8004850: 681b ldr r3, [r3, #0] 8004852: 4a35 ldr r2, [pc, #212] @ (8004928 ) 8004854: 4293 cmp r3, r2 8004856: d01d beq.n 8004894 8004858: 687b ldr r3, [r7, #4] 800485a: 681b ldr r3, [r3, #0] 800485c: 4a33 ldr r2, [pc, #204] @ (800492c ) 800485e: 4293 cmp r3, r2 8004860: d018 beq.n 8004894 8004862: 687b ldr r3, [r7, #4] 8004864: 681b ldr r3, [r3, #0] 8004866: 4a32 ldr r2, [pc, #200] @ (8004930 ) 8004868: 4293 cmp r3, r2 800486a: d013 beq.n 8004894 800486c: 687b ldr r3, [r7, #4] 800486e: 681b ldr r3, [r3, #0] 8004870: 4a30 ldr r2, [pc, #192] @ (8004934 ) 8004872: 4293 cmp r3, r2 8004874: d00e beq.n 8004894 8004876: 687b ldr r3, [r7, #4] 8004878: 681b ldr r3, [r3, #0] 800487a: 4a2f ldr r2, [pc, #188] @ (8004938 ) 800487c: 4293 cmp r3, r2 800487e: d009 beq.n 8004894 8004880: 687b ldr r3, [r7, #4] 8004882: 681b ldr r3, [r3, #0] 8004884: 4a2d ldr r2, [pc, #180] @ (800493c ) 8004886: 4293 cmp r3, r2 8004888: d004 beq.n 8004894 800488a: 687b ldr r3, [r7, #4] 800488c: 681b ldr r3, [r3, #0] 800488e: 4a2c ldr r2, [pc, #176] @ (8004940 ) 8004890: 4293 cmp r3, r2 8004892: d101 bne.n 8004898 8004894: 2301 movs r3, #1 8004896: e000 b.n 800489a 8004898: 2300 movs r3, #0 800489a: 2b00 cmp r3, #0 800489c: d024 beq.n 80048e8 { uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 800489e: 687b ldr r3, [r7, #4] 80048a0: 681b ldr r3, [r3, #0] 80048a2: b2db uxtb r3, r3 80048a4: 3b10 subs r3, #16 80048a6: 4a27 ldr r2, [pc, #156] @ (8004944 ) 80048a8: fba2 2303 umull r2, r3, r2, r3 80048ac: 091b lsrs r3, r3, #4 80048ae: 60fb str r3, [r7, #12] /* lookup table for necessary bitshift of flags within status registers */ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U]; 80048b0: 68fb ldr r3, [r7, #12] 80048b2: f003 0307 and.w r3, r3, #7 80048b6: 4a24 ldr r2, [pc, #144] @ (8004948 ) 80048b8: 5cd3 ldrb r3, [r2, r3] 80048ba: 461a mov r2, r3 80048bc: 687b ldr r3, [r7, #4] 80048be: 65da str r2, [r3, #92] @ 0x5c if (stream_number > 3U) 80048c0: 68fb ldr r3, [r7, #12] 80048c2: 2b03 cmp r3, #3 80048c4: d908 bls.n 80048d8 { /* return pointer to HISR and HIFCR */ hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U); 80048c6: 687b ldr r3, [r7, #4] 80048c8: 681b ldr r3, [r3, #0] 80048ca: 461a mov r2, r3 80048cc: 4b1f ldr r3, [pc, #124] @ (800494c ) 80048ce: 4013 ands r3, r2 80048d0: 1d1a adds r2, r3, #4 80048d2: 687b ldr r3, [r7, #4] 80048d4: 659a str r2, [r3, #88] @ 0x58 80048d6: e00d b.n 80048f4 } else { /* return pointer to LISR and LIFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)); 80048d8: 687b ldr r3, [r7, #4] 80048da: 681b ldr r3, [r3, #0] 80048dc: 461a mov r2, r3 80048de: 4b1b ldr r3, [pc, #108] @ (800494c ) 80048e0: 4013 ands r3, r2 80048e2: 687a ldr r2, [r7, #4] 80048e4: 6593 str r3, [r2, #88] @ 0x58 80048e6: e005 b.n 80048f4 } } else /* BDMA instance(s) */ { /* return pointer to ISR and IFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU)); 80048e8: 687b ldr r3, [r7, #4] 80048ea: 681b ldr r3, [r3, #0] 80048ec: f023 02ff bic.w r2, r3, #255 @ 0xff 80048f0: 687b ldr r3, [r7, #4] 80048f2: 659a str r2, [r3, #88] @ 0x58 } return hdma->StreamBaseAddress; 80048f4: 687b ldr r3, [r7, #4] 80048f6: 6d9b ldr r3, [r3, #88] @ 0x58 } 80048f8: 4618 mov r0, r3 80048fa: 3714 adds r7, #20 80048fc: 46bd mov sp, r7 80048fe: f85d 7b04 ldr.w r7, [sp], #4 8004902: 4770 bx lr 8004904: 40020010 .word 0x40020010 8004908: 40020028 .word 0x40020028 800490c: 40020040 .word 0x40020040 8004910: 40020058 .word 0x40020058 8004914: 40020070 .word 0x40020070 8004918: 40020088 .word 0x40020088 800491c: 400200a0 .word 0x400200a0 8004920: 400200b8 .word 0x400200b8 8004924: 40020410 .word 0x40020410 8004928: 40020428 .word 0x40020428 800492c: 40020440 .word 0x40020440 8004930: 40020458 .word 0x40020458 8004934: 40020470 .word 0x40020470 8004938: 40020488 .word 0x40020488 800493c: 400204a0 .word 0x400204a0 8004940: 400204b8 .word 0x400204b8 8004944: aaaaaaab .word 0xaaaaaaab 8004948: 0800aac4 .word 0x0800aac4 800494c: fffffc00 .word 0xfffffc00 08004950 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static HAL_StatusTypeDef DMA_CheckFifoParam(const DMA_HandleTypeDef *hdma) { 8004950: b480 push {r7} 8004952: b085 sub sp, #20 8004954: af00 add r7, sp, #0 8004956: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8004958: 2300 movs r3, #0 800495a: 73fb strb r3, [r7, #15] /* Memory Data size equal to Byte */ if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) 800495c: 687b ldr r3, [r7, #4] 800495e: 699b ldr r3, [r3, #24] 8004960: 2b00 cmp r3, #0 8004962: d120 bne.n 80049a6 { switch (hdma->Init.FIFOThreshold) 8004964: 687b ldr r3, [r7, #4] 8004966: 6a9b ldr r3, [r3, #40] @ 0x28 8004968: 2b03 cmp r3, #3 800496a: d858 bhi.n 8004a1e 800496c: a201 add r2, pc, #4 @ (adr r2, 8004974 ) 800496e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004972: bf00 nop 8004974: 08004985 .word 0x08004985 8004978: 08004997 .word 0x08004997 800497c: 08004985 .word 0x08004985 8004980: 08004a1f .word 0x08004a1f { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8004984: 687b ldr r3, [r7, #4] 8004986: 6adb ldr r3, [r3, #44] @ 0x2c 8004988: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800498c: 2b00 cmp r3, #0 800498e: d048 beq.n 8004a22 { status = HAL_ERROR; 8004990: 2301 movs r3, #1 8004992: 73fb strb r3, [r7, #15] } break; 8004994: e045 b.n 8004a22 case DMA_FIFO_THRESHOLD_HALFFULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 8004996: 687b ldr r3, [r7, #4] 8004998: 6adb ldr r3, [r3, #44] @ 0x2c 800499a: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800499e: d142 bne.n 8004a26 { status = HAL_ERROR; 80049a0: 2301 movs r3, #1 80049a2: 73fb strb r3, [r7, #15] } break; 80049a4: e03f b.n 8004a26 break; } } /* Memory Data size equal to Half-Word */ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 80049a6: 687b ldr r3, [r7, #4] 80049a8: 699b ldr r3, [r3, #24] 80049aa: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80049ae: d123 bne.n 80049f8 { switch (hdma->Init.FIFOThreshold) 80049b0: 687b ldr r3, [r7, #4] 80049b2: 6a9b ldr r3, [r3, #40] @ 0x28 80049b4: 2b03 cmp r3, #3 80049b6: d838 bhi.n 8004a2a 80049b8: a201 add r2, pc, #4 @ (adr r2, 80049c0 ) 80049ba: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80049be: bf00 nop 80049c0: 080049d1 .word 0x080049d1 80049c4: 080049d7 .word 0x080049d7 80049c8: 080049d1 .word 0x080049d1 80049cc: 080049e9 .word 0x080049e9 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: status = HAL_ERROR; 80049d0: 2301 movs r3, #1 80049d2: 73fb strb r3, [r7, #15] break; 80049d4: e030 b.n 8004a38 case DMA_FIFO_THRESHOLD_HALFFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 80049d6: 687b ldr r3, [r7, #4] 80049d8: 6adb ldr r3, [r3, #44] @ 0x2c 80049da: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 80049de: 2b00 cmp r3, #0 80049e0: d025 beq.n 8004a2e { status = HAL_ERROR; 80049e2: 2301 movs r3, #1 80049e4: 73fb strb r3, [r7, #15] } break; 80049e6: e022 b.n 8004a2e case DMA_FIFO_THRESHOLD_FULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 80049e8: 687b ldr r3, [r7, #4] 80049ea: 6adb ldr r3, [r3, #44] @ 0x2c 80049ec: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 80049f0: d11f bne.n 8004a32 { status = HAL_ERROR; 80049f2: 2301 movs r3, #1 80049f4: 73fb strb r3, [r7, #15] } break; 80049f6: e01c b.n 8004a32 } /* Memory Data size equal to Word */ else { switch (hdma->Init.FIFOThreshold) 80049f8: 687b ldr r3, [r7, #4] 80049fa: 6a9b ldr r3, [r3, #40] @ 0x28 80049fc: 2b02 cmp r3, #2 80049fe: d902 bls.n 8004a06 8004a00: 2b03 cmp r3, #3 8004a02: d003 beq.n 8004a0c status = HAL_ERROR; } break; default: break; 8004a04: e018 b.n 8004a38 status = HAL_ERROR; 8004a06: 2301 movs r3, #1 8004a08: 73fb strb r3, [r7, #15] break; 8004a0a: e015 b.n 8004a38 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8004a0c: 687b ldr r3, [r7, #4] 8004a0e: 6adb ldr r3, [r3, #44] @ 0x2c 8004a10: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8004a14: 2b00 cmp r3, #0 8004a16: d00e beq.n 8004a36 status = HAL_ERROR; 8004a18: 2301 movs r3, #1 8004a1a: 73fb strb r3, [r7, #15] break; 8004a1c: e00b b.n 8004a36 break; 8004a1e: bf00 nop 8004a20: e00a b.n 8004a38 break; 8004a22: bf00 nop 8004a24: e008 b.n 8004a38 break; 8004a26: bf00 nop 8004a28: e006 b.n 8004a38 break; 8004a2a: bf00 nop 8004a2c: e004 b.n 8004a38 break; 8004a2e: bf00 nop 8004a30: e002 b.n 8004a38 break; 8004a32: bf00 nop 8004a34: e000 b.n 8004a38 break; 8004a36: bf00 nop } } return status; 8004a38: 7bfb ldrb r3, [r7, #15] } 8004a3a: 4618 mov r0, r3 8004a3c: 3714 adds r7, #20 8004a3e: 46bd mov sp, r7 8004a40: f85d 7b04 ldr.w r7, [sp], #4 8004a44: 4770 bx lr 8004a46: bf00 nop 08004a48 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { 8004a48: b480 push {r7} 8004a4a: b085 sub sp, #20 8004a4c: af00 add r7, sp, #0 8004a4e: 6078 str r0, [r7, #4] uint32_t stream_number; uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance); 8004a50: 687b ldr r3, [r7, #4] 8004a52: 681b ldr r3, [r3, #0] 8004a54: 60bb str r3, [r7, #8] if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 8004a56: 687b ldr r3, [r7, #4] 8004a58: 681b ldr r3, [r3, #0] 8004a5a: 4a38 ldr r2, [pc, #224] @ (8004b3c ) 8004a5c: 4293 cmp r3, r2 8004a5e: d022 beq.n 8004aa6 8004a60: 687b ldr r3, [r7, #4] 8004a62: 681b ldr r3, [r3, #0] 8004a64: 4a36 ldr r2, [pc, #216] @ (8004b40 ) 8004a66: 4293 cmp r3, r2 8004a68: d01d beq.n 8004aa6 8004a6a: 687b ldr r3, [r7, #4] 8004a6c: 681b ldr r3, [r3, #0] 8004a6e: 4a35 ldr r2, [pc, #212] @ (8004b44 ) 8004a70: 4293 cmp r3, r2 8004a72: d018 beq.n 8004aa6 8004a74: 687b ldr r3, [r7, #4] 8004a76: 681b ldr r3, [r3, #0] 8004a78: 4a33 ldr r2, [pc, #204] @ (8004b48 ) 8004a7a: 4293 cmp r3, r2 8004a7c: d013 beq.n 8004aa6 8004a7e: 687b ldr r3, [r7, #4] 8004a80: 681b ldr r3, [r3, #0] 8004a82: 4a32 ldr r2, [pc, #200] @ (8004b4c ) 8004a84: 4293 cmp r3, r2 8004a86: d00e beq.n 8004aa6 8004a88: 687b ldr r3, [r7, #4] 8004a8a: 681b ldr r3, [r3, #0] 8004a8c: 4a30 ldr r2, [pc, #192] @ (8004b50 ) 8004a8e: 4293 cmp r3, r2 8004a90: d009 beq.n 8004aa6 8004a92: 687b ldr r3, [r7, #4] 8004a94: 681b ldr r3, [r3, #0] 8004a96: 4a2f ldr r2, [pc, #188] @ (8004b54 ) 8004a98: 4293 cmp r3, r2 8004a9a: d004 beq.n 8004aa6 8004a9c: 687b ldr r3, [r7, #4] 8004a9e: 681b ldr r3, [r3, #0] 8004aa0: 4a2d ldr r2, [pc, #180] @ (8004b58 ) 8004aa2: 4293 cmp r3, r2 8004aa4: d101 bne.n 8004aaa 8004aa6: 2301 movs r3, #1 8004aa8: e000 b.n 8004aac 8004aaa: 2300 movs r3, #0 8004aac: 2b00 cmp r3, #0 8004aae: d01a beq.n 8004ae6 { /* BDMA Channels are connected to DMAMUX2 channels */ stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U; 8004ab0: 687b ldr r3, [r7, #4] 8004ab2: 681b ldr r3, [r3, #0] 8004ab4: b2db uxtb r3, r3 8004ab6: 3b08 subs r3, #8 8004ab8: 4a28 ldr r2, [pc, #160] @ (8004b5c ) 8004aba: fba2 2303 umull r2, r3, r2, r3 8004abe: 091b lsrs r3, r3, #4 8004ac0: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U))); 8004ac2: 68fa ldr r2, [r7, #12] 8004ac4: 4b26 ldr r3, [pc, #152] @ (8004b60 ) 8004ac6: 4413 add r3, r2 8004ac8: 009b lsls r3, r3, #2 8004aca: 461a mov r2, r3 8004acc: 687b ldr r3, [r7, #4] 8004ace: 661a str r2, [r3, #96] @ 0x60 hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus; 8004ad0: 687b ldr r3, [r7, #4] 8004ad2: 4a24 ldr r2, [pc, #144] @ (8004b64 ) 8004ad4: 665a str r2, [r3, #100] @ 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 8004ad6: 68fb ldr r3, [r7, #12] 8004ad8: f003 031f and.w r3, r3, #31 8004adc: 2201 movs r2, #1 8004ade: 409a lsls r2, r3 8004ae0: 687b ldr r3, [r7, #4] 8004ae2: 669a str r2, [r3, #104] @ 0x68 } hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); } } 8004ae4: e024 b.n 8004b30 stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 8004ae6: 687b ldr r3, [r7, #4] 8004ae8: 681b ldr r3, [r3, #0] 8004aea: b2db uxtb r3, r3 8004aec: 3b10 subs r3, #16 8004aee: 4a1e ldr r2, [pc, #120] @ (8004b68 ) 8004af0: fba2 2303 umull r2, r3, r2, r3 8004af4: 091b lsrs r3, r3, #4 8004af6: 60fb str r3, [r7, #12] if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \ 8004af8: 68bb ldr r3, [r7, #8] 8004afa: 4a1c ldr r2, [pc, #112] @ (8004b6c ) 8004afc: 4293 cmp r3, r2 8004afe: d806 bhi.n 8004b0e 8004b00: 68bb ldr r3, [r7, #8] 8004b02: 4a1b ldr r2, [pc, #108] @ (8004b70 ) 8004b04: 4293 cmp r3, r2 8004b06: d902 bls.n 8004b0e stream_number += 8U; 8004b08: 68fb ldr r3, [r7, #12] 8004b0a: 3308 adds r3, #8 8004b0c: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); 8004b0e: 68fa ldr r2, [r7, #12] 8004b10: 4b18 ldr r3, [pc, #96] @ (8004b74 ) 8004b12: 4413 add r3, r2 8004b14: 009b lsls r3, r3, #2 8004b16: 461a mov r2, r3 8004b18: 687b ldr r3, [r7, #4] 8004b1a: 661a str r2, [r3, #96] @ 0x60 hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; 8004b1c: 687b ldr r3, [r7, #4] 8004b1e: 4a16 ldr r2, [pc, #88] @ (8004b78 ) 8004b20: 665a str r2, [r3, #100] @ 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 8004b22: 68fb ldr r3, [r7, #12] 8004b24: f003 031f and.w r3, r3, #31 8004b28: 2201 movs r2, #1 8004b2a: 409a lsls r2, r3 8004b2c: 687b ldr r3, [r7, #4] 8004b2e: 669a str r2, [r3, #104] @ 0x68 } 8004b30: bf00 nop 8004b32: 3714 adds r7, #20 8004b34: 46bd mov sp, r7 8004b36: f85d 7b04 ldr.w r7, [sp], #4 8004b3a: 4770 bx lr 8004b3c: 58025408 .word 0x58025408 8004b40: 5802541c .word 0x5802541c 8004b44: 58025430 .word 0x58025430 8004b48: 58025444 .word 0x58025444 8004b4c: 58025458 .word 0x58025458 8004b50: 5802546c .word 0x5802546c 8004b54: 58025480 .word 0x58025480 8004b58: 58025494 .word 0x58025494 8004b5c: cccccccd .word 0xcccccccd 8004b60: 16009600 .word 0x16009600 8004b64: 58025880 .word 0x58025880 8004b68: aaaaaaab .word 0xaaaaaaab 8004b6c: 400204b8 .word 0x400204b8 8004b70: 4002040f .word 0x4002040f 8004b74: 10008200 .word 0x10008200 8004b78: 40020880 .word 0x40020880 08004b7c : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { 8004b7c: b480 push {r7} 8004b7e: b085 sub sp, #20 8004b80: af00 add r7, sp, #0 8004b82: 6078 str r0, [r7, #4] uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; 8004b84: 687b ldr r3, [r7, #4] 8004b86: 685b ldr r3, [r3, #4] 8004b88: b2db uxtb r3, r3 8004b8a: 60fb str r3, [r7, #12] if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7)) 8004b8c: 68fb ldr r3, [r7, #12] 8004b8e: 2b00 cmp r3, #0 8004b90: d04a beq.n 8004c28 8004b92: 68fb ldr r3, [r7, #12] 8004b94: 2b08 cmp r3, #8 8004b96: d847 bhi.n 8004c28 { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 8004b98: 687b ldr r3, [r7, #4] 8004b9a: 681b ldr r3, [r3, #0] 8004b9c: 4a25 ldr r2, [pc, #148] @ (8004c34 ) 8004b9e: 4293 cmp r3, r2 8004ba0: d022 beq.n 8004be8 8004ba2: 687b ldr r3, [r7, #4] 8004ba4: 681b ldr r3, [r3, #0] 8004ba6: 4a24 ldr r2, [pc, #144] @ (8004c38 ) 8004ba8: 4293 cmp r3, r2 8004baa: d01d beq.n 8004be8 8004bac: 687b ldr r3, [r7, #4] 8004bae: 681b ldr r3, [r3, #0] 8004bb0: 4a22 ldr r2, [pc, #136] @ (8004c3c ) 8004bb2: 4293 cmp r3, r2 8004bb4: d018 beq.n 8004be8 8004bb6: 687b ldr r3, [r7, #4] 8004bb8: 681b ldr r3, [r3, #0] 8004bba: 4a21 ldr r2, [pc, #132] @ (8004c40 ) 8004bbc: 4293 cmp r3, r2 8004bbe: d013 beq.n 8004be8 8004bc0: 687b ldr r3, [r7, #4] 8004bc2: 681b ldr r3, [r3, #0] 8004bc4: 4a1f ldr r2, [pc, #124] @ (8004c44 ) 8004bc6: 4293 cmp r3, r2 8004bc8: d00e beq.n 8004be8 8004bca: 687b ldr r3, [r7, #4] 8004bcc: 681b ldr r3, [r3, #0] 8004bce: 4a1e ldr r2, [pc, #120] @ (8004c48 ) 8004bd0: 4293 cmp r3, r2 8004bd2: d009 beq.n 8004be8 8004bd4: 687b ldr r3, [r7, #4] 8004bd6: 681b ldr r3, [r3, #0] 8004bd8: 4a1c ldr r2, [pc, #112] @ (8004c4c ) 8004bda: 4293 cmp r3, r2 8004bdc: d004 beq.n 8004be8 8004bde: 687b ldr r3, [r7, #4] 8004be0: 681b ldr r3, [r3, #0] 8004be2: 4a1b ldr r2, [pc, #108] @ (8004c50 ) 8004be4: 4293 cmp r3, r2 8004be6: d101 bne.n 8004bec 8004be8: 2301 movs r3, #1 8004bea: e000 b.n 8004bee 8004bec: 2300 movs r3, #0 8004bee: 2b00 cmp r3, #0 8004bf0: d00a beq.n 8004c08 { /* BDMA Channels are connected to DMAMUX2 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U))); 8004bf2: 68fa ldr r2, [r7, #12] 8004bf4: 4b17 ldr r3, [pc, #92] @ (8004c54 ) 8004bf6: 4413 add r3, r2 8004bf8: 009b lsls r3, r3, #2 8004bfa: 461a mov r2, r3 8004bfc: 687b ldr r3, [r7, #4] 8004bfe: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus; 8004c00: 687b ldr r3, [r7, #4] 8004c02: 4a15 ldr r2, [pc, #84] @ (8004c58 ) 8004c04: 671a str r2, [r3, #112] @ 0x70 8004c06: e009 b.n 8004c1c } else { /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 8004c08: 68fa ldr r2, [r7, #12] 8004c0a: 4b14 ldr r3, [pc, #80] @ (8004c5c ) 8004c0c: 4413 add r3, r2 8004c0e: 009b lsls r3, r3, #2 8004c10: 461a mov r2, r3 8004c12: 687b ldr r3, [r7, #4] 8004c14: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 8004c16: 687b ldr r3, [r7, #4] 8004c18: 4a11 ldr r2, [pc, #68] @ (8004c60 ) 8004c1a: 671a str r2, [r3, #112] @ 0x70 } hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U); 8004c1c: 68fb ldr r3, [r7, #12] 8004c1e: 3b01 subs r3, #1 8004c20: 2201 movs r2, #1 8004c22: 409a lsls r2, r3 8004c24: 687b ldr r3, [r7, #4] 8004c26: 675a str r2, [r3, #116] @ 0x74 } } 8004c28: bf00 nop 8004c2a: 3714 adds r7, #20 8004c2c: 46bd mov sp, r7 8004c2e: f85d 7b04 ldr.w r7, [sp], #4 8004c32: 4770 bx lr 8004c34: 58025408 .word 0x58025408 8004c38: 5802541c .word 0x5802541c 8004c3c: 58025430 .word 0x58025430 8004c40: 58025444 .word 0x58025444 8004c44: 58025458 .word 0x58025458 8004c48: 5802546c .word 0x5802546c 8004c4c: 58025480 .word 0x58025480 8004c50: 58025494 .word 0x58025494 8004c54: 1600963f .word 0x1600963f 8004c58: 58025940 .word 0x58025940 8004c5c: 1000823f .word 0x1000823f 8004c60: 40020940 .word 0x40020940 08004c64 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) { 8004c64: b480 push {r7} 8004c66: b089 sub sp, #36 @ 0x24 8004c68: af00 add r7, sp, #0 8004c6a: 6078 str r0, [r7, #4] 8004c6c: 6039 str r1, [r7, #0] uint32_t position = 0x00U; 8004c6e: 2300 movs r3, #0 8004c70: 61fb str r3, [r7, #28] EXTI_Core_TypeDef *EXTI_CurrentCPU; #if defined(DUAL_CORE) && defined(CORE_CM4) EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ #else EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ 8004c72: 4b89 ldr r3, [pc, #548] @ (8004e98 ) 8004c74: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00U) 8004c76: e194 b.n 8004fa2 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); 8004c78: 683b ldr r3, [r7, #0] 8004c7a: 681a ldr r2, [r3, #0] 8004c7c: 2101 movs r1, #1 8004c7e: 69fb ldr r3, [r7, #28] 8004c80: fa01 f303 lsl.w r3, r1, r3 8004c84: 4013 ands r3, r2 8004c86: 613b str r3, [r7, #16] if (iocurrent != 0x00U) 8004c88: 693b ldr r3, [r7, #16] 8004c8a: 2b00 cmp r3, #0 8004c8c: f000 8186 beq.w 8004f9c { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8004c90: 683b ldr r3, [r7, #0] 8004c92: 685b ldr r3, [r3, #4] 8004c94: f003 0303 and.w r3, r3, #3 8004c98: 2b01 cmp r3, #1 8004c9a: d005 beq.n 8004ca8 8004c9c: 683b ldr r3, [r7, #0] 8004c9e: 685b ldr r3, [r3, #4] 8004ca0: f003 0303 and.w r3, r3, #3 8004ca4: 2b02 cmp r3, #2 8004ca6: d130 bne.n 8004d0a { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8004ca8: 687b ldr r3, [r7, #4] 8004caa: 689b ldr r3, [r3, #8] 8004cac: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 8004cae: 69fb ldr r3, [r7, #28] 8004cb0: 005b lsls r3, r3, #1 8004cb2: 2203 movs r2, #3 8004cb4: fa02 f303 lsl.w r3, r2, r3 8004cb8: 43db mvns r3, r3 8004cba: 69ba ldr r2, [r7, #24] 8004cbc: 4013 ands r3, r2 8004cbe: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 8004cc0: 683b ldr r3, [r7, #0] 8004cc2: 68da ldr r2, [r3, #12] 8004cc4: 69fb ldr r3, [r7, #28] 8004cc6: 005b lsls r3, r3, #1 8004cc8: fa02 f303 lsl.w r3, r2, r3 8004ccc: 69ba ldr r2, [r7, #24] 8004cce: 4313 orrs r3, r2 8004cd0: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 8004cd2: 687b ldr r3, [r7, #4] 8004cd4: 69ba ldr r2, [r7, #24] 8004cd6: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8004cd8: 687b ldr r3, [r7, #4] 8004cda: 685b ldr r3, [r3, #4] 8004cdc: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT0 << position) ; 8004cde: 2201 movs r2, #1 8004ce0: 69fb ldr r3, [r7, #28] 8004ce2: fa02 f303 lsl.w r3, r2, r3 8004ce6: 43db mvns r3, r3 8004ce8: 69ba ldr r2, [r7, #24] 8004cea: 4013 ands r3, r2 8004cec: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8004cee: 683b ldr r3, [r7, #0] 8004cf0: 685b ldr r3, [r3, #4] 8004cf2: 091b lsrs r3, r3, #4 8004cf4: f003 0201 and.w r2, r3, #1 8004cf8: 69fb ldr r3, [r7, #28] 8004cfa: fa02 f303 lsl.w r3, r2, r3 8004cfe: 69ba ldr r2, [r7, #24] 8004d00: 4313 orrs r3, r2 8004d02: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 8004d04: 687b ldr r3, [r7, #4] 8004d06: 69ba ldr r2, [r7, #24] 8004d08: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8004d0a: 683b ldr r3, [r7, #0] 8004d0c: 685b ldr r3, [r3, #4] 8004d0e: f003 0303 and.w r3, r3, #3 8004d12: 2b03 cmp r3, #3 8004d14: d017 beq.n 8004d46 { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8004d16: 687b ldr r3, [r7, #4] 8004d18: 68db ldr r3, [r3, #12] 8004d1a: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 8004d1c: 69fb ldr r3, [r7, #28] 8004d1e: 005b lsls r3, r3, #1 8004d20: 2203 movs r2, #3 8004d22: fa02 f303 lsl.w r3, r2, r3 8004d26: 43db mvns r3, r3 8004d28: 69ba ldr r2, [r7, #24] 8004d2a: 4013 ands r3, r2 8004d2c: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8004d2e: 683b ldr r3, [r7, #0] 8004d30: 689a ldr r2, [r3, #8] 8004d32: 69fb ldr r3, [r7, #28] 8004d34: 005b lsls r3, r3, #1 8004d36: fa02 f303 lsl.w r3, r2, r3 8004d3a: 69ba ldr r2, [r7, #24] 8004d3c: 4313 orrs r3, r2 8004d3e: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 8004d40: 687b ldr r3, [r7, #4] 8004d42: 69ba ldr r2, [r7, #24] 8004d44: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8004d46: 683b ldr r3, [r7, #0] 8004d48: 685b ldr r3, [r3, #4] 8004d4a: f003 0303 and.w r3, r3, #3 8004d4e: 2b02 cmp r3, #2 8004d50: d123 bne.n 8004d9a /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 8004d52: 69fb ldr r3, [r7, #28] 8004d54: 08da lsrs r2, r3, #3 8004d56: 687b ldr r3, [r7, #4] 8004d58: 3208 adds r2, #8 8004d5a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8004d5e: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 8004d60: 69fb ldr r3, [r7, #28] 8004d62: f003 0307 and.w r3, r3, #7 8004d66: 009b lsls r3, r3, #2 8004d68: 220f movs r2, #15 8004d6a: fa02 f303 lsl.w r3, r2, r3 8004d6e: 43db mvns r3, r3 8004d70: 69ba ldr r2, [r7, #24] 8004d72: 4013 ands r3, r2 8004d74: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 8004d76: 683b ldr r3, [r7, #0] 8004d78: 691a ldr r2, [r3, #16] 8004d7a: 69fb ldr r3, [r7, #28] 8004d7c: f003 0307 and.w r3, r3, #7 8004d80: 009b lsls r3, r3, #2 8004d82: fa02 f303 lsl.w r3, r2, r3 8004d86: 69ba ldr r2, [r7, #24] 8004d88: 4313 orrs r3, r2 8004d8a: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 8004d8c: 69fb ldr r3, [r7, #28] 8004d8e: 08da lsrs r2, r3, #3 8004d90: 687b ldr r3, [r7, #4] 8004d92: 3208 adds r2, #8 8004d94: 69b9 ldr r1, [r7, #24] 8004d96: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8004d9a: 687b ldr r3, [r7, #4] 8004d9c: 681b ldr r3, [r3, #0] 8004d9e: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); 8004da0: 69fb ldr r3, [r7, #28] 8004da2: 005b lsls r3, r3, #1 8004da4: 2203 movs r2, #3 8004da6: fa02 f303 lsl.w r3, r2, r3 8004daa: 43db mvns r3, r3 8004dac: 69ba ldr r2, [r7, #24] 8004dae: 4013 ands r3, r2 8004db0: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 8004db2: 683b ldr r3, [r7, #0] 8004db4: 685b ldr r3, [r3, #4] 8004db6: f003 0203 and.w r2, r3, #3 8004dba: 69fb ldr r3, [r7, #28] 8004dbc: 005b lsls r3, r3, #1 8004dbe: fa02 f303 lsl.w r3, r2, r3 8004dc2: 69ba ldr r2, [r7, #24] 8004dc4: 4313 orrs r3, r2 8004dc6: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 8004dc8: 687b ldr r3, [r7, #4] 8004dca: 69ba ldr r2, [r7, #24] 8004dcc: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8004dce: 683b ldr r3, [r7, #0] 8004dd0: 685b ldr r3, [r3, #4] 8004dd2: f403 3340 and.w r3, r3, #196608 @ 0x30000 8004dd6: 2b00 cmp r3, #0 8004dd8: f000 80e0 beq.w 8004f9c { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8004ddc: 4b2f ldr r3, [pc, #188] @ (8004e9c ) 8004dde: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8004de2: 4a2e ldr r2, [pc, #184] @ (8004e9c ) 8004de4: f043 0302 orr.w r3, r3, #2 8004de8: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 8004dec: 4b2b ldr r3, [pc, #172] @ (8004e9c ) 8004dee: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8004df2: f003 0302 and.w r3, r3, #2 8004df6: 60fb str r3, [r7, #12] 8004df8: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 8004dfa: 4a29 ldr r2, [pc, #164] @ (8004ea0 ) 8004dfc: 69fb ldr r3, [r7, #28] 8004dfe: 089b lsrs r3, r3, #2 8004e00: 3302 adds r3, #2 8004e02: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8004e06: 61bb str r3, [r7, #24] temp &= ~(0x0FUL << (4U * (position & 0x03U))); 8004e08: 69fb ldr r3, [r7, #28] 8004e0a: f003 0303 and.w r3, r3, #3 8004e0e: 009b lsls r3, r3, #2 8004e10: 220f movs r2, #15 8004e12: fa02 f303 lsl.w r3, r2, r3 8004e16: 43db mvns r3, r3 8004e18: 69ba ldr r2, [r7, #24] 8004e1a: 4013 ands r3, r2 8004e1c: 61bb str r3, [r7, #24] temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 8004e1e: 687b ldr r3, [r7, #4] 8004e20: 4a20 ldr r2, [pc, #128] @ (8004ea4 ) 8004e22: 4293 cmp r3, r2 8004e24: d052 beq.n 8004ecc 8004e26: 687b ldr r3, [r7, #4] 8004e28: 4a1f ldr r2, [pc, #124] @ (8004ea8 ) 8004e2a: 4293 cmp r3, r2 8004e2c: d031 beq.n 8004e92 8004e2e: 687b ldr r3, [r7, #4] 8004e30: 4a1e ldr r2, [pc, #120] @ (8004eac ) 8004e32: 4293 cmp r3, r2 8004e34: d02b beq.n 8004e8e 8004e36: 687b ldr r3, [r7, #4] 8004e38: 4a1d ldr r2, [pc, #116] @ (8004eb0 ) 8004e3a: 4293 cmp r3, r2 8004e3c: d025 beq.n 8004e8a 8004e3e: 687b ldr r3, [r7, #4] 8004e40: 4a1c ldr r2, [pc, #112] @ (8004eb4 ) 8004e42: 4293 cmp r3, r2 8004e44: d01f beq.n 8004e86 8004e46: 687b ldr r3, [r7, #4] 8004e48: 4a1b ldr r2, [pc, #108] @ (8004eb8 ) 8004e4a: 4293 cmp r3, r2 8004e4c: d019 beq.n 8004e82 8004e4e: 687b ldr r3, [r7, #4] 8004e50: 4a1a ldr r2, [pc, #104] @ (8004ebc ) 8004e52: 4293 cmp r3, r2 8004e54: d013 beq.n 8004e7e 8004e56: 687b ldr r3, [r7, #4] 8004e58: 4a19 ldr r2, [pc, #100] @ (8004ec0 ) 8004e5a: 4293 cmp r3, r2 8004e5c: d00d beq.n 8004e7a 8004e5e: 687b ldr r3, [r7, #4] 8004e60: 4a18 ldr r2, [pc, #96] @ (8004ec4 ) 8004e62: 4293 cmp r3, r2 8004e64: d007 beq.n 8004e76 8004e66: 687b ldr r3, [r7, #4] 8004e68: 4a17 ldr r2, [pc, #92] @ (8004ec8 ) 8004e6a: 4293 cmp r3, r2 8004e6c: d101 bne.n 8004e72 8004e6e: 2309 movs r3, #9 8004e70: e02d b.n 8004ece 8004e72: 230a movs r3, #10 8004e74: e02b b.n 8004ece 8004e76: 2308 movs r3, #8 8004e78: e029 b.n 8004ece 8004e7a: 2307 movs r3, #7 8004e7c: e027 b.n 8004ece 8004e7e: 2306 movs r3, #6 8004e80: e025 b.n 8004ece 8004e82: 2305 movs r3, #5 8004e84: e023 b.n 8004ece 8004e86: 2304 movs r3, #4 8004e88: e021 b.n 8004ece 8004e8a: 2303 movs r3, #3 8004e8c: e01f b.n 8004ece 8004e8e: 2302 movs r3, #2 8004e90: e01d b.n 8004ece 8004e92: 2301 movs r3, #1 8004e94: e01b b.n 8004ece 8004e96: bf00 nop 8004e98: 58000080 .word 0x58000080 8004e9c: 58024400 .word 0x58024400 8004ea0: 58000400 .word 0x58000400 8004ea4: 58020000 .word 0x58020000 8004ea8: 58020400 .word 0x58020400 8004eac: 58020800 .word 0x58020800 8004eb0: 58020c00 .word 0x58020c00 8004eb4: 58021000 .word 0x58021000 8004eb8: 58021400 .word 0x58021400 8004ebc: 58021800 .word 0x58021800 8004ec0: 58021c00 .word 0x58021c00 8004ec4: 58022000 .word 0x58022000 8004ec8: 58022400 .word 0x58022400 8004ecc: 2300 movs r3, #0 8004ece: 69fa ldr r2, [r7, #28] 8004ed0: f002 0203 and.w r2, r2, #3 8004ed4: 0092 lsls r2, r2, #2 8004ed6: 4093 lsls r3, r2 8004ed8: 69ba ldr r2, [r7, #24] 8004eda: 4313 orrs r3, r2 8004edc: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 8004ede: 4938 ldr r1, [pc, #224] @ (8004fc0 ) 8004ee0: 69fb ldr r3, [r7, #28] 8004ee2: 089b lsrs r3, r3, #2 8004ee4: 3302 adds r3, #2 8004ee6: 69ba ldr r2, [r7, #24] 8004ee8: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 8004eec: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8004ef0: 681b ldr r3, [r3, #0] 8004ef2: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8004ef4: 693b ldr r3, [r7, #16] 8004ef6: 43db mvns r3, r3 8004ef8: 69ba ldr r2, [r7, #24] 8004efa: 4013 ands r3, r2 8004efc: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 8004efe: 683b ldr r3, [r7, #0] 8004f00: 685b ldr r3, [r3, #4] 8004f02: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8004f06: 2b00 cmp r3, #0 8004f08: d003 beq.n 8004f12 { temp |= iocurrent; 8004f0a: 69ba ldr r2, [r7, #24] 8004f0c: 693b ldr r3, [r7, #16] 8004f0e: 4313 orrs r3, r2 8004f10: 61bb str r3, [r7, #24] } EXTI->RTSR1 = temp; 8004f12: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8004f16: 69bb ldr r3, [r7, #24] 8004f18: 6013 str r3, [r2, #0] temp = EXTI->FTSR1; 8004f1a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8004f1e: 685b ldr r3, [r3, #4] 8004f20: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8004f22: 693b ldr r3, [r7, #16] 8004f24: 43db mvns r3, r3 8004f26: 69ba ldr r2, [r7, #24] 8004f28: 4013 ands r3, r2 8004f2a: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8004f2c: 683b ldr r3, [r7, #0] 8004f2e: 685b ldr r3, [r3, #4] 8004f30: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8004f34: 2b00 cmp r3, #0 8004f36: d003 beq.n 8004f40 { temp |= iocurrent; 8004f38: 69ba ldr r2, [r7, #24] 8004f3a: 693b ldr r3, [r7, #16] 8004f3c: 4313 orrs r3, r2 8004f3e: 61bb str r3, [r7, #24] } EXTI->FTSR1 = temp; 8004f40: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8004f44: 69bb ldr r3, [r7, #24] 8004f46: 6053 str r3, [r2, #4] temp = EXTI_CurrentCPU->EMR1; 8004f48: 697b ldr r3, [r7, #20] 8004f4a: 685b ldr r3, [r3, #4] 8004f4c: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8004f4e: 693b ldr r3, [r7, #16] 8004f50: 43db mvns r3, r3 8004f52: 69ba ldr r2, [r7, #24] 8004f54: 4013 ands r3, r2 8004f56: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 8004f58: 683b ldr r3, [r7, #0] 8004f5a: 685b ldr r3, [r3, #4] 8004f5c: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004f60: 2b00 cmp r3, #0 8004f62: d003 beq.n 8004f6c { temp |= iocurrent; 8004f64: 69ba ldr r2, [r7, #24] 8004f66: 693b ldr r3, [r7, #16] 8004f68: 4313 orrs r3, r2 8004f6a: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->EMR1 = temp; 8004f6c: 697b ldr r3, [r7, #20] 8004f6e: 69ba ldr r2, [r7, #24] 8004f70: 605a str r2, [r3, #4] /* Clear EXTI line configuration */ temp = EXTI_CurrentCPU->IMR1; 8004f72: 697b ldr r3, [r7, #20] 8004f74: 681b ldr r3, [r3, #0] 8004f76: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8004f78: 693b ldr r3, [r7, #16] 8004f7a: 43db mvns r3, r3 8004f7c: 69ba ldr r2, [r7, #24] 8004f7e: 4013 ands r3, r2 8004f80: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8004f82: 683b ldr r3, [r7, #0] 8004f84: 685b ldr r3, [r3, #4] 8004f86: f403 3380 and.w r3, r3, #65536 @ 0x10000 8004f8a: 2b00 cmp r3, #0 8004f8c: d003 beq.n 8004f96 { temp |= iocurrent; 8004f8e: 69ba ldr r2, [r7, #24] 8004f90: 693b ldr r3, [r7, #16] 8004f92: 4313 orrs r3, r2 8004f94: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->IMR1 = temp; 8004f96: 697b ldr r3, [r7, #20] 8004f98: 69ba ldr r2, [r7, #24] 8004f9a: 601a str r2, [r3, #0] } } position++; 8004f9c: 69fb ldr r3, [r7, #28] 8004f9e: 3301 adds r3, #1 8004fa0: 61fb str r3, [r7, #28] while (((GPIO_Init->Pin) >> position) != 0x00U) 8004fa2: 683b ldr r3, [r7, #0] 8004fa4: 681a ldr r2, [r3, #0] 8004fa6: 69fb ldr r3, [r7, #28] 8004fa8: fa22 f303 lsr.w r3, r2, r3 8004fac: 2b00 cmp r3, #0 8004fae: f47f ae63 bne.w 8004c78 } } 8004fb2: bf00 nop 8004fb4: bf00 nop 8004fb6: 3724 adds r7, #36 @ 0x24 8004fb8: 46bd mov sp, r7 8004fba: f85d 7b04 ldr.w r7, [sp], #4 8004fbe: 4770 bx lr 8004fc0: 58000400 .word 0x58000400 08004fc4 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8004fc4: b480 push {r7} 8004fc6: b083 sub sp, #12 8004fc8: af00 add r7, sp, #0 8004fca: 6078 str r0, [r7, #4] 8004fcc: 460b mov r3, r1 8004fce: 807b strh r3, [r7, #2] 8004fd0: 4613 mov r3, r2 8004fd2: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8004fd4: 787b ldrb r3, [r7, #1] 8004fd6: 2b00 cmp r3, #0 8004fd8: d003 beq.n 8004fe2 { GPIOx->BSRR = GPIO_Pin; 8004fda: 887a ldrh r2, [r7, #2] 8004fdc: 687b ldr r3, [r7, #4] 8004fde: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; } } 8004fe0: e003 b.n 8004fea GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; 8004fe2: 887b ldrh r3, [r7, #2] 8004fe4: 041a lsls r2, r3, #16 8004fe6: 687b ldr r3, [r7, #4] 8004fe8: 619a str r2, [r3, #24] } 8004fea: bf00 nop 8004fec: 370c adds r7, #12 8004fee: 46bd mov sp, r7 8004ff0: f85d 7b04 ldr.w r7, [sp], #4 8004ff4: 4770 bx lr ... 08004ff8 : * process during startup. * For more details, please refer to the power control chapter in the reference manual * @retval HAL status. */ HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) { 8004ff8: b580 push {r7, lr} 8004ffa: b084 sub sp, #16 8004ffc: af00 add r7, sp, #0 8004ffe: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param (IS_PWR_SUPPLY (SupplySource)); /* Check if supply source was configured */ #if defined (PWR_FLAG_SCUEN) if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) 8005000: 4b19 ldr r3, [pc, #100] @ (8005068 ) 8005002: 68db ldr r3, [r3, #12] 8005004: f003 0304 and.w r3, r3, #4 8005008: 2b04 cmp r3, #4 800500a: d00a beq.n 8005022 #else if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) #endif /* defined (PWR_FLAG_SCUEN) */ { /* Check supply configuration */ if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) 800500c: 4b16 ldr r3, [pc, #88] @ (8005068 ) 800500e: 68db ldr r3, [r3, #12] 8005010: f003 0307 and.w r3, r3, #7 8005014: 687a ldr r2, [r7, #4] 8005016: 429a cmp r2, r3 8005018: d001 beq.n 800501e { /* Supply configuration update locked, can't apply a new supply config */ return HAL_ERROR; 800501a: 2301 movs r3, #1 800501c: e01f b.n 800505e else { /* Supply configuration update locked, but new supply configuration matches with old supply configuration : nothing to do */ return HAL_OK; 800501e: 2300 movs r3, #0 8005020: e01d b.n 800505e } } /* Set the power supply configuration */ MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); 8005022: 4b11 ldr r3, [pc, #68] @ (8005068 ) 8005024: 68db ldr r3, [r3, #12] 8005026: f023 0207 bic.w r2, r3, #7 800502a: 490f ldr r1, [pc, #60] @ (8005068 ) 800502c: 687b ldr r3, [r7, #4] 800502e: 4313 orrs r3, r2 8005030: 60cb str r3, [r1, #12] /* Get tick */ tickstart = HAL_GetTick (); 8005032: f7fc fb57 bl 80016e4 8005036: 60f8 str r0, [r7, #12] /* Wait till voltage level flag is set */ while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 8005038: e009 b.n 800504e { if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) 800503a: f7fc fb53 bl 80016e4 800503e: 4602 mov r2, r0 8005040: 68fb ldr r3, [r7, #12] 8005042: 1ad3 subs r3, r2, r3 8005044: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8005048: d901 bls.n 800504e { return HAL_ERROR; 800504a: 2301 movs r3, #1 800504c: e007 b.n 800505e while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 800504e: 4b06 ldr r3, [pc, #24] @ (8005068 ) 8005050: 685b ldr r3, [r3, #4] 8005052: f403 5300 and.w r3, r3, #8192 @ 0x2000 8005056: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800505a: d1ee bne.n 800503a } } } #endif /* defined (SMPS) */ return HAL_OK; 800505c: 2300 movs r3, #0 } 800505e: 4618 mov r0, r3 8005060: 3710 adds r7, #16 8005062: 46bd mov sp, r7 8005064: bd80 pop {r7, pc} 8005066: bf00 nop 8005068: 58024800 .word 0x58024800 0800506c : * supported by this function. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 800506c: b580 push {r7, lr} 800506e: b08c sub sp, #48 @ 0x30 8005070: af00 add r7, sp, #0 8005072: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp1_pllckcfg, temp2_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8005074: 687b ldr r3, [r7, #4] 8005076: 2b00 cmp r3, #0 8005078: d102 bne.n 8005080 { return HAL_ERROR; 800507a: 2301 movs r3, #1 800507c: f000 bc48 b.w 8005910 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8005080: 687b ldr r3, [r7, #4] 8005082: 681b ldr r3, [r3, #0] 8005084: f003 0301 and.w r3, r3, #1 8005088: 2b00 cmp r3, #0 800508a: f000 8088 beq.w 800519e { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800508e: 4b99 ldr r3, [pc, #612] @ (80052f4 ) 8005090: 691b ldr r3, [r3, #16] 8005092: f003 0338 and.w r3, r3, #56 @ 0x38 8005096: 62fb str r3, [r7, #44] @ 0x2c const uint32_t temp_pllckselr = RCC->PLLCKSELR; 8005098: 4b96 ldr r3, [pc, #600] @ (80052f4 ) 800509a: 6a9b ldr r3, [r3, #40] @ 0x28 800509c: 62bb str r3, [r7, #40] @ 0x28 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) 800509e: 6afb ldr r3, [r7, #44] @ 0x2c 80050a0: 2b10 cmp r3, #16 80050a2: d007 beq.n 80050b4 80050a4: 6afb ldr r3, [r7, #44] @ 0x2c 80050a6: 2b18 cmp r3, #24 80050a8: d111 bne.n 80050ce 80050aa: 6abb ldr r3, [r7, #40] @ 0x28 80050ac: f003 0303 and.w r3, r3, #3 80050b0: 2b02 cmp r3, #2 80050b2: d10c bne.n 80050ce { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80050b4: 4b8f ldr r3, [pc, #572] @ (80052f4 ) 80050b6: 681b ldr r3, [r3, #0] 80050b8: f403 3300 and.w r3, r3, #131072 @ 0x20000 80050bc: 2b00 cmp r3, #0 80050be: d06d beq.n 800519c 80050c0: 687b ldr r3, [r7, #4] 80050c2: 685b ldr r3, [r3, #4] 80050c4: 2b00 cmp r3, #0 80050c6: d169 bne.n 800519c { return HAL_ERROR; 80050c8: 2301 movs r3, #1 80050ca: f000 bc21 b.w 8005910 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80050ce: 687b ldr r3, [r7, #4] 80050d0: 685b ldr r3, [r3, #4] 80050d2: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80050d6: d106 bne.n 80050e6 80050d8: 4b86 ldr r3, [pc, #536] @ (80052f4 ) 80050da: 681b ldr r3, [r3, #0] 80050dc: 4a85 ldr r2, [pc, #532] @ (80052f4 ) 80050de: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80050e2: 6013 str r3, [r2, #0] 80050e4: e02e b.n 8005144 80050e6: 687b ldr r3, [r7, #4] 80050e8: 685b ldr r3, [r3, #4] 80050ea: 2b00 cmp r3, #0 80050ec: d10c bne.n 8005108 80050ee: 4b81 ldr r3, [pc, #516] @ (80052f4 ) 80050f0: 681b ldr r3, [r3, #0] 80050f2: 4a80 ldr r2, [pc, #512] @ (80052f4 ) 80050f4: f423 3380 bic.w r3, r3, #65536 @ 0x10000 80050f8: 6013 str r3, [r2, #0] 80050fa: 4b7e ldr r3, [pc, #504] @ (80052f4 ) 80050fc: 681b ldr r3, [r3, #0] 80050fe: 4a7d ldr r2, [pc, #500] @ (80052f4 ) 8005100: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8005104: 6013 str r3, [r2, #0] 8005106: e01d b.n 8005144 8005108: 687b ldr r3, [r7, #4] 800510a: 685b ldr r3, [r3, #4] 800510c: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8005110: d10c bne.n 800512c 8005112: 4b78 ldr r3, [pc, #480] @ (80052f4 ) 8005114: 681b ldr r3, [r3, #0] 8005116: 4a77 ldr r2, [pc, #476] @ (80052f4 ) 8005118: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800511c: 6013 str r3, [r2, #0] 800511e: 4b75 ldr r3, [pc, #468] @ (80052f4 ) 8005120: 681b ldr r3, [r3, #0] 8005122: 4a74 ldr r2, [pc, #464] @ (80052f4 ) 8005124: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8005128: 6013 str r3, [r2, #0] 800512a: e00b b.n 8005144 800512c: 4b71 ldr r3, [pc, #452] @ (80052f4 ) 800512e: 681b ldr r3, [r3, #0] 8005130: 4a70 ldr r2, [pc, #448] @ (80052f4 ) 8005132: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8005136: 6013 str r3, [r2, #0] 8005138: 4b6e ldr r3, [pc, #440] @ (80052f4 ) 800513a: 681b ldr r3, [r3, #0] 800513c: 4a6d ldr r2, [pc, #436] @ (80052f4 ) 800513e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8005142: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8005144: 687b ldr r3, [r7, #4] 8005146: 685b ldr r3, [r3, #4] 8005148: 2b00 cmp r3, #0 800514a: d013 beq.n 8005174 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800514c: f7fc faca bl 80016e4 8005150: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 8005152: e008 b.n 8005166 { if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8005154: f7fc fac6 bl 80016e4 8005158: 4602 mov r2, r0 800515a: 6a7b ldr r3, [r7, #36] @ 0x24 800515c: 1ad3 subs r3, r2, r3 800515e: 2b64 cmp r3, #100 @ 0x64 8005160: d901 bls.n 8005166 { return HAL_TIMEOUT; 8005162: 2303 movs r3, #3 8005164: e3d4 b.n 8005910 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 8005166: 4b63 ldr r3, [pc, #396] @ (80052f4 ) 8005168: 681b ldr r3, [r3, #0] 800516a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800516e: 2b00 cmp r3, #0 8005170: d0f0 beq.n 8005154 8005172: e014 b.n 800519e } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005174: f7fc fab6 bl 80016e4 8005178: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 800517a: e008 b.n 800518e { if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800517c: f7fc fab2 bl 80016e4 8005180: 4602 mov r2, r0 8005182: 6a7b ldr r3, [r7, #36] @ 0x24 8005184: 1ad3 subs r3, r2, r3 8005186: 2b64 cmp r3, #100 @ 0x64 8005188: d901 bls.n 800518e { return HAL_TIMEOUT; 800518a: 2303 movs r3, #3 800518c: e3c0 b.n 8005910 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 800518e: 4b59 ldr r3, [pc, #356] @ (80052f4 ) 8005190: 681b ldr r3, [r3, #0] 8005192: f403 3300 and.w r3, r3, #131072 @ 0x20000 8005196: 2b00 cmp r3, #0 8005198: d1f0 bne.n 800517c 800519a: e000 b.n 800519e if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800519c: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800519e: 687b ldr r3, [r7, #4] 80051a0: 681b ldr r3, [r3, #0] 80051a2: f003 0302 and.w r3, r3, #2 80051a6: 2b00 cmp r3, #0 80051a8: f000 80ca beq.w 8005340 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* When the HSI is used as system clock it will not be disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 80051ac: 4b51 ldr r3, [pc, #324] @ (80052f4 ) 80051ae: 691b ldr r3, [r3, #16] 80051b0: f003 0338 and.w r3, r3, #56 @ 0x38 80051b4: 623b str r3, [r7, #32] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 80051b6: 4b4f ldr r3, [pc, #316] @ (80052f4 ) 80051b8: 6a9b ldr r3, [r3, #40] @ 0x28 80051ba: 61fb str r3, [r7, #28] if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) 80051bc: 6a3b ldr r3, [r7, #32] 80051be: 2b00 cmp r3, #0 80051c0: d007 beq.n 80051d2 80051c2: 6a3b ldr r3, [r7, #32] 80051c4: 2b18 cmp r3, #24 80051c6: d156 bne.n 8005276 80051c8: 69fb ldr r3, [r7, #28] 80051ca: f003 0303 and.w r3, r3, #3 80051ce: 2b00 cmp r3, #0 80051d0: d151 bne.n 8005276 { /* When HSI is used as system clock it will not be disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 80051d2: 4b48 ldr r3, [pc, #288] @ (80052f4 ) 80051d4: 681b ldr r3, [r3, #0] 80051d6: f003 0304 and.w r3, r3, #4 80051da: 2b00 cmp r3, #0 80051dc: d005 beq.n 80051ea 80051de: 687b ldr r3, [r7, #4] 80051e0: 68db ldr r3, [r3, #12] 80051e2: 2b00 cmp r3, #0 80051e4: d101 bne.n 80051ea { return HAL_ERROR; 80051e6: 2301 movs r3, #1 80051e8: e392 b.n 8005910 } /* Otherwise, only HSI division and calibration are allowed */ else { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 80051ea: 4b42 ldr r3, [pc, #264] @ (80052f4 ) 80051ec: 681b ldr r3, [r3, #0] 80051ee: f023 0219 bic.w r2, r3, #25 80051f2: 687b ldr r3, [r7, #4] 80051f4: 68db ldr r3, [r3, #12] 80051f6: 493f ldr r1, [pc, #252] @ (80052f4 ) 80051f8: 4313 orrs r3, r2 80051fa: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80051fc: f7fc fa72 bl 80016e4 8005200: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8005202: e008 b.n 8005216 { if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8005204: f7fc fa6e bl 80016e4 8005208: 4602 mov r2, r0 800520a: 6a7b ldr r3, [r7, #36] @ 0x24 800520c: 1ad3 subs r3, r2, r3 800520e: 2b02 cmp r3, #2 8005210: d901 bls.n 8005216 { return HAL_TIMEOUT; 8005212: 2303 movs r3, #3 8005214: e37c b.n 8005910 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8005216: 4b37 ldr r3, [pc, #220] @ (80052f4 ) 8005218: 681b ldr r3, [r3, #0] 800521a: f003 0304 and.w r3, r3, #4 800521e: 2b00 cmp r3, #0 8005220: d0f0 beq.n 8005204 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8005222: f7fc fa6b bl 80016fc 8005226: 4603 mov r3, r0 8005228: f241 0203 movw r2, #4099 @ 0x1003 800522c: 4293 cmp r3, r2 800522e: d817 bhi.n 8005260 8005230: 687b ldr r3, [r7, #4] 8005232: 691b ldr r3, [r3, #16] 8005234: 2b40 cmp r3, #64 @ 0x40 8005236: d108 bne.n 800524a 8005238: 4b2e ldr r3, [pc, #184] @ (80052f4 ) 800523a: 685b ldr r3, [r3, #4] 800523c: f423 337c bic.w r3, r3, #258048 @ 0x3f000 8005240: 4a2c ldr r2, [pc, #176] @ (80052f4 ) 8005242: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8005246: 6053 str r3, [r2, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8005248: e07a b.n 8005340 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800524a: 4b2a ldr r3, [pc, #168] @ (80052f4 ) 800524c: 685b ldr r3, [r3, #4] 800524e: f423 327c bic.w r2, r3, #258048 @ 0x3f000 8005252: 687b ldr r3, [r7, #4] 8005254: 691b ldr r3, [r3, #16] 8005256: 031b lsls r3, r3, #12 8005258: 4926 ldr r1, [pc, #152] @ (80052f4 ) 800525a: 4313 orrs r3, r2 800525c: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800525e: e06f b.n 8005340 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8005260: 4b24 ldr r3, [pc, #144] @ (80052f4 ) 8005262: 685b ldr r3, [r3, #4] 8005264: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 8005268: 687b ldr r3, [r7, #4] 800526a: 691b ldr r3, [r3, #16] 800526c: 061b lsls r3, r3, #24 800526e: 4921 ldr r1, [pc, #132] @ (80052f4 ) 8005270: 4313 orrs r3, r2 8005272: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8005274: e064 b.n 8005340 } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 8005276: 687b ldr r3, [r7, #4] 8005278: 68db ldr r3, [r3, #12] 800527a: 2b00 cmp r3, #0 800527c: d047 beq.n 800530e { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 800527e: 4b1d ldr r3, [pc, #116] @ (80052f4 ) 8005280: 681b ldr r3, [r3, #0] 8005282: f023 0219 bic.w r2, r3, #25 8005286: 687b ldr r3, [r7, #4] 8005288: 68db ldr r3, [r3, #12] 800528a: 491a ldr r1, [pc, #104] @ (80052f4 ) 800528c: 4313 orrs r3, r2 800528e: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005290: f7fc fa28 bl 80016e4 8005294: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8005296: e008 b.n 80052aa { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8005298: f7fc fa24 bl 80016e4 800529c: 4602 mov r2, r0 800529e: 6a7b ldr r3, [r7, #36] @ 0x24 80052a0: 1ad3 subs r3, r2, r3 80052a2: 2b02 cmp r3, #2 80052a4: d901 bls.n 80052aa { return HAL_TIMEOUT; 80052a6: 2303 movs r3, #3 80052a8: e332 b.n 8005910 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 80052aa: 4b12 ldr r3, [pc, #72] @ (80052f4 ) 80052ac: 681b ldr r3, [r3, #0] 80052ae: f003 0304 and.w r3, r3, #4 80052b2: 2b00 cmp r3, #0 80052b4: d0f0 beq.n 8005298 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80052b6: f7fc fa21 bl 80016fc 80052ba: 4603 mov r3, r0 80052bc: f241 0203 movw r2, #4099 @ 0x1003 80052c0: 4293 cmp r3, r2 80052c2: d819 bhi.n 80052f8 80052c4: 687b ldr r3, [r7, #4] 80052c6: 691b ldr r3, [r3, #16] 80052c8: 2b40 cmp r3, #64 @ 0x40 80052ca: d108 bne.n 80052de 80052cc: 4b09 ldr r3, [pc, #36] @ (80052f4 ) 80052ce: 685b ldr r3, [r3, #4] 80052d0: f423 337c bic.w r3, r3, #258048 @ 0x3f000 80052d4: 4a07 ldr r2, [pc, #28] @ (80052f4 ) 80052d6: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80052da: 6053 str r3, [r2, #4] 80052dc: e030 b.n 8005340 80052de: 4b05 ldr r3, [pc, #20] @ (80052f4 ) 80052e0: 685b ldr r3, [r3, #4] 80052e2: f423 327c bic.w r2, r3, #258048 @ 0x3f000 80052e6: 687b ldr r3, [r7, #4] 80052e8: 691b ldr r3, [r3, #16] 80052ea: 031b lsls r3, r3, #12 80052ec: 4901 ldr r1, [pc, #4] @ (80052f4 ) 80052ee: 4313 orrs r3, r2 80052f0: 604b str r3, [r1, #4] 80052f2: e025 b.n 8005340 80052f4: 58024400 .word 0x58024400 80052f8: 4b9a ldr r3, [pc, #616] @ (8005564 ) 80052fa: 685b ldr r3, [r3, #4] 80052fc: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 8005300: 687b ldr r3, [r7, #4] 8005302: 691b ldr r3, [r3, #16] 8005304: 061b lsls r3, r3, #24 8005306: 4997 ldr r1, [pc, #604] @ (8005564 ) 8005308: 4313 orrs r3, r2 800530a: 604b str r3, [r1, #4] 800530c: e018 b.n 8005340 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 800530e: 4b95 ldr r3, [pc, #596] @ (8005564 ) 8005310: 681b ldr r3, [r3, #0] 8005312: 4a94 ldr r2, [pc, #592] @ (8005564 ) 8005314: f023 0301 bic.w r3, r3, #1 8005318: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800531a: f7fc f9e3 bl 80016e4 800531e: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 8005320: e008 b.n 8005334 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8005322: f7fc f9df bl 80016e4 8005326: 4602 mov r2, r0 8005328: 6a7b ldr r3, [r7, #36] @ 0x24 800532a: 1ad3 subs r3, r2, r3 800532c: 2b02 cmp r3, #2 800532e: d901 bls.n 8005334 { return HAL_TIMEOUT; 8005330: 2303 movs r3, #3 8005332: e2ed b.n 8005910 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 8005334: 4b8b ldr r3, [pc, #556] @ (8005564 ) 8005336: 681b ldr r3, [r3, #0] 8005338: f003 0304 and.w r3, r3, #4 800533c: 2b00 cmp r3, #0 800533e: d1f0 bne.n 8005322 } } } } /*----------------------------- CSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) 8005340: 687b ldr r3, [r7, #4] 8005342: 681b ldr r3, [r3, #0] 8005344: f003 0310 and.w r3, r3, #16 8005348: 2b00 cmp r3, #0 800534a: f000 80a9 beq.w 80054a0 /* Check the parameters */ assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue)); /* When the CSI is used as system clock it will not disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800534e: 4b85 ldr r3, [pc, #532] @ (8005564 ) 8005350: 691b ldr r3, [r3, #16] 8005352: f003 0338 and.w r3, r3, #56 @ 0x38 8005356: 61bb str r3, [r7, #24] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 8005358: 4b82 ldr r3, [pc, #520] @ (8005564 ) 800535a: 6a9b ldr r3, [r3, #40] @ 0x28 800535c: 617b str r3, [r7, #20] if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) 800535e: 69bb ldr r3, [r7, #24] 8005360: 2b08 cmp r3, #8 8005362: d007 beq.n 8005374 8005364: 69bb ldr r3, [r7, #24] 8005366: 2b18 cmp r3, #24 8005368: d13a bne.n 80053e0 800536a: 697b ldr r3, [r7, #20] 800536c: f003 0303 and.w r3, r3, #3 8005370: 2b01 cmp r3, #1 8005372: d135 bne.n 80053e0 { /* When CSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 8005374: 4b7b ldr r3, [pc, #492] @ (8005564 ) 8005376: 681b ldr r3, [r3, #0] 8005378: f403 7380 and.w r3, r3, #256 @ 0x100 800537c: 2b00 cmp r3, #0 800537e: d005 beq.n 800538c 8005380: 687b ldr r3, [r7, #4] 8005382: 69db ldr r3, [r3, #28] 8005384: 2b80 cmp r3, #128 @ 0x80 8005386: d001 beq.n 800538c { return HAL_ERROR; 8005388: 2301 movs r3, #1 800538a: e2c1 b.n 8005910 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800538c: f7fc f9b6 bl 80016fc 8005390: 4603 mov r3, r0 8005392: f241 0203 movw r2, #4099 @ 0x1003 8005396: 4293 cmp r3, r2 8005398: d817 bhi.n 80053ca 800539a: 687b ldr r3, [r7, #4] 800539c: 6a1b ldr r3, [r3, #32] 800539e: 2b20 cmp r3, #32 80053a0: d108 bne.n 80053b4 80053a2: 4b70 ldr r3, [pc, #448] @ (8005564 ) 80053a4: 685b ldr r3, [r3, #4] 80053a6: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000 80053aa: 4a6e ldr r2, [pc, #440] @ (8005564 ) 80053ac: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 80053b0: 6053 str r3, [r2, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 80053b2: e075 b.n 80054a0 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 80053b4: 4b6b ldr r3, [pc, #428] @ (8005564 ) 80053b6: 685b ldr r3, [r3, #4] 80053b8: f023 42f8 bic.w r2, r3, #2080374784 @ 0x7c000000 80053bc: 687b ldr r3, [r7, #4] 80053be: 6a1b ldr r3, [r3, #32] 80053c0: 069b lsls r3, r3, #26 80053c2: 4968 ldr r1, [pc, #416] @ (8005564 ) 80053c4: 4313 orrs r3, r2 80053c6: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 80053c8: e06a b.n 80054a0 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 80053ca: 4b66 ldr r3, [pc, #408] @ (8005564 ) 80053cc: 68db ldr r3, [r3, #12] 80053ce: f023 527c bic.w r2, r3, #1056964608 @ 0x3f000000 80053d2: 687b ldr r3, [r7, #4] 80053d4: 6a1b ldr r3, [r3, #32] 80053d6: 061b lsls r3, r3, #24 80053d8: 4962 ldr r1, [pc, #392] @ (8005564 ) 80053da: 4313 orrs r3, r2 80053dc: 60cb str r3, [r1, #12] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 80053de: e05f b.n 80054a0 } } else { /* Check the CSI State */ if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF) 80053e0: 687b ldr r3, [r7, #4] 80053e2: 69db ldr r3, [r3, #28] 80053e4: 2b00 cmp r3, #0 80053e6: d042 beq.n 800546e { /* Enable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_ENABLE(); 80053e8: 4b5e ldr r3, [pc, #376] @ (8005564 ) 80053ea: 681b ldr r3, [r3, #0] 80053ec: 4a5d ldr r2, [pc, #372] @ (8005564 ) 80053ee: f043 0380 orr.w r3, r3, #128 @ 0x80 80053f2: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80053f4: f7fc f976 bl 80016e4 80053f8: 6278 str r0, [r7, #36] @ 0x24 /* Wait till CSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 80053fa: e008 b.n 800540e { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 80053fc: f7fc f972 bl 80016e4 8005400: 4602 mov r2, r0 8005402: 6a7b ldr r3, [r7, #36] @ 0x24 8005404: 1ad3 subs r3, r2, r3 8005406: 2b02 cmp r3, #2 8005408: d901 bls.n 800540e { return HAL_TIMEOUT; 800540a: 2303 movs r3, #3 800540c: e280 b.n 8005910 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800540e: 4b55 ldr r3, [pc, #340] @ (8005564 ) 8005410: 681b ldr r3, [r3, #0] 8005412: f403 7380 and.w r3, r3, #256 @ 0x100 8005416: 2b00 cmp r3, #0 8005418: d0f0 beq.n 80053fc } } /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800541a: f7fc f96f bl 80016fc 800541e: 4603 mov r3, r0 8005420: f241 0203 movw r2, #4099 @ 0x1003 8005424: 4293 cmp r3, r2 8005426: d817 bhi.n 8005458 8005428: 687b ldr r3, [r7, #4] 800542a: 6a1b ldr r3, [r3, #32] 800542c: 2b20 cmp r3, #32 800542e: d108 bne.n 8005442 8005430: 4b4c ldr r3, [pc, #304] @ (8005564 ) 8005432: 685b ldr r3, [r3, #4] 8005434: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000 8005438: 4a4a ldr r2, [pc, #296] @ (8005564 ) 800543a: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800543e: 6053 str r3, [r2, #4] 8005440: e02e b.n 80054a0 8005442: 4b48 ldr r3, [pc, #288] @ (8005564 ) 8005444: 685b ldr r3, [r3, #4] 8005446: f023 42f8 bic.w r2, r3, #2080374784 @ 0x7c000000 800544a: 687b ldr r3, [r7, #4] 800544c: 6a1b ldr r3, [r3, #32] 800544e: 069b lsls r3, r3, #26 8005450: 4944 ldr r1, [pc, #272] @ (8005564 ) 8005452: 4313 orrs r3, r2 8005454: 604b str r3, [r1, #4] 8005456: e023 b.n 80054a0 8005458: 4b42 ldr r3, [pc, #264] @ (8005564 ) 800545a: 68db ldr r3, [r3, #12] 800545c: f023 527c bic.w r2, r3, #1056964608 @ 0x3f000000 8005460: 687b ldr r3, [r7, #4] 8005462: 6a1b ldr r3, [r3, #32] 8005464: 061b lsls r3, r3, #24 8005466: 493f ldr r1, [pc, #252] @ (8005564 ) 8005468: 4313 orrs r3, r2 800546a: 60cb str r3, [r1, #12] 800546c: e018 b.n 80054a0 } else { /* Disable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_DISABLE(); 800546e: 4b3d ldr r3, [pc, #244] @ (8005564 ) 8005470: 681b ldr r3, [r3, #0] 8005472: 4a3c ldr r2, [pc, #240] @ (8005564 ) 8005474: f023 0380 bic.w r3, r3, #128 @ 0x80 8005478: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800547a: f7fc f933 bl 80016e4 800547e: 6278 str r0, [r7, #36] @ 0x24 /* Wait till CSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 8005480: e008 b.n 8005494 { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 8005482: f7fc f92f bl 80016e4 8005486: 4602 mov r2, r0 8005488: 6a7b ldr r3, [r7, #36] @ 0x24 800548a: 1ad3 subs r3, r2, r3 800548c: 2b02 cmp r3, #2 800548e: d901 bls.n 8005494 { return HAL_TIMEOUT; 8005490: 2303 movs r3, #3 8005492: e23d b.n 8005910 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 8005494: 4b33 ldr r3, [pc, #204] @ (8005564 ) 8005496: 681b ldr r3, [r3, #0] 8005498: f403 7380 and.w r3, r3, #256 @ 0x100 800549c: 2b00 cmp r3, #0 800549e: d1f0 bne.n 8005482 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 80054a0: 687b ldr r3, [r7, #4] 80054a2: 681b ldr r3, [r3, #0] 80054a4: f003 0308 and.w r3, r3, #8 80054a8: 2b00 cmp r3, #0 80054aa: d036 beq.n 800551a { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 80054ac: 687b ldr r3, [r7, #4] 80054ae: 695b ldr r3, [r3, #20] 80054b0: 2b00 cmp r3, #0 80054b2: d019 beq.n 80054e8 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 80054b4: 4b2b ldr r3, [pc, #172] @ (8005564 ) 80054b6: 6f5b ldr r3, [r3, #116] @ 0x74 80054b8: 4a2a ldr r2, [pc, #168] @ (8005564 ) 80054ba: f043 0301 orr.w r3, r3, #1 80054be: 6753 str r3, [r2, #116] @ 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 80054c0: f7fc f910 bl 80016e4 80054c4: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 80054c6: e008 b.n 80054da { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80054c8: f7fc f90c bl 80016e4 80054cc: 4602 mov r2, r0 80054ce: 6a7b ldr r3, [r7, #36] @ 0x24 80054d0: 1ad3 subs r3, r2, r3 80054d2: 2b02 cmp r3, #2 80054d4: d901 bls.n 80054da { return HAL_TIMEOUT; 80054d6: 2303 movs r3, #3 80054d8: e21a b.n 8005910 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 80054da: 4b22 ldr r3, [pc, #136] @ (8005564 ) 80054dc: 6f5b ldr r3, [r3, #116] @ 0x74 80054de: f003 0302 and.w r3, r3, #2 80054e2: 2b00 cmp r3, #0 80054e4: d0f0 beq.n 80054c8 80054e6: e018 b.n 800551a } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 80054e8: 4b1e ldr r3, [pc, #120] @ (8005564 ) 80054ea: 6f5b ldr r3, [r3, #116] @ 0x74 80054ec: 4a1d ldr r2, [pc, #116] @ (8005564 ) 80054ee: f023 0301 bic.w r3, r3, #1 80054f2: 6753 str r3, [r2, #116] @ 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 80054f4: f7fc f8f6 bl 80016e4 80054f8: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 80054fa: e008 b.n 800550e { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80054fc: f7fc f8f2 bl 80016e4 8005500: 4602 mov r2, r0 8005502: 6a7b ldr r3, [r7, #36] @ 0x24 8005504: 1ad3 subs r3, r2, r3 8005506: 2b02 cmp r3, #2 8005508: d901 bls.n 800550e { return HAL_TIMEOUT; 800550a: 2303 movs r3, #3 800550c: e200 b.n 8005910 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 800550e: 4b15 ldr r3, [pc, #84] @ (8005564 ) 8005510: 6f5b ldr r3, [r3, #116] @ 0x74 8005512: f003 0302 and.w r3, r3, #2 8005516: 2b00 cmp r3, #0 8005518: d1f0 bne.n 80054fc } } } /*------------------------------ HSI48 Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 800551a: 687b ldr r3, [r7, #4] 800551c: 681b ldr r3, [r3, #0] 800551e: f003 0320 and.w r3, r3, #32 8005522: 2b00 cmp r3, #0 8005524: d039 beq.n 800559a { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF) 8005526: 687b ldr r3, [r7, #4] 8005528: 699b ldr r3, [r3, #24] 800552a: 2b00 cmp r3, #0 800552c: d01c beq.n 8005568 { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 800552e: 4b0d ldr r3, [pc, #52] @ (8005564 ) 8005530: 681b ldr r3, [r3, #0] 8005532: 4a0c ldr r2, [pc, #48] @ (8005564 ) 8005534: f443 5380 orr.w r3, r3, #4096 @ 0x1000 8005538: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 800553a: f7fc f8d3 bl 80016e4 800553e: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI48 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 8005540: e008 b.n 8005554 { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 8005542: f7fc f8cf bl 80016e4 8005546: 4602 mov r2, r0 8005548: 6a7b ldr r3, [r7, #36] @ 0x24 800554a: 1ad3 subs r3, r2, r3 800554c: 2b02 cmp r3, #2 800554e: d901 bls.n 8005554 { return HAL_TIMEOUT; 8005550: 2303 movs r3, #3 8005552: e1dd b.n 8005910 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 8005554: 4b03 ldr r3, [pc, #12] @ (8005564 ) 8005556: 681b ldr r3, [r3, #0] 8005558: f403 5300 and.w r3, r3, #8192 @ 0x2000 800555c: 2b00 cmp r3, #0 800555e: d0f0 beq.n 8005542 8005560: e01b b.n 800559a 8005562: bf00 nop 8005564: 58024400 .word 0x58024400 } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 8005568: 4b9b ldr r3, [pc, #620] @ (80057d8 ) 800556a: 681b ldr r3, [r3, #0] 800556c: 4a9a ldr r2, [pc, #616] @ (80057d8 ) 800556e: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8005572: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 8005574: f7fc f8b6 bl 80016e4 8005578: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI48 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 800557a: e008 b.n 800558e { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800557c: f7fc f8b2 bl 80016e4 8005580: 4602 mov r2, r0 8005582: 6a7b ldr r3, [r7, #36] @ 0x24 8005584: 1ad3 subs r3, r2, r3 8005586: 2b02 cmp r3, #2 8005588: d901 bls.n 800558e { return HAL_TIMEOUT; 800558a: 2303 movs r3, #3 800558c: e1c0 b.n 8005910 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 800558e: 4b92 ldr r3, [pc, #584] @ (80057d8 ) 8005590: 681b ldr r3, [r3, #0] 8005592: f403 5300 and.w r3, r3, #8192 @ 0x2000 8005596: 2b00 cmp r3, #0 8005598: d1f0 bne.n 800557c } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800559a: 687b ldr r3, [r7, #4] 800559c: 681b ldr r3, [r3, #0] 800559e: f003 0304 and.w r3, r3, #4 80055a2: 2b00 cmp r3, #0 80055a4: f000 8081 beq.w 80056aa { /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; 80055a8: 4b8c ldr r3, [pc, #560] @ (80057dc ) 80055aa: 681b ldr r3, [r3, #0] 80055ac: 4a8b ldr r2, [pc, #556] @ (80057dc ) 80055ae: f443 7380 orr.w r3, r3, #256 @ 0x100 80055b2: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80055b4: f7fc f896 bl 80016e4 80055b8: 6278 str r0, [r7, #36] @ 0x24 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 80055ba: e008 b.n 80055ce { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80055bc: f7fc f892 bl 80016e4 80055c0: 4602 mov r2, r0 80055c2: 6a7b ldr r3, [r7, #36] @ 0x24 80055c4: 1ad3 subs r3, r2, r3 80055c6: 2b64 cmp r3, #100 @ 0x64 80055c8: d901 bls.n 80055ce { return HAL_TIMEOUT; 80055ca: 2303 movs r3, #3 80055cc: e1a0 b.n 8005910 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 80055ce: 4b83 ldr r3, [pc, #524] @ (80057dc ) 80055d0: 681b ldr r3, [r3, #0] 80055d2: f403 7380 and.w r3, r3, #256 @ 0x100 80055d6: 2b00 cmp r3, #0 80055d8: d0f0 beq.n 80055bc } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 80055da: 687b ldr r3, [r7, #4] 80055dc: 689b ldr r3, [r3, #8] 80055de: 2b01 cmp r3, #1 80055e0: d106 bne.n 80055f0 80055e2: 4b7d ldr r3, [pc, #500] @ (80057d8 ) 80055e4: 6f1b ldr r3, [r3, #112] @ 0x70 80055e6: 4a7c ldr r2, [pc, #496] @ (80057d8 ) 80055e8: f043 0301 orr.w r3, r3, #1 80055ec: 6713 str r3, [r2, #112] @ 0x70 80055ee: e02d b.n 800564c 80055f0: 687b ldr r3, [r7, #4] 80055f2: 689b ldr r3, [r3, #8] 80055f4: 2b00 cmp r3, #0 80055f6: d10c bne.n 8005612 80055f8: 4b77 ldr r3, [pc, #476] @ (80057d8 ) 80055fa: 6f1b ldr r3, [r3, #112] @ 0x70 80055fc: 4a76 ldr r2, [pc, #472] @ (80057d8 ) 80055fe: f023 0301 bic.w r3, r3, #1 8005602: 6713 str r3, [r2, #112] @ 0x70 8005604: 4b74 ldr r3, [pc, #464] @ (80057d8 ) 8005606: 6f1b ldr r3, [r3, #112] @ 0x70 8005608: 4a73 ldr r2, [pc, #460] @ (80057d8 ) 800560a: f023 0304 bic.w r3, r3, #4 800560e: 6713 str r3, [r2, #112] @ 0x70 8005610: e01c b.n 800564c 8005612: 687b ldr r3, [r7, #4] 8005614: 689b ldr r3, [r3, #8] 8005616: 2b05 cmp r3, #5 8005618: d10c bne.n 8005634 800561a: 4b6f ldr r3, [pc, #444] @ (80057d8 ) 800561c: 6f1b ldr r3, [r3, #112] @ 0x70 800561e: 4a6e ldr r2, [pc, #440] @ (80057d8 ) 8005620: f043 0304 orr.w r3, r3, #4 8005624: 6713 str r3, [r2, #112] @ 0x70 8005626: 4b6c ldr r3, [pc, #432] @ (80057d8 ) 8005628: 6f1b ldr r3, [r3, #112] @ 0x70 800562a: 4a6b ldr r2, [pc, #428] @ (80057d8 ) 800562c: f043 0301 orr.w r3, r3, #1 8005630: 6713 str r3, [r2, #112] @ 0x70 8005632: e00b b.n 800564c 8005634: 4b68 ldr r3, [pc, #416] @ (80057d8 ) 8005636: 6f1b ldr r3, [r3, #112] @ 0x70 8005638: 4a67 ldr r2, [pc, #412] @ (80057d8 ) 800563a: f023 0301 bic.w r3, r3, #1 800563e: 6713 str r3, [r2, #112] @ 0x70 8005640: 4b65 ldr r3, [pc, #404] @ (80057d8 ) 8005642: 6f1b ldr r3, [r3, #112] @ 0x70 8005644: 4a64 ldr r2, [pc, #400] @ (80057d8 ) 8005646: f023 0304 bic.w r3, r3, #4 800564a: 6713 str r3, [r2, #112] @ 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 800564c: 687b ldr r3, [r7, #4] 800564e: 689b ldr r3, [r3, #8] 8005650: 2b00 cmp r3, #0 8005652: d015 beq.n 8005680 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005654: f7fc f846 bl 80016e4 8005658: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800565a: e00a b.n 8005672 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800565c: f7fc f842 bl 80016e4 8005660: 4602 mov r2, r0 8005662: 6a7b ldr r3, [r7, #36] @ 0x24 8005664: 1ad3 subs r3, r2, r3 8005666: f241 3288 movw r2, #5000 @ 0x1388 800566a: 4293 cmp r3, r2 800566c: d901 bls.n 8005672 { return HAL_TIMEOUT; 800566e: 2303 movs r3, #3 8005670: e14e b.n 8005910 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8005672: 4b59 ldr r3, [pc, #356] @ (80057d8 ) 8005674: 6f1b ldr r3, [r3, #112] @ 0x70 8005676: f003 0302 and.w r3, r3, #2 800567a: 2b00 cmp r3, #0 800567c: d0ee beq.n 800565c 800567e: e014 b.n 80056aa } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005680: f7fc f830 bl 80016e4 8005684: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 8005686: e00a b.n 800569e { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8005688: f7fc f82c bl 80016e4 800568c: 4602 mov r2, r0 800568e: 6a7b ldr r3, [r7, #36] @ 0x24 8005690: 1ad3 subs r3, r2, r3 8005692: f241 3288 movw r2, #5000 @ 0x1388 8005696: 4293 cmp r3, r2 8005698: d901 bls.n 800569e { return HAL_TIMEOUT; 800569a: 2303 movs r3, #3 800569c: e138 b.n 8005910 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 800569e: 4b4e ldr r3, [pc, #312] @ (80057d8 ) 80056a0: 6f1b ldr r3, [r3, #112] @ 0x70 80056a2: f003 0302 and.w r3, r3, #2 80056a6: 2b00 cmp r3, #0 80056a8: d1ee bne.n 8005688 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 80056aa: 687b ldr r3, [r7, #4] 80056ac: 6a5b ldr r3, [r3, #36] @ 0x24 80056ae: 2b00 cmp r3, #0 80056b0: f000 812d beq.w 800590e { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) 80056b4: 4b48 ldr r3, [pc, #288] @ (80057d8 ) 80056b6: 691b ldr r3, [r3, #16] 80056b8: f003 0338 and.w r3, r3, #56 @ 0x38 80056bc: 2b18 cmp r3, #24 80056be: f000 80bd beq.w 800583c { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 80056c2: 687b ldr r3, [r7, #4] 80056c4: 6a5b ldr r3, [r3, #36] @ 0x24 80056c6: 2b02 cmp r3, #2 80056c8: f040 809e bne.w 8005808 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80056cc: 4b42 ldr r3, [pc, #264] @ (80057d8 ) 80056ce: 681b ldr r3, [r3, #0] 80056d0: 4a41 ldr r2, [pc, #260] @ (80057d8 ) 80056d2: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 80056d6: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80056d8: f7fc f804 bl 80016e4 80056dc: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 80056de: e008 b.n 80056f2 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80056e0: f7fc f800 bl 80016e4 80056e4: 4602 mov r2, r0 80056e6: 6a7b ldr r3, [r7, #36] @ 0x24 80056e8: 1ad3 subs r3, r2, r3 80056ea: 2b02 cmp r3, #2 80056ec: d901 bls.n 80056f2 { return HAL_TIMEOUT; 80056ee: 2303 movs r3, #3 80056f0: e10e b.n 8005910 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 80056f2: 4b39 ldr r3, [pc, #228] @ (80057d8 ) 80056f4: 681b ldr r3, [r3, #0] 80056f6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80056fa: 2b00 cmp r3, #0 80056fc: d1f0 bne.n 80056e0 } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 80056fe: 4b36 ldr r3, [pc, #216] @ (80057d8 ) 8005700: 6a9a ldr r2, [r3, #40] @ 0x28 8005702: 4b37 ldr r3, [pc, #220] @ (80057e0 ) 8005704: 4013 ands r3, r2 8005706: 687a ldr r2, [r7, #4] 8005708: 6a91 ldr r1, [r2, #40] @ 0x28 800570a: 687a ldr r2, [r7, #4] 800570c: 6ad2 ldr r2, [r2, #44] @ 0x2c 800570e: 0112 lsls r2, r2, #4 8005710: 430a orrs r2, r1 8005712: 4931 ldr r1, [pc, #196] @ (80057d8 ) 8005714: 4313 orrs r3, r2 8005716: 628b str r3, [r1, #40] @ 0x28 8005718: 687b ldr r3, [r7, #4] 800571a: 6b1b ldr r3, [r3, #48] @ 0x30 800571c: 3b01 subs r3, #1 800571e: f3c3 0208 ubfx r2, r3, #0, #9 8005722: 687b ldr r3, [r7, #4] 8005724: 6b5b ldr r3, [r3, #52] @ 0x34 8005726: 3b01 subs r3, #1 8005728: 025b lsls r3, r3, #9 800572a: b29b uxth r3, r3 800572c: 431a orrs r2, r3 800572e: 687b ldr r3, [r7, #4] 8005730: 6b9b ldr r3, [r3, #56] @ 0x38 8005732: 3b01 subs r3, #1 8005734: 041b lsls r3, r3, #16 8005736: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800573a: 431a orrs r2, r3 800573c: 687b ldr r3, [r7, #4] 800573e: 6bdb ldr r3, [r3, #60] @ 0x3c 8005740: 3b01 subs r3, #1 8005742: 061b lsls r3, r3, #24 8005744: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 8005748: 4923 ldr r1, [pc, #140] @ (80057d8 ) 800574a: 4313 orrs r3, r2 800574c: 630b str r3, [r1, #48] @ 0x30 RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Disable PLLFRACN . */ __HAL_RCC_PLLFRACN_DISABLE(); 800574e: 4b22 ldr r3, [pc, #136] @ (80057d8 ) 8005750: 6adb ldr r3, [r3, #44] @ 0x2c 8005752: 4a21 ldr r2, [pc, #132] @ (80057d8 ) 8005754: f023 0301 bic.w r3, r3, #1 8005758: 62d3 str r3, [r2, #44] @ 0x2c /* Configure PLL PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 800575a: 4b1f ldr r3, [pc, #124] @ (80057d8 ) 800575c: 6b5a ldr r2, [r3, #52] @ 0x34 800575e: 4b21 ldr r3, [pc, #132] @ (80057e4 ) 8005760: 4013 ands r3, r2 8005762: 687a ldr r2, [r7, #4] 8005764: 6c92 ldr r2, [r2, #72] @ 0x48 8005766: 00d2 lsls r2, r2, #3 8005768: 491b ldr r1, [pc, #108] @ (80057d8 ) 800576a: 4313 orrs r3, r2 800576c: 634b str r3, [r1, #52] @ 0x34 /* Select PLL1 input reference frequency range: VCI */ __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ; 800576e: 4b1a ldr r3, [pc, #104] @ (80057d8 ) 8005770: 6adb ldr r3, [r3, #44] @ 0x2c 8005772: f023 020c bic.w r2, r3, #12 8005776: 687b ldr r3, [r7, #4] 8005778: 6c1b ldr r3, [r3, #64] @ 0x40 800577a: 4917 ldr r1, [pc, #92] @ (80057d8 ) 800577c: 4313 orrs r3, r2 800577e: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL1 output frequency range : VCO */ __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ; 8005780: 4b15 ldr r3, [pc, #84] @ (80057d8 ) 8005782: 6adb ldr r3, [r3, #44] @ 0x2c 8005784: f023 0202 bic.w r2, r3, #2 8005788: 687b ldr r3, [r7, #4] 800578a: 6c5b ldr r3, [r3, #68] @ 0x44 800578c: 4912 ldr r1, [pc, #72] @ (80057d8 ) 800578e: 4313 orrs r3, r2 8005790: 62cb str r3, [r1, #44] @ 0x2c /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); 8005792: 4b11 ldr r3, [pc, #68] @ (80057d8 ) 8005794: 6adb ldr r3, [r3, #44] @ 0x2c 8005796: 4a10 ldr r2, [pc, #64] @ (80057d8 ) 8005798: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800579c: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1Q Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800579e: 4b0e ldr r3, [pc, #56] @ (80057d8 ) 80057a0: 6adb ldr r3, [r3, #44] @ 0x2c 80057a2: 4a0d ldr r2, [pc, #52] @ (80057d8 ) 80057a4: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80057a8: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1R Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); 80057aa: 4b0b ldr r3, [pc, #44] @ (80057d8 ) 80057ac: 6adb ldr r3, [r3, #44] @ 0x2c 80057ae: 4a0a ldr r2, [pc, #40] @ (80057d8 ) 80057b0: f443 2380 orr.w r3, r3, #262144 @ 0x40000 80057b4: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1FRACN . */ __HAL_RCC_PLLFRACN_ENABLE(); 80057b6: 4b08 ldr r3, [pc, #32] @ (80057d8 ) 80057b8: 6adb ldr r3, [r3, #44] @ 0x2c 80057ba: 4a07 ldr r2, [pc, #28] @ (80057d8 ) 80057bc: f043 0301 orr.w r3, r3, #1 80057c0: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 80057c2: 4b05 ldr r3, [pc, #20] @ (80057d8 ) 80057c4: 681b ldr r3, [r3, #0] 80057c6: 4a04 ldr r2, [pc, #16] @ (80057d8 ) 80057c8: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 80057cc: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80057ce: f7fb ff89 bl 80016e4 80057d2: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 80057d4: e011 b.n 80057fa 80057d6: bf00 nop 80057d8: 58024400 .word 0x58024400 80057dc: 58024800 .word 0x58024800 80057e0: fffffc0c .word 0xfffffc0c 80057e4: ffff0007 .word 0xffff0007 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80057e8: f7fb ff7c bl 80016e4 80057ec: 4602 mov r2, r0 80057ee: 6a7b ldr r3, [r7, #36] @ 0x24 80057f0: 1ad3 subs r3, r2, r3 80057f2: 2b02 cmp r3, #2 80057f4: d901 bls.n 80057fa { return HAL_TIMEOUT; 80057f6: 2303 movs r3, #3 80057f8: e08a b.n 8005910 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 80057fa: 4b47 ldr r3, [pc, #284] @ (8005918 ) 80057fc: 681b ldr r3, [r3, #0] 80057fe: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8005802: 2b00 cmp r3, #0 8005804: d0f0 beq.n 80057e8 8005806: e082 b.n 800590e } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8005808: 4b43 ldr r3, [pc, #268] @ (8005918 ) 800580a: 681b ldr r3, [r3, #0] 800580c: 4a42 ldr r2, [pc, #264] @ (8005918 ) 800580e: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 8005812: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005814: f7fb ff66 bl 80016e4 8005818: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800581a: e008 b.n 800582e { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800581c: f7fb ff62 bl 80016e4 8005820: 4602 mov r2, r0 8005822: 6a7b ldr r3, [r7, #36] @ 0x24 8005824: 1ad3 subs r3, r2, r3 8005826: 2b02 cmp r3, #2 8005828: d901 bls.n 800582e { return HAL_TIMEOUT; 800582a: 2303 movs r3, #3 800582c: e070 b.n 8005910 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800582e: 4b3a ldr r3, [pc, #232] @ (8005918 ) 8005830: 681b ldr r3, [r3, #0] 8005832: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8005836: 2b00 cmp r3, #0 8005838: d1f0 bne.n 800581c 800583a: e068 b.n 800590e } } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp1_pllckcfg = RCC->PLLCKSELR; 800583c: 4b36 ldr r3, [pc, #216] @ (8005918 ) 800583e: 6a9b ldr r3, [r3, #40] @ 0x28 8005840: 613b str r3, [r7, #16] temp2_pllckcfg = RCC->PLL1DIVR; 8005842: 4b35 ldr r3, [pc, #212] @ (8005918 ) 8005844: 6b1b ldr r3, [r3, #48] @ 0x30 8005846: 60fb str r3, [r7, #12] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8005848: 687b ldr r3, [r7, #4] 800584a: 6a5b ldr r3, [r3, #36] @ 0x24 800584c: 2b01 cmp r3, #1 800584e: d031 beq.n 80058b4 (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8005850: 693b ldr r3, [r7, #16] 8005852: f003 0203 and.w r2, r3, #3 8005856: 687b ldr r3, [r7, #4] 8005858: 6a9b ldr r3, [r3, #40] @ 0x28 if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 800585a: 429a cmp r2, r3 800585c: d12a bne.n 80058b4 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 800585e: 693b ldr r3, [r7, #16] 8005860: 091b lsrs r3, r3, #4 8005862: f003 023f and.w r2, r3, #63 @ 0x3f 8005866: 687b ldr r3, [r7, #4] 8005868: 6adb ldr r3, [r3, #44] @ 0x2c (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800586a: 429a cmp r2, r3 800586c: d122 bne.n 80058b4 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 800586e: 68fb ldr r3, [r7, #12] 8005870: f3c3 0208 ubfx r2, r3, #0, #9 8005874: 687b ldr r3, [r7, #4] 8005876: 6b1b ldr r3, [r3, #48] @ 0x30 8005878: 3b01 subs r3, #1 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 800587a: 429a cmp r2, r3 800587c: d11a bne.n 80058b4 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 800587e: 68fb ldr r3, [r7, #12] 8005880: 0a5b lsrs r3, r3, #9 8005882: f003 027f and.w r2, r3, #127 @ 0x7f 8005886: 687b ldr r3, [r7, #4] 8005888: 6b5b ldr r3, [r3, #52] @ 0x34 800588a: 3b01 subs r3, #1 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 800588c: 429a cmp r2, r3 800588e: d111 bne.n 80058b4 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 8005890: 68fb ldr r3, [r7, #12] 8005892: 0c1b lsrs r3, r3, #16 8005894: f003 027f and.w r2, r3, #127 @ 0x7f 8005898: 687b ldr r3, [r7, #4] 800589a: 6b9b ldr r3, [r3, #56] @ 0x38 800589c: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 800589e: 429a cmp r2, r3 80058a0: d108 bne.n 80058b4 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) 80058a2: 68fb ldr r3, [r7, #12] 80058a4: 0e1b lsrs r3, r3, #24 80058a6: f003 027f and.w r2, r3, #127 @ 0x7f 80058aa: 687b ldr r3, [r7, #4] 80058ac: 6bdb ldr r3, [r3, #60] @ 0x3c 80058ae: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 80058b0: 429a cmp r2, r3 80058b2: d001 beq.n 80058b8 { return HAL_ERROR; 80058b4: 2301 movs r3, #1 80058b6: e02b b.n 8005910 } else { /* Check if only fractional part needs to be updated */ temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos); 80058b8: 4b17 ldr r3, [pc, #92] @ (8005918 ) 80058ba: 6b5b ldr r3, [r3, #52] @ 0x34 80058bc: 08db lsrs r3, r3, #3 80058be: f3c3 030c ubfx r3, r3, #0, #13 80058c2: 613b str r3, [r7, #16] if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg) 80058c4: 687b ldr r3, [r7, #4] 80058c6: 6c9b ldr r3, [r3, #72] @ 0x48 80058c8: 693a ldr r2, [r7, #16] 80058ca: 429a cmp r2, r3 80058cc: d01f beq.n 800590e { assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable PLL1FRACEN */ __HAL_RCC_PLLFRACN_DISABLE(); 80058ce: 4b12 ldr r3, [pc, #72] @ (8005918 ) 80058d0: 6adb ldr r3, [r3, #44] @ 0x2c 80058d2: 4a11 ldr r2, [pc, #68] @ (8005918 ) 80058d4: f023 0301 bic.w r3, r3, #1 80058d8: 62d3 str r3, [r2, #44] @ 0x2c /* Get Start Tick*/ tickstart = HAL_GetTick(); 80058da: f7fb ff03 bl 80016e4 80058de: 6278 str r0, [r7, #36] @ 0x24 /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */ while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE) 80058e0: bf00 nop 80058e2: f7fb feff bl 80016e4 80058e6: 4602 mov r2, r0 80058e8: 6a7b ldr r3, [r7, #36] @ 0x24 80058ea: 4293 cmp r3, r2 80058ec: d0f9 beq.n 80058e2 { } /* Configure PLL1 PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 80058ee: 4b0a ldr r3, [pc, #40] @ (8005918 ) 80058f0: 6b5a ldr r2, [r3, #52] @ 0x34 80058f2: 4b0a ldr r3, [pc, #40] @ (800591c ) 80058f4: 4013 ands r3, r2 80058f6: 687a ldr r2, [r7, #4] 80058f8: 6c92 ldr r2, [r2, #72] @ 0x48 80058fa: 00d2 lsls r2, r2, #3 80058fc: 4906 ldr r1, [pc, #24] @ (8005918 ) 80058fe: 4313 orrs r3, r2 8005900: 634b str r3, [r1, #52] @ 0x34 /* Enable PLL1FRACEN to latch new value. */ __HAL_RCC_PLLFRACN_ENABLE(); 8005902: 4b05 ldr r3, [pc, #20] @ (8005918 ) 8005904: 6adb ldr r3, [r3, #44] @ 0x2c 8005906: 4a04 ldr r2, [pc, #16] @ (8005918 ) 8005908: f043 0301 orr.w r3, r3, #1 800590c: 62d3 str r3, [r2, #44] @ 0x2c } } } } return HAL_OK; 800590e: 2300 movs r3, #0 } 8005910: 4618 mov r0, r3 8005912: 3730 adds r7, #48 @ 0x30 8005914: 46bd mov sp, r7 8005916: bd80 pop {r7, pc} 8005918: 58024400 .word 0x58024400 800591c: ffff0007 .word 0xffff0007 08005920 : * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8005920: b580 push {r7, lr} 8005922: b086 sub sp, #24 8005924: af00 add r7, sp, #0 8005926: 6078 str r0, [r7, #4] 8005928: 6039 str r1, [r7, #0] HAL_StatusTypeDef halstatus; uint32_t tickstart; uint32_t common_system_clock; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 800592a: 687b ldr r3, [r7, #4] 800592c: 2b00 cmp r3, #0 800592e: d101 bne.n 8005934 { return HAL_ERROR; 8005930: 2301 movs r3, #1 8005932: e19c b.n 8005c6e /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8005934: 4b8a ldr r3, [pc, #552] @ (8005b60 ) 8005936: 681b ldr r3, [r3, #0] 8005938: f003 030f and.w r3, r3, #15 800593c: 683a ldr r2, [r7, #0] 800593e: 429a cmp r2, r3 8005940: d910 bls.n 8005964 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8005942: 4b87 ldr r3, [pc, #540] @ (8005b60 ) 8005944: 681b ldr r3, [r3, #0] 8005946: f023 020f bic.w r2, r3, #15 800594a: 4985 ldr r1, [pc, #532] @ (8005b60 ) 800594c: 683b ldr r3, [r7, #0] 800594e: 4313 orrs r3, r2 8005950: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8005952: 4b83 ldr r3, [pc, #524] @ (8005b60 ) 8005954: 681b ldr r3, [r3, #0] 8005956: f003 030f and.w r3, r3, #15 800595a: 683a ldr r2, [r7, #0] 800595c: 429a cmp r2, r3 800595e: d001 beq.n 8005964 { return HAL_ERROR; 8005960: 2301 movs r3, #1 8005962: e184 b.n 8005c6e } /* Increasing the BUS frequency divider */ /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 8005964: 687b ldr r3, [r7, #4] 8005966: 681b ldr r3, [r3, #0] 8005968: f003 0304 and.w r3, r3, #4 800596c: 2b00 cmp r3, #0 800596e: d010 beq.n 8005992 { #if defined (RCC_D1CFGR_D1PPRE) if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 8005970: 687b ldr r3, [r7, #4] 8005972: 691a ldr r2, [r3, #16] 8005974: 4b7b ldr r3, [pc, #492] @ (8005b64 ) 8005976: 699b ldr r3, [r3, #24] 8005978: f003 0370 and.w r3, r3, #112 @ 0x70 800597c: 429a cmp r2, r3 800597e: d908 bls.n 8005992 { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 8005980: 4b78 ldr r3, [pc, #480] @ (8005b64 ) 8005982: 699b ldr r3, [r3, #24] 8005984: f023 0270 bic.w r2, r3, #112 @ 0x70 8005988: 687b ldr r3, [r7, #4] 800598a: 691b ldr r3, [r3, #16] 800598c: 4975 ldr r1, [pc, #468] @ (8005b64 ) 800598e: 4313 orrs r3, r2 8005990: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8005992: 687b ldr r3, [r7, #4] 8005994: 681b ldr r3, [r3, #0] 8005996: f003 0308 and.w r3, r3, #8 800599a: 2b00 cmp r3, #0 800599c: d010 beq.n 80059c0 { #if defined (RCC_D2CFGR_D2PPRE1) if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 800599e: 687b ldr r3, [r7, #4] 80059a0: 695a ldr r2, [r3, #20] 80059a2: 4b70 ldr r3, [pc, #448] @ (8005b64 ) 80059a4: 69db ldr r3, [r3, #28] 80059a6: f003 0370 and.w r3, r3, #112 @ 0x70 80059aa: 429a cmp r2, r3 80059ac: d908 bls.n 80059c0 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 80059ae: 4b6d ldr r3, [pc, #436] @ (8005b64 ) 80059b0: 69db ldr r3, [r3, #28] 80059b2: f023 0270 bic.w r2, r3, #112 @ 0x70 80059b6: 687b ldr r3, [r7, #4] 80059b8: 695b ldr r3, [r3, #20] 80059ba: 496a ldr r1, [pc, #424] @ (8005b64 ) 80059bc: 4313 orrs r3, r2 80059be: 61cb str r3, [r1, #28] MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80059c0: 687b ldr r3, [r7, #4] 80059c2: 681b ldr r3, [r3, #0] 80059c4: f003 0310 and.w r3, r3, #16 80059c8: 2b00 cmp r3, #0 80059ca: d010 beq.n 80059ee { #if defined(RCC_D2CFGR_D2PPRE2) if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 80059cc: 687b ldr r3, [r7, #4] 80059ce: 699a ldr r2, [r3, #24] 80059d0: 4b64 ldr r3, [pc, #400] @ (8005b64 ) 80059d2: 69db ldr r3, [r3, #28] 80059d4: f403 63e0 and.w r3, r3, #1792 @ 0x700 80059d8: 429a cmp r2, r3 80059da: d908 bls.n 80059ee { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 80059dc: 4b61 ldr r3, [pc, #388] @ (8005b64 ) 80059de: 69db ldr r3, [r3, #28] 80059e0: f423 62e0 bic.w r2, r3, #1792 @ 0x700 80059e4: 687b ldr r3, [r7, #4] 80059e6: 699b ldr r3, [r3, #24] 80059e8: 495e ldr r1, [pc, #376] @ (8005b64 ) 80059ea: 4313 orrs r3, r2 80059ec: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 80059ee: 687b ldr r3, [r7, #4] 80059f0: 681b ldr r3, [r3, #0] 80059f2: f003 0320 and.w r3, r3, #32 80059f6: 2b00 cmp r3, #0 80059f8: d010 beq.n 8005a1c { #if defined(RCC_D3CFGR_D3PPRE) if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 80059fa: 687b ldr r3, [r7, #4] 80059fc: 69da ldr r2, [r3, #28] 80059fe: 4b59 ldr r3, [pc, #356] @ (8005b64 ) 8005a00: 6a1b ldr r3, [r3, #32] 8005a02: f003 0370 and.w r3, r3, #112 @ 0x70 8005a06: 429a cmp r2, r3 8005a08: d908 bls.n 8005a1c { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 8005a0a: 4b56 ldr r3, [pc, #344] @ (8005b64 ) 8005a0c: 6a1b ldr r3, [r3, #32] 8005a0e: f023 0270 bic.w r2, r3, #112 @ 0x70 8005a12: 687b ldr r3, [r7, #4] 8005a14: 69db ldr r3, [r3, #28] 8005a16: 4953 ldr r1, [pc, #332] @ (8005b64 ) 8005a18: 4313 orrs r3, r2 8005a1a: 620b str r3, [r1, #32] } #endif } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8005a1c: 687b ldr r3, [r7, #4] 8005a1e: 681b ldr r3, [r3, #0] 8005a20: f003 0302 and.w r3, r3, #2 8005a24: 2b00 cmp r3, #0 8005a26: d010 beq.n 8005a4a { #if defined (RCC_D1CFGR_HPRE) if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 8005a28: 687b ldr r3, [r7, #4] 8005a2a: 68da ldr r2, [r3, #12] 8005a2c: 4b4d ldr r3, [pc, #308] @ (8005b64 ) 8005a2e: 699b ldr r3, [r3, #24] 8005a30: f003 030f and.w r3, r3, #15 8005a34: 429a cmp r2, r3 8005a36: d908 bls.n 8005a4a { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8005a38: 4b4a ldr r3, [pc, #296] @ (8005b64 ) 8005a3a: 699b ldr r3, [r3, #24] 8005a3c: f023 020f bic.w r2, r3, #15 8005a40: 687b ldr r3, [r7, #4] 8005a42: 68db ldr r3, [r3, #12] 8005a44: 4947 ldr r1, [pc, #284] @ (8005b64 ) 8005a46: 4313 orrs r3, r2 8005a48: 618b str r3, [r1, #24] } #endif } /*------------------------- SYSCLK Configuration -------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8005a4a: 687b ldr r3, [r7, #4] 8005a4c: 681b ldr r3, [r3, #0] 8005a4e: f003 0301 and.w r3, r3, #1 8005a52: 2b00 cmp r3, #0 8005a54: d055 beq.n 8005b02 { assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); #if defined(RCC_D1CFGR_D1CPRE) MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); 8005a56: 4b43 ldr r3, [pc, #268] @ (8005b64 ) 8005a58: 699b ldr r3, [r3, #24] 8005a5a: f423 6270 bic.w r2, r3, #3840 @ 0xf00 8005a5e: 687b ldr r3, [r7, #4] 8005a60: 689b ldr r3, [r3, #8] 8005a62: 4940 ldr r1, [pc, #256] @ (8005b64 ) 8005a64: 4313 orrs r3, r2 8005a66: 618b str r3, [r1, #24] #else MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); #endif /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8005a68: 687b ldr r3, [r7, #4] 8005a6a: 685b ldr r3, [r3, #4] 8005a6c: 2b02 cmp r3, #2 8005a6e: d107 bne.n 8005a80 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 8005a70: 4b3c ldr r3, [pc, #240] @ (8005b64 ) 8005a72: 681b ldr r3, [r3, #0] 8005a74: f403 3300 and.w r3, r3, #131072 @ 0x20000 8005a78: 2b00 cmp r3, #0 8005a7a: d121 bne.n 8005ac0 { return HAL_ERROR; 8005a7c: 2301 movs r3, #1 8005a7e: e0f6 b.n 8005c6e } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8005a80: 687b ldr r3, [r7, #4] 8005a82: 685b ldr r3, [r3, #4] 8005a84: 2b03 cmp r3, #3 8005a86: d107 bne.n 8005a98 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 8005a88: 4b36 ldr r3, [pc, #216] @ (8005b64 ) 8005a8a: 681b ldr r3, [r3, #0] 8005a8c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8005a90: 2b00 cmp r3, #0 8005a92: d115 bne.n 8005ac0 { return HAL_ERROR; 8005a94: 2301 movs r3, #1 8005a96: e0ea b.n 8005c6e } } /* CSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) 8005a98: 687b ldr r3, [r7, #4] 8005a9a: 685b ldr r3, [r3, #4] 8005a9c: 2b01 cmp r3, #1 8005a9e: d107 bne.n 8005ab0 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 8005aa0: 4b30 ldr r3, [pc, #192] @ (8005b64 ) 8005aa2: 681b ldr r3, [r3, #0] 8005aa4: f403 7380 and.w r3, r3, #256 @ 0x100 8005aa8: 2b00 cmp r3, #0 8005aaa: d109 bne.n 8005ac0 { return HAL_ERROR; 8005aac: 2301 movs r3, #1 8005aae: e0de b.n 8005c6e } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8005ab0: 4b2c ldr r3, [pc, #176] @ (8005b64 ) 8005ab2: 681b ldr r3, [r3, #0] 8005ab4: f003 0304 and.w r3, r3, #4 8005ab8: 2b00 cmp r3, #0 8005aba: d101 bne.n 8005ac0 { return HAL_ERROR; 8005abc: 2301 movs r3, #1 8005abe: e0d6 b.n 8005c6e } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 8005ac0: 4b28 ldr r3, [pc, #160] @ (8005b64 ) 8005ac2: 691b ldr r3, [r3, #16] 8005ac4: f023 0207 bic.w r2, r3, #7 8005ac8: 687b ldr r3, [r7, #4] 8005aca: 685b ldr r3, [r3, #4] 8005acc: 4925 ldr r1, [pc, #148] @ (8005b64 ) 8005ace: 4313 orrs r3, r2 8005ad0: 610b str r3, [r1, #16] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005ad2: f7fb fe07 bl 80016e4 8005ad6: 6178 str r0, [r7, #20] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8005ad8: e00a b.n 8005af0 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8005ada: f7fb fe03 bl 80016e4 8005ade: 4602 mov r2, r0 8005ae0: 697b ldr r3, [r7, #20] 8005ae2: 1ad3 subs r3, r2, r3 8005ae4: f241 3288 movw r2, #5000 @ 0x1388 8005ae8: 4293 cmp r3, r2 8005aea: d901 bls.n 8005af0 { return HAL_TIMEOUT; 8005aec: 2303 movs r3, #3 8005aee: e0be b.n 8005c6e while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8005af0: 4b1c ldr r3, [pc, #112] @ (8005b64 ) 8005af2: 691b ldr r3, [r3, #16] 8005af4: f003 0238 and.w r2, r3, #56 @ 0x38 8005af8: 687b ldr r3, [r7, #4] 8005afa: 685b ldr r3, [r3, #4] 8005afc: 00db lsls r3, r3, #3 8005afe: 429a cmp r2, r3 8005b00: d1eb bne.n 8005ada } /* Decreasing the BUS frequency divider */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8005b02: 687b ldr r3, [r7, #4] 8005b04: 681b ldr r3, [r3, #0] 8005b06: f003 0302 and.w r3, r3, #2 8005b0a: 2b00 cmp r3, #0 8005b0c: d010 beq.n 8005b30 { #if defined(RCC_D1CFGR_HPRE) if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 8005b0e: 687b ldr r3, [r7, #4] 8005b10: 68da ldr r2, [r3, #12] 8005b12: 4b14 ldr r3, [pc, #80] @ (8005b64 ) 8005b14: 699b ldr r3, [r3, #24] 8005b16: f003 030f and.w r3, r3, #15 8005b1a: 429a cmp r2, r3 8005b1c: d208 bcs.n 8005b30 { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8005b1e: 4b11 ldr r3, [pc, #68] @ (8005b64 ) 8005b20: 699b ldr r3, [r3, #24] 8005b22: f023 020f bic.w r2, r3, #15 8005b26: 687b ldr r3, [r7, #4] 8005b28: 68db ldr r3, [r3, #12] 8005b2a: 490e ldr r1, [pc, #56] @ (8005b64 ) 8005b2c: 4313 orrs r3, r2 8005b2e: 618b str r3, [r1, #24] } #endif } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8005b30: 4b0b ldr r3, [pc, #44] @ (8005b60 ) 8005b32: 681b ldr r3, [r3, #0] 8005b34: f003 030f and.w r3, r3, #15 8005b38: 683a ldr r2, [r7, #0] 8005b3a: 429a cmp r2, r3 8005b3c: d214 bcs.n 8005b68 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8005b3e: 4b08 ldr r3, [pc, #32] @ (8005b60 ) 8005b40: 681b ldr r3, [r3, #0] 8005b42: f023 020f bic.w r2, r3, #15 8005b46: 4906 ldr r1, [pc, #24] @ (8005b60 ) 8005b48: 683b ldr r3, [r7, #0] 8005b4a: 4313 orrs r3, r2 8005b4c: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8005b4e: 4b04 ldr r3, [pc, #16] @ (8005b60 ) 8005b50: 681b ldr r3, [r3, #0] 8005b52: f003 030f and.w r3, r3, #15 8005b56: 683a ldr r2, [r7, #0] 8005b58: 429a cmp r2, r3 8005b5a: d005 beq.n 8005b68 { return HAL_ERROR; 8005b5c: 2301 movs r3, #1 8005b5e: e086 b.n 8005c6e 8005b60: 52002000 .word 0x52002000 8005b64: 58024400 .word 0x58024400 } } /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 8005b68: 687b ldr r3, [r7, #4] 8005b6a: 681b ldr r3, [r3, #0] 8005b6c: f003 0304 and.w r3, r3, #4 8005b70: 2b00 cmp r3, #0 8005b72: d010 beq.n 8005b96 { #if defined(RCC_D1CFGR_D1PPRE) if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 8005b74: 687b ldr r3, [r7, #4] 8005b76: 691a ldr r2, [r3, #16] 8005b78: 4b3f ldr r3, [pc, #252] @ (8005c78 ) 8005b7a: 699b ldr r3, [r3, #24] 8005b7c: f003 0370 and.w r3, r3, #112 @ 0x70 8005b80: 429a cmp r2, r3 8005b82: d208 bcs.n 8005b96 { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 8005b84: 4b3c ldr r3, [pc, #240] @ (8005c78 ) 8005b86: 699b ldr r3, [r3, #24] 8005b88: f023 0270 bic.w r2, r3, #112 @ 0x70 8005b8c: 687b ldr r3, [r7, #4] 8005b8e: 691b ldr r3, [r3, #16] 8005b90: 4939 ldr r1, [pc, #228] @ (8005c78 ) 8005b92: 4313 orrs r3, r2 8005b94: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8005b96: 687b ldr r3, [r7, #4] 8005b98: 681b ldr r3, [r3, #0] 8005b9a: f003 0308 and.w r3, r3, #8 8005b9e: 2b00 cmp r3, #0 8005ba0: d010 beq.n 8005bc4 { #if defined(RCC_D2CFGR_D2PPRE1) if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 8005ba2: 687b ldr r3, [r7, #4] 8005ba4: 695a ldr r2, [r3, #20] 8005ba6: 4b34 ldr r3, [pc, #208] @ (8005c78 ) 8005ba8: 69db ldr r3, [r3, #28] 8005baa: f003 0370 and.w r3, r3, #112 @ 0x70 8005bae: 429a cmp r2, r3 8005bb0: d208 bcs.n 8005bc4 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 8005bb2: 4b31 ldr r3, [pc, #196] @ (8005c78 ) 8005bb4: 69db ldr r3, [r3, #28] 8005bb6: f023 0270 bic.w r2, r3, #112 @ 0x70 8005bba: 687b ldr r3, [r7, #4] 8005bbc: 695b ldr r3, [r3, #20] 8005bbe: 492e ldr r1, [pc, #184] @ (8005c78 ) 8005bc0: 4313 orrs r3, r2 8005bc2: 61cb str r3, [r1, #28] } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8005bc4: 687b ldr r3, [r7, #4] 8005bc6: 681b ldr r3, [r3, #0] 8005bc8: f003 0310 and.w r3, r3, #16 8005bcc: 2b00 cmp r3, #0 8005bce: d010 beq.n 8005bf2 { #if defined (RCC_D2CFGR_D2PPRE2) if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 8005bd0: 687b ldr r3, [r7, #4] 8005bd2: 699a ldr r2, [r3, #24] 8005bd4: 4b28 ldr r3, [pc, #160] @ (8005c78 ) 8005bd6: 69db ldr r3, [r3, #28] 8005bd8: f403 63e0 and.w r3, r3, #1792 @ 0x700 8005bdc: 429a cmp r2, r3 8005bde: d208 bcs.n 8005bf2 { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 8005be0: 4b25 ldr r3, [pc, #148] @ (8005c78 ) 8005be2: 69db ldr r3, [r3, #28] 8005be4: f423 62e0 bic.w r2, r3, #1792 @ 0x700 8005be8: 687b ldr r3, [r7, #4] 8005bea: 699b ldr r3, [r3, #24] 8005bec: 4922 ldr r1, [pc, #136] @ (8005c78 ) 8005bee: 4313 orrs r3, r2 8005bf0: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 8005bf2: 687b ldr r3, [r7, #4] 8005bf4: 681b ldr r3, [r3, #0] 8005bf6: f003 0320 and.w r3, r3, #32 8005bfa: 2b00 cmp r3, #0 8005bfc: d010 beq.n 8005c20 { #if defined(RCC_D3CFGR_D3PPRE) if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 8005bfe: 687b ldr r3, [r7, #4] 8005c00: 69da ldr r2, [r3, #28] 8005c02: 4b1d ldr r3, [pc, #116] @ (8005c78 ) 8005c04: 6a1b ldr r3, [r3, #32] 8005c06: f003 0370 and.w r3, r3, #112 @ 0x70 8005c0a: 429a cmp r2, r3 8005c0c: d208 bcs.n 8005c20 { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 8005c0e: 4b1a ldr r3, [pc, #104] @ (8005c78 ) 8005c10: 6a1b ldr r3, [r3, #32] 8005c12: f023 0270 bic.w r2, r3, #112 @ 0x70 8005c16: 687b ldr r3, [r7, #4] 8005c18: 69db ldr r3, [r3, #28] 8005c1a: 4917 ldr r1, [pc, #92] @ (8005c78 ) 8005c1c: 4313 orrs r3, r2 8005c1e: 620b str r3, [r1, #32] #endif } /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 8005c20: f000 f834 bl 8005c8c 8005c24: 4602 mov r2, r0 8005c26: 4b14 ldr r3, [pc, #80] @ (8005c78 ) 8005c28: 699b ldr r3, [r3, #24] 8005c2a: 0a1b lsrs r3, r3, #8 8005c2c: f003 030f and.w r3, r3, #15 8005c30: 4912 ldr r1, [pc, #72] @ (8005c7c ) 8005c32: 5ccb ldrb r3, [r1, r3] 8005c34: f003 031f and.w r3, r3, #31 8005c38: fa22 f303 lsr.w r3, r2, r3 8005c3c: 613b str r3, [r7, #16] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8005c3e: 4b0e ldr r3, [pc, #56] @ (8005c78 ) 8005c40: 699b ldr r3, [r3, #24] 8005c42: f003 030f and.w r3, r3, #15 8005c46: 4a0d ldr r2, [pc, #52] @ (8005c7c ) 8005c48: 5cd3 ldrb r3, [r2, r3] 8005c4a: f003 031f and.w r3, r3, #31 8005c4e: 693a ldr r2, [r7, #16] 8005c50: fa22 f303 lsr.w r3, r2, r3 8005c54: 4a0a ldr r2, [pc, #40] @ (8005c80 ) 8005c56: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8005c58: 4a0a ldr r2, [pc, #40] @ (8005c84 ) 8005c5a: 693b ldr r3, [r7, #16] 8005c5c: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Configure the source of time base considering new system clocks settings*/ halstatus = HAL_InitTick(uwTickPrio); 8005c5e: 4b0a ldr r3, [pc, #40] @ (8005c88 ) 8005c60: 681b ldr r3, [r3, #0] 8005c62: 4618 mov r0, r3 8005c64: f7fb fcf4 bl 8001650 8005c68: 4603 mov r3, r0 8005c6a: 73fb strb r3, [r7, #15] return halstatus; 8005c6c: 7bfb ldrb r3, [r7, #15] } 8005c6e: 4618 mov r0, r3 8005c70: 3718 adds r7, #24 8005c72: 46bd mov sp, r7 8005c74: bd80 pop {r7, pc} 8005c76: bf00 nop 8005c78: 58024400 .word 0x58024400 8005c7c: 0800aab4 .word 0x0800aab4 8005c80: 24000004 .word 0x24000004 8005c84: 24000000 .word 0x24000000 8005c88: 24000008 .word 0x24000008 08005c8c : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8005c8c: b480 push {r7} 8005c8e: b089 sub sp, #36 @ 0x24 8005c90: af00 add r7, sp, #0 float_t fracn1, pllvco; uint32_t sysclockfreq; /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 8005c92: 4bb3 ldr r3, [pc, #716] @ (8005f60 ) 8005c94: 691b ldr r3, [r3, #16] 8005c96: f003 0338 and.w r3, r3, #56 @ 0x38 8005c9a: 2b18 cmp r3, #24 8005c9c: f200 8155 bhi.w 8005f4a 8005ca0: a201 add r2, pc, #4 @ (adr r2, 8005ca8 ) 8005ca2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005ca6: bf00 nop 8005ca8: 08005d0d .word 0x08005d0d 8005cac: 08005f4b .word 0x08005f4b 8005cb0: 08005f4b .word 0x08005f4b 8005cb4: 08005f4b .word 0x08005f4b 8005cb8: 08005f4b .word 0x08005f4b 8005cbc: 08005f4b .word 0x08005f4b 8005cc0: 08005f4b .word 0x08005f4b 8005cc4: 08005f4b .word 0x08005f4b 8005cc8: 08005d33 .word 0x08005d33 8005ccc: 08005f4b .word 0x08005f4b 8005cd0: 08005f4b .word 0x08005f4b 8005cd4: 08005f4b .word 0x08005f4b 8005cd8: 08005f4b .word 0x08005f4b 8005cdc: 08005f4b .word 0x08005f4b 8005ce0: 08005f4b .word 0x08005f4b 8005ce4: 08005f4b .word 0x08005f4b 8005ce8: 08005d39 .word 0x08005d39 8005cec: 08005f4b .word 0x08005f4b 8005cf0: 08005f4b .word 0x08005f4b 8005cf4: 08005f4b .word 0x08005f4b 8005cf8: 08005f4b .word 0x08005f4b 8005cfc: 08005f4b .word 0x08005f4b 8005d00: 08005f4b .word 0x08005f4b 8005d04: 08005f4b .word 0x08005f4b 8005d08: 08005d3f .word 0x08005d3f { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8005d0c: 4b94 ldr r3, [pc, #592] @ (8005f60 ) 8005d0e: 681b ldr r3, [r3, #0] 8005d10: f003 0320 and.w r3, r3, #32 8005d14: 2b00 cmp r3, #0 8005d16: d009 beq.n 8005d2c { sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8005d18: 4b91 ldr r3, [pc, #580] @ (8005f60 ) 8005d1a: 681b ldr r3, [r3, #0] 8005d1c: 08db lsrs r3, r3, #3 8005d1e: f003 0303 and.w r3, r3, #3 8005d22: 4a90 ldr r2, [pc, #576] @ (8005f64 ) 8005d24: fa22 f303 lsr.w r3, r2, r3 8005d28: 61bb str r3, [r7, #24] else { sysclockfreq = (uint32_t) HSI_VALUE; } break; 8005d2a: e111 b.n 8005f50 sysclockfreq = (uint32_t) HSI_VALUE; 8005d2c: 4b8d ldr r3, [pc, #564] @ (8005f64 ) 8005d2e: 61bb str r3, [r7, #24] break; 8005d30: e10e b.n 8005f50 case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ sysclockfreq = CSI_VALUE; 8005d32: 4b8d ldr r3, [pc, #564] @ (8005f68 ) 8005d34: 61bb str r3, [r7, #24] break; 8005d36: e10b b.n 8005f50 case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 8005d38: 4b8c ldr r3, [pc, #560] @ (8005f6c ) 8005d3a: 61bb str r3, [r7, #24] break; 8005d3c: e108 b.n 8005f50 case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 8005d3e: 4b88 ldr r3, [pc, #544] @ (8005f60 ) 8005d40: 6a9b ldr r3, [r3, #40] @ 0x28 8005d42: f003 0303 and.w r3, r3, #3 8005d46: 617b str r3, [r7, #20] pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ; 8005d48: 4b85 ldr r3, [pc, #532] @ (8005f60 ) 8005d4a: 6a9b ldr r3, [r3, #40] @ 0x28 8005d4c: 091b lsrs r3, r3, #4 8005d4e: f003 033f and.w r3, r3, #63 @ 0x3f 8005d52: 613b str r3, [r7, #16] pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); 8005d54: 4b82 ldr r3, [pc, #520] @ (8005f60 ) 8005d56: 6adb ldr r3, [r3, #44] @ 0x2c 8005d58: f003 0301 and.w r3, r3, #1 8005d5c: 60fb str r3, [r7, #12] fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 8005d5e: 4b80 ldr r3, [pc, #512] @ (8005f60 ) 8005d60: 6b5b ldr r3, [r3, #52] @ 0x34 8005d62: 08db lsrs r3, r3, #3 8005d64: f3c3 030c ubfx r3, r3, #0, #13 8005d68: 68fa ldr r2, [r7, #12] 8005d6a: fb02 f303 mul.w r3, r2, r3 8005d6e: ee07 3a90 vmov s15, r3 8005d72: eef8 7a67 vcvt.f32.u32 s15, s15 8005d76: edc7 7a02 vstr s15, [r7, #8] if (pllm != 0U) 8005d7a: 693b ldr r3, [r7, #16] 8005d7c: 2b00 cmp r3, #0 8005d7e: f000 80e1 beq.w 8005f44 { switch (pllsource) 8005d82: 697b ldr r3, [r7, #20] 8005d84: 2b02 cmp r3, #2 8005d86: f000 8083 beq.w 8005e90 8005d8a: 697b ldr r3, [r7, #20] 8005d8c: 2b02 cmp r3, #2 8005d8e: f200 80a1 bhi.w 8005ed4 8005d92: 697b ldr r3, [r7, #20] 8005d94: 2b00 cmp r3, #0 8005d96: d003 beq.n 8005da0 8005d98: 697b ldr r3, [r7, #20] 8005d9a: 2b01 cmp r3, #1 8005d9c: d056 beq.n 8005e4c 8005d9e: e099 b.n 8005ed4 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8005da0: 4b6f ldr r3, [pc, #444] @ (8005f60 ) 8005da2: 681b ldr r3, [r3, #0] 8005da4: f003 0320 and.w r3, r3, #32 8005da8: 2b00 cmp r3, #0 8005daa: d02d beq.n 8005e08 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8005dac: 4b6c ldr r3, [pc, #432] @ (8005f60 ) 8005dae: 681b ldr r3, [r3, #0] 8005db0: 08db lsrs r3, r3, #3 8005db2: f003 0303 and.w r3, r3, #3 8005db6: 4a6b ldr r2, [pc, #428] @ (8005f64 ) 8005db8: fa22 f303 lsr.w r3, r2, r3 8005dbc: 607b str r3, [r7, #4] pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8005dbe: 687b ldr r3, [r7, #4] 8005dc0: ee07 3a90 vmov s15, r3 8005dc4: eef8 6a67 vcvt.f32.u32 s13, s15 8005dc8: 693b ldr r3, [r7, #16] 8005dca: ee07 3a90 vmov s15, r3 8005dce: eef8 7a67 vcvt.f32.u32 s15, s15 8005dd2: ee86 7aa7 vdiv.f32 s14, s13, s15 8005dd6: 4b62 ldr r3, [pc, #392] @ (8005f60 ) 8005dd8: 6b1b ldr r3, [r3, #48] @ 0x30 8005dda: f3c3 0308 ubfx r3, r3, #0, #9 8005dde: ee07 3a90 vmov s15, r3 8005de2: eef8 6a67 vcvt.f32.u32 s13, s15 8005de6: ed97 6a02 vldr s12, [r7, #8] 8005dea: eddf 5a61 vldr s11, [pc, #388] @ 8005f70 8005dee: eec6 7a25 vdiv.f32 s15, s12, s11 8005df2: ee76 7aa7 vadd.f32 s15, s13, s15 8005df6: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8005dfa: ee77 7aa6 vadd.f32 s15, s15, s13 8005dfe: ee67 7a27 vmul.f32 s15, s14, s15 8005e02: edc7 7a07 vstr s15, [r7, #28] } else { pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); } break; 8005e06: e087 b.n 8005f18 pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8005e08: 693b ldr r3, [r7, #16] 8005e0a: ee07 3a90 vmov s15, r3 8005e0e: eef8 7a67 vcvt.f32.u32 s15, s15 8005e12: eddf 6a58 vldr s13, [pc, #352] @ 8005f74 8005e16: ee86 7aa7 vdiv.f32 s14, s13, s15 8005e1a: 4b51 ldr r3, [pc, #324] @ (8005f60 ) 8005e1c: 6b1b ldr r3, [r3, #48] @ 0x30 8005e1e: f3c3 0308 ubfx r3, r3, #0, #9 8005e22: ee07 3a90 vmov s15, r3 8005e26: eef8 6a67 vcvt.f32.u32 s13, s15 8005e2a: ed97 6a02 vldr s12, [r7, #8] 8005e2e: eddf 5a50 vldr s11, [pc, #320] @ 8005f70 8005e32: eec6 7a25 vdiv.f32 s15, s12, s11 8005e36: ee76 7aa7 vadd.f32 s15, s13, s15 8005e3a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8005e3e: ee77 7aa6 vadd.f32 s15, s15, s13 8005e42: ee67 7a27 vmul.f32 s15, s14, s15 8005e46: edc7 7a07 vstr s15, [r7, #28] break; 8005e4a: e065 b.n 8005f18 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8005e4c: 693b ldr r3, [r7, #16] 8005e4e: ee07 3a90 vmov s15, r3 8005e52: eef8 7a67 vcvt.f32.u32 s15, s15 8005e56: eddf 6a48 vldr s13, [pc, #288] @ 8005f78 8005e5a: ee86 7aa7 vdiv.f32 s14, s13, s15 8005e5e: 4b40 ldr r3, [pc, #256] @ (8005f60 ) 8005e60: 6b1b ldr r3, [r3, #48] @ 0x30 8005e62: f3c3 0308 ubfx r3, r3, #0, #9 8005e66: ee07 3a90 vmov s15, r3 8005e6a: eef8 6a67 vcvt.f32.u32 s13, s15 8005e6e: ed97 6a02 vldr s12, [r7, #8] 8005e72: eddf 5a3f vldr s11, [pc, #252] @ 8005f70 8005e76: eec6 7a25 vdiv.f32 s15, s12, s11 8005e7a: ee76 7aa7 vadd.f32 s15, s13, s15 8005e7e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8005e82: ee77 7aa6 vadd.f32 s15, s15, s13 8005e86: ee67 7a27 vmul.f32 s15, s14, s15 8005e8a: edc7 7a07 vstr s15, [r7, #28] break; 8005e8e: e043 b.n 8005f18 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8005e90: 693b ldr r3, [r7, #16] 8005e92: ee07 3a90 vmov s15, r3 8005e96: eef8 7a67 vcvt.f32.u32 s15, s15 8005e9a: eddf 6a38 vldr s13, [pc, #224] @ 8005f7c 8005e9e: ee86 7aa7 vdiv.f32 s14, s13, s15 8005ea2: 4b2f ldr r3, [pc, #188] @ (8005f60 ) 8005ea4: 6b1b ldr r3, [r3, #48] @ 0x30 8005ea6: f3c3 0308 ubfx r3, r3, #0, #9 8005eaa: ee07 3a90 vmov s15, r3 8005eae: eef8 6a67 vcvt.f32.u32 s13, s15 8005eb2: ed97 6a02 vldr s12, [r7, #8] 8005eb6: eddf 5a2e vldr s11, [pc, #184] @ 8005f70 8005eba: eec6 7a25 vdiv.f32 s15, s12, s11 8005ebe: ee76 7aa7 vadd.f32 s15, s13, s15 8005ec2: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8005ec6: ee77 7aa6 vadd.f32 s15, s15, s13 8005eca: ee67 7a27 vmul.f32 s15, s14, s15 8005ece: edc7 7a07 vstr s15, [r7, #28] break; 8005ed2: e021 b.n 8005f18 default: pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8005ed4: 693b ldr r3, [r7, #16] 8005ed6: ee07 3a90 vmov s15, r3 8005eda: eef8 7a67 vcvt.f32.u32 s15, s15 8005ede: eddf 6a26 vldr s13, [pc, #152] @ 8005f78 8005ee2: ee86 7aa7 vdiv.f32 s14, s13, s15 8005ee6: 4b1e ldr r3, [pc, #120] @ (8005f60 ) 8005ee8: 6b1b ldr r3, [r3, #48] @ 0x30 8005eea: f3c3 0308 ubfx r3, r3, #0, #9 8005eee: ee07 3a90 vmov s15, r3 8005ef2: eef8 6a67 vcvt.f32.u32 s13, s15 8005ef6: ed97 6a02 vldr s12, [r7, #8] 8005efa: eddf 5a1d vldr s11, [pc, #116] @ 8005f70 8005efe: eec6 7a25 vdiv.f32 s15, s12, s11 8005f02: ee76 7aa7 vadd.f32 s15, s13, s15 8005f06: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8005f0a: ee77 7aa6 vadd.f32 s15, s15, s13 8005f0e: ee67 7a27 vmul.f32 s15, s14, s15 8005f12: edc7 7a07 vstr s15, [r7, #28] break; 8005f16: bf00 nop } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ; 8005f18: 4b11 ldr r3, [pc, #68] @ (8005f60 ) 8005f1a: 6b1b ldr r3, [r3, #48] @ 0x30 8005f1c: 0a5b lsrs r3, r3, #9 8005f1e: f003 037f and.w r3, r3, #127 @ 0x7f 8005f22: 3301 adds r3, #1 8005f24: 603b str r3, [r7, #0] sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp); 8005f26: 683b ldr r3, [r7, #0] 8005f28: ee07 3a90 vmov s15, r3 8005f2c: eeb8 7a67 vcvt.f32.u32 s14, s15 8005f30: edd7 6a07 vldr s13, [r7, #28] 8005f34: eec6 7a87 vdiv.f32 s15, s13, s14 8005f38: eefc 7ae7 vcvt.u32.f32 s15, s15 8005f3c: ee17 3a90 vmov r3, s15 8005f40: 61bb str r3, [r7, #24] } else { sysclockfreq = 0U; } break; 8005f42: e005 b.n 8005f50 sysclockfreq = 0U; 8005f44: 2300 movs r3, #0 8005f46: 61bb str r3, [r7, #24] break; 8005f48: e002 b.n 8005f50 default: sysclockfreq = CSI_VALUE; 8005f4a: 4b07 ldr r3, [pc, #28] @ (8005f68 ) 8005f4c: 61bb str r3, [r7, #24] break; 8005f4e: bf00 nop } return sysclockfreq; 8005f50: 69bb ldr r3, [r7, #24] } 8005f52: 4618 mov r0, r3 8005f54: 3724 adds r7, #36 @ 0x24 8005f56: 46bd mov sp, r7 8005f58: f85d 7b04 ldr.w r7, [sp], #4 8005f5c: 4770 bx lr 8005f5e: bf00 nop 8005f60: 58024400 .word 0x58024400 8005f64: 03d09000 .word 0x03d09000 8005f68: 003d0900 .word 0x003d0900 8005f6c: 007a1200 .word 0x007a1200 8005f70: 46000000 .word 0x46000000 8005f74: 4c742400 .word 0x4c742400 8005f78: 4a742400 .word 0x4a742400 8005f7c: 4af42400 .word 0x4af42400 08005f80 : * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8005f80: b580 push {r7, lr} 8005f82: b082 sub sp, #8 8005f84: af00 add r7, sp, #0 uint32_t common_system_clock; #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 8005f86: f7ff fe81 bl 8005c8c 8005f8a: 4602 mov r2, r0 8005f8c: 4b10 ldr r3, [pc, #64] @ (8005fd0 ) 8005f8e: 699b ldr r3, [r3, #24] 8005f90: 0a1b lsrs r3, r3, #8 8005f92: f003 030f and.w r3, r3, #15 8005f96: 490f ldr r1, [pc, #60] @ (8005fd4 ) 8005f98: 5ccb ldrb r3, [r1, r3] 8005f9a: f003 031f and.w r3, r3, #31 8005f9e: fa22 f303 lsr.w r3, r2, r3 8005fa2: 607b str r3, [r7, #4] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8005fa4: 4b0a ldr r3, [pc, #40] @ (8005fd0 ) 8005fa6: 699b ldr r3, [r3, #24] 8005fa8: f003 030f and.w r3, r3, #15 8005fac: 4a09 ldr r2, [pc, #36] @ (8005fd4 ) 8005fae: 5cd3 ldrb r3, [r2, r3] 8005fb0: f003 031f and.w r3, r3, #31 8005fb4: 687a ldr r2, [r7, #4] 8005fb6: fa22 f303 lsr.w r3, r2, r3 8005fba: 4a07 ldr r2, [pc, #28] @ (8005fd8 ) 8005fbc: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8005fbe: 4a07 ldr r2, [pc, #28] @ (8005fdc ) 8005fc0: 687b ldr r3, [r7, #4] 8005fc2: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ return SystemD2Clock; 8005fc4: 4b04 ldr r3, [pc, #16] @ (8005fd8 ) 8005fc6: 681b ldr r3, [r3, #0] } 8005fc8: 4618 mov r0, r3 8005fca: 3708 adds r7, #8 8005fcc: 46bd mov sp, r7 8005fce: bd80 pop {r7, pc} 8005fd0: 58024400 .word 0x58024400 8005fd4: 0800aab4 .word 0x0800aab4 8005fd8: 24000004 .word 0x24000004 8005fdc: 24000000 .word 0x24000000 08005fe0 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8005fe0: b580 push {r7, lr} 8005fe2: af00 add r7, sp, #0 #if defined (RCC_D2CFGR_D2PPRE1) /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)); 8005fe4: f7ff ffcc bl 8005f80 8005fe8: 4602 mov r2, r0 8005fea: 4b06 ldr r3, [pc, #24] @ (8006004 ) 8005fec: 69db ldr r3, [r3, #28] 8005fee: 091b lsrs r3, r3, #4 8005ff0: f003 0307 and.w r3, r3, #7 8005ff4: 4904 ldr r1, [pc, #16] @ (8006008 ) 8005ff6: 5ccb ldrb r3, [r1, r3] 8005ff8: f003 031f and.w r3, r3, #31 8005ffc: fa22 f303 lsr.w r3, r2, r3 #else /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)); #endif } 8006000: 4618 mov r0, r3 8006002: bd80 pop {r7, pc} 8006004: 58024400 .word 0x58024400 8006008: 0800aab4 .word 0x0800aab4 0800600c : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 800600c: b580 push {r7, lr} 800600e: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ #if defined(RCC_D2CFGR_D2PPRE2) return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)); 8006010: f7ff ffb6 bl 8005f80 8006014: 4602 mov r2, r0 8006016: 4b06 ldr r3, [pc, #24] @ (8006030 ) 8006018: 69db ldr r3, [r3, #28] 800601a: 0a1b lsrs r3, r3, #8 800601c: f003 0307 and.w r3, r3, #7 8006020: 4904 ldr r1, [pc, #16] @ (8006034 ) 8006022: 5ccb ldrb r3, [r1, r3] 8006024: f003 031f and.w r3, r3, #31 8006028: fa22 f303 lsr.w r3, r2, r3 #else return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)); #endif } 800602c: 4618 mov r0, r3 800602e: bd80 pop {r7, pc} 8006030: 58024400 .word 0x58024400 8006034: 0800aab4 .word 0x0800aab4 08006038 : * (*) : Available on some STM32H7 lines only. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8006038: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 800603c: b0ca sub sp, #296 @ 0x128 800603e: af00 add r7, sp, #0 8006040: f8c7 0114 str.w r0, [r7, #276] @ 0x114 uint32_t tmpreg; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 8006044: 2300 movs r3, #0 8006046: f887 3127 strb.w r3, [r7, #295] @ 0x127 HAL_StatusTypeDef status = HAL_OK; /* Final status */ 800604a: 2300 movs r3, #0 800604c: f887 3126 strb.w r3, [r7, #294] @ 0x126 /*---------------------------- SPDIFRX configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 8006050: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006054: e9d3 2300 ldrd r2, r3, [r3] 8006058: f002 6400 and.w r4, r2, #134217728 @ 0x8000000 800605c: 2500 movs r5, #0 800605e: ea54 0305 orrs.w r3, r4, r5 8006062: d049 beq.n 80060f8 { switch (PeriphClkInit->SpdifrxClockSelection) 8006064: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006068: 6e9b ldr r3, [r3, #104] @ 0x68 800606a: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800606e: d02f beq.n 80060d0 8006070: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 8006074: d828 bhi.n 80060c8 8006076: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800607a: d01a beq.n 80060b2 800607c: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8006080: d822 bhi.n 80060c8 8006082: 2b00 cmp r3, #0 8006084: d003 beq.n 800608e 8006086: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800608a: d007 beq.n 800609c 800608c: e01c b.n 80060c8 { case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ /* Enable PLL1Q Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800608e: 4bb8 ldr r3, [pc, #736] @ (8006370 ) 8006090: 6adb ldr r3, [r3, #44] @ 0x2c 8006092: 4ab7 ldr r2, [pc, #732] @ (8006370 ) 8006094: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8006098: 62d3 str r3, [r2, #44] @ 0x2c /* SPDIFRX clock source configuration done later after clock selection check */ break; 800609a: e01a b.n 80060d2 case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800609c: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80060a0: 3308 adds r3, #8 80060a2: 2102 movs r1, #2 80060a4: 4618 mov r0, r3 80060a6: f002 fb61 bl 800876c 80060aa: 4603 mov r3, r0 80060ac: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* SPDIFRX clock source configuration done later after clock selection check */ break; 80060b0: e00f b.n 80060d2 case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 80060b2: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80060b6: 3328 adds r3, #40 @ 0x28 80060b8: 2102 movs r1, #2 80060ba: 4618 mov r0, r3 80060bc: f002 fc08 bl 80088d0 80060c0: 4603 mov r3, r0 80060c2: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* SPDIFRX clock source configuration done later after clock selection check */ break; 80060c6: e004 b.n 80060d2 /* Internal OSC clock is used as source of SPDIFRX clock*/ /* SPDIFRX clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80060c8: 2301 movs r3, #1 80060ca: f887 3127 strb.w r3, [r7, #295] @ 0x127 break; 80060ce: e000 b.n 80060d2 break; 80060d0: bf00 nop } if (ret == HAL_OK) 80060d2: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 80060d6: 2b00 cmp r3, #0 80060d8: d10a bne.n 80060f0 { /* Set the source of SPDIFRX clock*/ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); 80060da: 4ba5 ldr r3, [pc, #660] @ (8006370 ) 80060dc: 6d1b ldr r3, [r3, #80] @ 0x50 80060de: f423 1140 bic.w r1, r3, #3145728 @ 0x300000 80060e2: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80060e6: 6e9b ldr r3, [r3, #104] @ 0x68 80060e8: 4aa1 ldr r2, [pc, #644] @ (8006370 ) 80060ea: 430b orrs r3, r1 80060ec: 6513 str r3, [r2, #80] @ 0x50 80060ee: e003 b.n 80060f8 } else { /* set overall return value */ status = ret; 80060f0: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 80060f4: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } /*---------------------------- SAI1 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 80060f8: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80060fc: e9d3 2300 ldrd r2, r3, [r3] 8006100: f402 7880 and.w r8, r2, #256 @ 0x100 8006104: f04f 0900 mov.w r9, #0 8006108: ea58 0309 orrs.w r3, r8, r9 800610c: d047 beq.n 800619e { switch (PeriphClkInit->Sai1ClockSelection) 800610e: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006112: 6d9b ldr r3, [r3, #88] @ 0x58 8006114: 2b04 cmp r3, #4 8006116: d82a bhi.n 800616e 8006118: a201 add r2, pc, #4 @ (adr r2, 8006120 ) 800611a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800611e: bf00 nop 8006120: 08006135 .word 0x08006135 8006124: 08006143 .word 0x08006143 8006128: 08006159 .word 0x08006159 800612c: 08006177 .word 0x08006177 8006130: 08006177 .word 0x08006177 { case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8006134: 4b8e ldr r3, [pc, #568] @ (8006370 ) 8006136: 6adb ldr r3, [r3, #44] @ 0x2c 8006138: 4a8d ldr r2, [pc, #564] @ (8006370 ) 800613a: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800613e: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 8006140: e01a b.n 8006178 case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 8006142: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006146: 3308 adds r3, #8 8006148: 2100 movs r1, #0 800614a: 4618 mov r0, r3 800614c: f002 fb0e bl 800876c 8006150: 4603 mov r3, r0 8006152: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* SAI1 clock source configuration done later after clock selection check */ break; 8006156: e00f b.n 8006178 case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 8006158: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800615c: 3328 adds r3, #40 @ 0x28 800615e: 2100 movs r1, #0 8006160: 4618 mov r0, r3 8006162: f002 fbb5 bl 80088d0 8006166: 4603 mov r3, r0 8006168: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* SAI1 clock source configuration done later after clock selection check */ break; 800616c: e004 b.n 8006178 /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ /* SAI1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800616e: 2301 movs r3, #1 8006170: f887 3127 strb.w r3, [r7, #295] @ 0x127 break; 8006174: e000 b.n 8006178 break; 8006176: bf00 nop } if (ret == HAL_OK) 8006178: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 800617c: 2b00 cmp r3, #0 800617e: d10a bne.n 8006196 { /* Set the source of SAI1 clock*/ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 8006180: 4b7b ldr r3, [pc, #492] @ (8006370 ) 8006182: 6d1b ldr r3, [r3, #80] @ 0x50 8006184: f023 0107 bic.w r1, r3, #7 8006188: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800618c: 6d9b ldr r3, [r3, #88] @ 0x58 800618e: 4a78 ldr r2, [pc, #480] @ (8006370 ) 8006190: 430b orrs r3, r1 8006192: 6513 str r3, [r2, #80] @ 0x50 8006194: e003 b.n 800619e } else { /* set overall return value */ status = ret; 8006196: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 800619a: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } #if defined(SAI3) /*---------------------------- SAI2/3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23) 800619e: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80061a2: e9d3 2300 ldrd r2, r3, [r3] 80061a6: f402 7a00 and.w sl, r2, #512 @ 0x200 80061aa: f04f 0b00 mov.w fp, #0 80061ae: ea5a 030b orrs.w r3, sl, fp 80061b2: d04c beq.n 800624e { switch (PeriphClkInit->Sai23ClockSelection) 80061b4: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80061b8: 6ddb ldr r3, [r3, #92] @ 0x5c 80061ba: f5b3 7f80 cmp.w r3, #256 @ 0x100 80061be: d030 beq.n 8006222 80061c0: f5b3 7f80 cmp.w r3, #256 @ 0x100 80061c4: d829 bhi.n 800621a 80061c6: 2bc0 cmp r3, #192 @ 0xc0 80061c8: d02d beq.n 8006226 80061ca: 2bc0 cmp r3, #192 @ 0xc0 80061cc: d825 bhi.n 800621a 80061ce: 2b80 cmp r3, #128 @ 0x80 80061d0: d018 beq.n 8006204 80061d2: 2b80 cmp r3, #128 @ 0x80 80061d4: d821 bhi.n 800621a 80061d6: 2b00 cmp r3, #0 80061d8: d002 beq.n 80061e0 80061da: 2b40 cmp r3, #64 @ 0x40 80061dc: d007 beq.n 80061ee 80061de: e01c b.n 800621a { case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80061e0: 4b63 ldr r3, [pc, #396] @ (8006370 ) 80061e2: 6adb ldr r3, [r3, #44] @ 0x2c 80061e4: 4a62 ldr r2, [pc, #392] @ (8006370 ) 80061e6: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80061ea: 62d3 str r3, [r2, #44] @ 0x2c /* SAI2/3 clock source configuration done later after clock selection check */ break; 80061ec: e01c b.n 8006228 case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 80061ee: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80061f2: 3308 adds r3, #8 80061f4: 2100 movs r1, #0 80061f6: 4618 mov r0, r3 80061f8: f002 fab8 bl 800876c 80061fc: 4603 mov r3, r0 80061fe: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* SAI2/3 clock source configuration done later after clock selection check */ break; 8006202: e011 b.n 8006228 case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 8006204: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006208: 3328 adds r3, #40 @ 0x28 800620a: 2100 movs r1, #0 800620c: 4618 mov r0, r3 800620e: f002 fb5f bl 80088d0 8006212: 4603 mov r3, r0 8006214: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* SAI2/3 clock source configuration done later after clock selection check */ break; 8006218: e006 b.n 8006228 /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */ /* SAI2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800621a: 2301 movs r3, #1 800621c: f887 3127 strb.w r3, [r7, #295] @ 0x127 break; 8006220: e002 b.n 8006228 break; 8006222: bf00 nop 8006224: e000 b.n 8006228 break; 8006226: bf00 nop } if (ret == HAL_OK) 8006228: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 800622c: 2b00 cmp r3, #0 800622e: d10a bne.n 8006246 { /* Set the source of SAI2/3 clock*/ __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection); 8006230: 4b4f ldr r3, [pc, #316] @ (8006370 ) 8006232: 6d1b ldr r3, [r3, #80] @ 0x50 8006234: f423 71e0 bic.w r1, r3, #448 @ 0x1c0 8006238: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800623c: 6ddb ldr r3, [r3, #92] @ 0x5c 800623e: 4a4c ldr r2, [pc, #304] @ (8006370 ) 8006240: 430b orrs r3, r1 8006242: 6513 str r3, [r2, #80] @ 0x50 8006244: e003 b.n 800624e } else { /* set overall return value */ status = ret; 8006246: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 800624a: f887 3126 strb.w r3, [r7, #294] @ 0x126 } #endif /*SAI2B*/ #if defined(SAI4) /*---------------------------- SAI4A configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) 800624e: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006252: e9d3 2300 ldrd r2, r3, [r3] 8006256: f402 6380 and.w r3, r2, #1024 @ 0x400 800625a: f8c7 3108 str.w r3, [r7, #264] @ 0x108 800625e: 2300 movs r3, #0 8006260: f8c7 310c str.w r3, [r7, #268] @ 0x10c 8006264: e9d7 1242 ldrd r1, r2, [r7, #264] @ 0x108 8006268: 460b mov r3, r1 800626a: 4313 orrs r3, r2 800626c: d053 beq.n 8006316 { switch (PeriphClkInit->Sai4AClockSelection) 800626e: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006272: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8 8006276: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800627a: d035 beq.n 80062e8 800627c: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 8006280: d82e bhi.n 80062e0 8006282: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 8006286: d031 beq.n 80062ec 8006288: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800628c: d828 bhi.n 80062e0 800628e: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8006292: d01a beq.n 80062ca 8006294: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8006298: d822 bhi.n 80062e0 800629a: 2b00 cmp r3, #0 800629c: d003 beq.n 80062a6 800629e: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 80062a2: d007 beq.n 80062b4 80062a4: e01c b.n 80062e0 { case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80062a6: 4b32 ldr r3, [pc, #200] @ (8006370 ) 80062a8: 6adb ldr r3, [r3, #44] @ 0x2c 80062aa: 4a31 ldr r2, [pc, #196] @ (8006370 ) 80062ac: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80062b0: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 80062b2: e01c b.n 80062ee case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 80062b4: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80062b8: 3308 adds r3, #8 80062ba: 2100 movs r1, #0 80062bc: 4618 mov r0, r3 80062be: f002 fa55 bl 800876c 80062c2: 4603 mov r3, r0 80062c4: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* SAI2 clock source configuration done later after clock selection check */ break; 80062c8: e011 b.n 80062ee case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 80062ca: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80062ce: 3328 adds r3, #40 @ 0x28 80062d0: 2100 movs r1, #0 80062d2: 4618 mov r0, r3 80062d4: f002 fafc bl 80088d0 80062d8: 4603 mov r3, r0 80062da: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* SAI1 clock source configuration done later after clock selection check */ break; 80062de: e006 b.n 80062ee /* SAI4A clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 80062e0: 2301 movs r3, #1 80062e2: f887 3127 strb.w r3, [r7, #295] @ 0x127 break; 80062e6: e002 b.n 80062ee break; 80062e8: bf00 nop 80062ea: e000 b.n 80062ee break; 80062ec: bf00 nop } if (ret == HAL_OK) 80062ee: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 80062f2: 2b00 cmp r3, #0 80062f4: d10b bne.n 800630e { /* Set the source of SAI4A clock*/ __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection); 80062f6: 4b1e ldr r3, [pc, #120] @ (8006370 ) 80062f8: 6d9b ldr r3, [r3, #88] @ 0x58 80062fa: f423 0160 bic.w r1, r3, #14680064 @ 0xe00000 80062fe: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006302: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8 8006306: 4a1a ldr r2, [pc, #104] @ (8006370 ) 8006308: 430b orrs r3, r1 800630a: 6593 str r3, [r2, #88] @ 0x58 800630c: e003 b.n 8006316 } else { /* set overall return value */ status = ret; 800630e: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8006312: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } /*---------------------------- SAI4B configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) 8006316: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800631a: e9d3 2300 ldrd r2, r3, [r3] 800631e: f402 6300 and.w r3, r2, #2048 @ 0x800 8006322: f8c7 3100 str.w r3, [r7, #256] @ 0x100 8006326: 2300 movs r3, #0 8006328: f8c7 3104 str.w r3, [r7, #260] @ 0x104 800632c: e9d7 1240 ldrd r1, r2, [r7, #256] @ 0x100 8006330: 460b mov r3, r1 8006332: 4313 orrs r3, r2 8006334: d056 beq.n 80063e4 { switch (PeriphClkInit->Sai4BClockSelection) 8006336: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800633a: f8d3 30ac ldr.w r3, [r3, #172] @ 0xac 800633e: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 8006342: d038 beq.n 80063b6 8006344: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 8006348: d831 bhi.n 80063ae 800634a: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800634e: d034 beq.n 80063ba 8006350: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 8006354: d82b bhi.n 80063ae 8006356: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800635a: d01d beq.n 8006398 800635c: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 8006360: d825 bhi.n 80063ae 8006362: 2b00 cmp r3, #0 8006364: d006 beq.n 8006374 8006366: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800636a: d00a beq.n 8006382 800636c: e01f b.n 80063ae 800636e: bf00 nop 8006370: 58024400 .word 0x58024400 { case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8006374: 4ba2 ldr r3, [pc, #648] @ (8006600 ) 8006376: 6adb ldr r3, [r3, #44] @ 0x2c 8006378: 4aa1 ldr r2, [pc, #644] @ (8006600 ) 800637a: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800637e: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 8006380: e01c b.n 80063bc case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 8006382: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006386: 3308 adds r3, #8 8006388: 2100 movs r1, #0 800638a: 4618 mov r0, r3 800638c: f002 f9ee bl 800876c 8006390: 4603 mov r3, r0 8006392: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* SAI2 clock source configuration done later after clock selection check */ break; 8006396: e011 b.n 80063bc case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 8006398: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800639c: 3328 adds r3, #40 @ 0x28 800639e: 2100 movs r1, #0 80063a0: 4618 mov r0, r3 80063a2: f002 fa95 bl 80088d0 80063a6: 4603 mov r3, r0 80063a8: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* SAI1 clock source configuration done later after clock selection check */ break; 80063ac: e006 b.n 80063bc /* SAI4B clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 80063ae: 2301 movs r3, #1 80063b0: f887 3127 strb.w r3, [r7, #295] @ 0x127 break; 80063b4: e002 b.n 80063bc break; 80063b6: bf00 nop 80063b8: e000 b.n 80063bc break; 80063ba: bf00 nop } if (ret == HAL_OK) 80063bc: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 80063c0: 2b00 cmp r3, #0 80063c2: d10b bne.n 80063dc { /* Set the source of SAI4B clock*/ __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection); 80063c4: 4b8e ldr r3, [pc, #568] @ (8006600 ) 80063c6: 6d9b ldr r3, [r3, #88] @ 0x58 80063c8: f023 61e0 bic.w r1, r3, #117440512 @ 0x7000000 80063cc: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80063d0: f8d3 30ac ldr.w r3, [r3, #172] @ 0xac 80063d4: 4a8a ldr r2, [pc, #552] @ (8006600 ) 80063d6: 430b orrs r3, r1 80063d8: 6593 str r3, [r2, #88] @ 0x58 80063da: e003 b.n 80063e4 } else { /* set overall return value */ status = ret; 80063dc: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 80063e0: f887 3126 strb.w r3, [r7, #294] @ 0x126 } #endif /*SAI4*/ #if defined(QUADSPI) /*---------------------------- QSPI configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) 80063e4: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80063e8: e9d3 2300 ldrd r2, r3, [r3] 80063ec: f002 7300 and.w r3, r2, #33554432 @ 0x2000000 80063f0: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 80063f4: 2300 movs r3, #0 80063f6: f8c7 30fc str.w r3, [r7, #252] @ 0xfc 80063fa: e9d7 123e ldrd r1, r2, [r7, #248] @ 0xf8 80063fe: 460b mov r3, r1 8006400: 4313 orrs r3, r2 8006402: d03a beq.n 800647a { switch (PeriphClkInit->QspiClockSelection) 8006404: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006408: 6cdb ldr r3, [r3, #76] @ 0x4c 800640a: 2b30 cmp r3, #48 @ 0x30 800640c: d01f beq.n 800644e 800640e: 2b30 cmp r3, #48 @ 0x30 8006410: d819 bhi.n 8006446 8006412: 2b20 cmp r3, #32 8006414: d00c beq.n 8006430 8006416: 2b20 cmp r3, #32 8006418: d815 bhi.n 8006446 800641a: 2b00 cmp r3, #0 800641c: d019 beq.n 8006452 800641e: 2b10 cmp r3, #16 8006420: d111 bne.n 8006446 { case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/ /* Enable QSPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8006422: 4b77 ldr r3, [pc, #476] @ (8006600 ) 8006424: 6adb ldr r3, [r3, #44] @ 0x2c 8006426: 4a76 ldr r2, [pc, #472] @ (8006600 ) 8006428: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800642c: 62d3 str r3, [r2, #44] @ 0x2c /* QSPI clock source configuration done later after clock selection check */ break; 800642e: e011 b.n 8006454 case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 8006430: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006434: 3308 adds r3, #8 8006436: 2102 movs r1, #2 8006438: 4618 mov r0, r3 800643a: f002 f997 bl 800876c 800643e: 4603 mov r3, r0 8006440: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* QSPI clock source configuration done later after clock selection check */ break; 8006444: e006 b.n 8006454 case RCC_QSPICLKSOURCE_D1HCLK: /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */ break; default: ret = HAL_ERROR; 8006446: 2301 movs r3, #1 8006448: f887 3127 strb.w r3, [r7, #295] @ 0x127 break; 800644c: e002 b.n 8006454 break; 800644e: bf00 nop 8006450: e000 b.n 8006454 break; 8006452: bf00 nop } if (ret == HAL_OK) 8006454: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8006458: 2b00 cmp r3, #0 800645a: d10a bne.n 8006472 { /* Set the source of QSPI clock*/ __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection); 800645c: 4b68 ldr r3, [pc, #416] @ (8006600 ) 800645e: 6cdb ldr r3, [r3, #76] @ 0x4c 8006460: f023 0130 bic.w r1, r3, #48 @ 0x30 8006464: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006468: 6cdb ldr r3, [r3, #76] @ 0x4c 800646a: 4a65 ldr r2, [pc, #404] @ (8006600 ) 800646c: 430b orrs r3, r1 800646e: 64d3 str r3, [r2, #76] @ 0x4c 8006470: e003 b.n 800647a } else { /* set overall return value */ status = ret; 8006472: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8006476: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } #endif /*OCTOSPI*/ /*---------------------------- SPI1/2/3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) 800647a: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800647e: e9d3 2300 ldrd r2, r3, [r3] 8006482: f402 5380 and.w r3, r2, #4096 @ 0x1000 8006486: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0 800648a: 2300 movs r3, #0 800648c: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4 8006490: e9d7 123c ldrd r1, r2, [r7, #240] @ 0xf0 8006494: 460b mov r3, r1 8006496: 4313 orrs r3, r2 8006498: d051 beq.n 800653e { switch (PeriphClkInit->Spi123ClockSelection) 800649a: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800649e: 6e1b ldr r3, [r3, #96] @ 0x60 80064a0: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 80064a4: d035 beq.n 8006512 80064a6: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 80064aa: d82e bhi.n 800650a 80064ac: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 80064b0: d031 beq.n 8006516 80064b2: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 80064b6: d828 bhi.n 800650a 80064b8: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80064bc: d01a beq.n 80064f4 80064be: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80064c2: d822 bhi.n 800650a 80064c4: 2b00 cmp r3, #0 80064c6: d003 beq.n 80064d0 80064c8: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80064cc: d007 beq.n 80064de 80064ce: e01c b.n 800650a { case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */ /* Enable SPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80064d0: 4b4b ldr r3, [pc, #300] @ (8006600 ) 80064d2: 6adb ldr r3, [r3, #44] @ 0x2c 80064d4: 4a4a ldr r2, [pc, #296] @ (8006600 ) 80064d6: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80064da: 62d3 str r3, [r2, #44] @ 0x2c /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 80064dc: e01c b.n 8006518 case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 80064de: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80064e2: 3308 adds r3, #8 80064e4: 2100 movs r1, #0 80064e6: 4618 mov r0, r3 80064e8: f002 f940 bl 800876c 80064ec: 4603 mov r3, r0 80064ee: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 80064f2: e011 b.n 8006518 case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 80064f4: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80064f8: 3328 adds r3, #40 @ 0x28 80064fa: 2100 movs r1, #0 80064fc: 4618 mov r0, r3 80064fe: f002 f9e7 bl 80088d0 8006502: 4603 mov r3, r0 8006504: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 8006508: e006 b.n 8006518 /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */ /* SPI1/2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800650a: 2301 movs r3, #1 800650c: f887 3127 strb.w r3, [r7, #295] @ 0x127 break; 8006510: e002 b.n 8006518 break; 8006512: bf00 nop 8006514: e000 b.n 8006518 break; 8006516: bf00 nop } if (ret == HAL_OK) 8006518: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 800651c: 2b00 cmp r3, #0 800651e: d10a bne.n 8006536 { /* Set the source of SPI1/2/3 clock*/ __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); 8006520: 4b37 ldr r3, [pc, #220] @ (8006600 ) 8006522: 6d1b ldr r3, [r3, #80] @ 0x50 8006524: f423 41e0 bic.w r1, r3, #28672 @ 0x7000 8006528: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800652c: 6e1b ldr r3, [r3, #96] @ 0x60 800652e: 4a34 ldr r2, [pc, #208] @ (8006600 ) 8006530: 430b orrs r3, r1 8006532: 6513 str r3, [r2, #80] @ 0x50 8006534: e003 b.n 800653e } else { /* set overall return value */ status = ret; 8006536: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 800653a: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } /*---------------------------- SPI4/5 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) 800653e: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006542: e9d3 2300 ldrd r2, r3, [r3] 8006546: f402 5300 and.w r3, r2, #8192 @ 0x2000 800654a: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 800654e: 2300 movs r3, #0 8006550: f8c7 30ec str.w r3, [r7, #236] @ 0xec 8006554: e9d7 123a ldrd r1, r2, [r7, #232] @ 0xe8 8006558: 460b mov r3, r1 800655a: 4313 orrs r3, r2 800655c: d056 beq.n 800660c { switch (PeriphClkInit->Spi45ClockSelection) 800655e: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006562: 6e5b ldr r3, [r3, #100] @ 0x64 8006564: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8006568: d033 beq.n 80065d2 800656a: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800656e: d82c bhi.n 80065ca 8006570: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8006574: d02f beq.n 80065d6 8006576: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800657a: d826 bhi.n 80065ca 800657c: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8006580: d02b beq.n 80065da 8006582: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8006586: d820 bhi.n 80065ca 8006588: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800658c: d012 beq.n 80065b4 800658e: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8006592: d81a bhi.n 80065ca 8006594: 2b00 cmp r3, #0 8006596: d022 beq.n 80065de 8006598: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800659c: d115 bne.n 80065ca /* SPI4/5 clock source configuration done later after clock selection check */ break; case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800659e: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80065a2: 3308 adds r3, #8 80065a4: 2101 movs r1, #1 80065a6: 4618 mov r0, r3 80065a8: f002 f8e0 bl 800876c 80065ac: 4603 mov r3, r0 80065ae: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* SPI4/5 clock source configuration done later after clock selection check */ break; 80065b2: e015 b.n 80065e0 case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 80065b4: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80065b8: 3328 adds r3, #40 @ 0x28 80065ba: 2101 movs r1, #1 80065bc: 4618 mov r0, r3 80065be: f002 f987 bl 80088d0 80065c2: 4603 mov r3, r0 80065c4: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* SPI4/5 clock source configuration done later after clock selection check */ break; 80065c8: e00a b.n 80065e0 /* HSE, oscillator is used as source of SPI4/5 clock */ /* SPI4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80065ca: 2301 movs r3, #1 80065cc: f887 3127 strb.w r3, [r7, #295] @ 0x127 break; 80065d0: e006 b.n 80065e0 break; 80065d2: bf00 nop 80065d4: e004 b.n 80065e0 break; 80065d6: bf00 nop 80065d8: e002 b.n 80065e0 break; 80065da: bf00 nop 80065dc: e000 b.n 80065e0 break; 80065de: bf00 nop } if (ret == HAL_OK) 80065e0: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 80065e4: 2b00 cmp r3, #0 80065e6: d10d bne.n 8006604 { /* Set the source of SPI4/5 clock*/ __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); 80065e8: 4b05 ldr r3, [pc, #20] @ (8006600 ) 80065ea: 6d1b ldr r3, [r3, #80] @ 0x50 80065ec: f423 21e0 bic.w r1, r3, #458752 @ 0x70000 80065f0: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80065f4: 6e5b ldr r3, [r3, #100] @ 0x64 80065f6: 4a02 ldr r2, [pc, #8] @ (8006600 ) 80065f8: 430b orrs r3, r1 80065fa: 6513 str r3, [r2, #80] @ 0x50 80065fc: e006 b.n 800660c 80065fe: bf00 nop 8006600: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 8006604: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8006608: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } /*---------------------------- SPI6 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) 800660c: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006610: e9d3 2300 ldrd r2, r3, [r3] 8006614: f402 4380 and.w r3, r2, #16384 @ 0x4000 8006618: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 800661c: 2300 movs r3, #0 800661e: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 8006622: e9d7 1238 ldrd r1, r2, [r7, #224] @ 0xe0 8006626: 460b mov r3, r1 8006628: 4313 orrs r3, r2 800662a: d055 beq.n 80066d8 { switch (PeriphClkInit->Spi6ClockSelection) 800662c: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006630: f8d3 30b0 ldr.w r3, [r3, #176] @ 0xb0 8006634: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8006638: d033 beq.n 80066a2 800663a: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800663e: d82c bhi.n 800669a 8006640: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8006644: d02f beq.n 80066a6 8006646: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800664a: d826 bhi.n 800669a 800664c: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 8006650: d02b beq.n 80066aa 8006652: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 8006656: d820 bhi.n 800669a 8006658: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800665c: d012 beq.n 8006684 800665e: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8006662: d81a bhi.n 800669a 8006664: 2b00 cmp r3, #0 8006666: d022 beq.n 80066ae 8006668: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800666c: d115 bne.n 800669a /* SPI6 clock source configuration done later after clock selection check */ break; case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800666e: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006672: 3308 adds r3, #8 8006674: 2101 movs r1, #1 8006676: 4618 mov r0, r3 8006678: f002 f878 bl 800876c 800667c: 4603 mov r3, r0 800667e: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* SPI6 clock source configuration done later after clock selection check */ break; 8006682: e015 b.n 80066b0 case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 8006684: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006688: 3328 adds r3, #40 @ 0x28 800668a: 2101 movs r1, #1 800668c: 4618 mov r0, r3 800668e: f002 f91f bl 80088d0 8006692: 4603 mov r3, r0 8006694: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* SPI6 clock source configuration done later after clock selection check */ break; 8006698: e00a b.n 80066b0 /* SPI6 clock source configuration done later after clock selection check */ break; #endif default: ret = HAL_ERROR; 800669a: 2301 movs r3, #1 800669c: f887 3127 strb.w r3, [r7, #295] @ 0x127 break; 80066a0: e006 b.n 80066b0 break; 80066a2: bf00 nop 80066a4: e004 b.n 80066b0 break; 80066a6: bf00 nop 80066a8: e002 b.n 80066b0 break; 80066aa: bf00 nop 80066ac: e000 b.n 80066b0 break; 80066ae: bf00 nop } if (ret == HAL_OK) 80066b0: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 80066b4: 2b00 cmp r3, #0 80066b6: d10b bne.n 80066d0 { /* Set the source of SPI6 clock*/ __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); 80066b8: 4ba3 ldr r3, [pc, #652] @ (8006948 ) 80066ba: 6d9b ldr r3, [r3, #88] @ 0x58 80066bc: f023 41e0 bic.w r1, r3, #1879048192 @ 0x70000000 80066c0: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80066c4: f8d3 30b0 ldr.w r3, [r3, #176] @ 0xb0 80066c8: 4a9f ldr r2, [pc, #636] @ (8006948 ) 80066ca: 430b orrs r3, r1 80066cc: 6593 str r3, [r2, #88] @ 0x58 80066ce: e003 b.n 80066d8 } else { /* set overall return value */ status = ret; 80066d0: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 80066d4: f887 3126 strb.w r3, [r7, #294] @ 0x126 } #endif /*DSI*/ #if defined(FDCAN1) || defined(FDCAN2) /*---------------------------- FDCAN configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 80066d8: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80066dc: e9d3 2300 ldrd r2, r3, [r3] 80066e0: f402 4300 and.w r3, r2, #32768 @ 0x8000 80066e4: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 80066e8: 2300 movs r3, #0 80066ea: f8c7 30dc str.w r3, [r7, #220] @ 0xdc 80066ee: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8 80066f2: 460b mov r3, r1 80066f4: 4313 orrs r3, r2 80066f6: d037 beq.n 8006768 { switch (PeriphClkInit->FdcanClockSelection) 80066f8: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80066fc: 6f1b ldr r3, [r3, #112] @ 0x70 80066fe: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8006702: d00e beq.n 8006722 8006704: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8006708: d816 bhi.n 8006738 800670a: 2b00 cmp r3, #0 800670c: d018 beq.n 8006740 800670e: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8006712: d111 bne.n 8006738 { case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/ /* Enable FDCAN Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8006714: 4b8c ldr r3, [pc, #560] @ (8006948 ) 8006716: 6adb ldr r3, [r3, #44] @ 0x2c 8006718: 4a8b ldr r2, [pc, #556] @ (8006948 ) 800671a: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800671e: 62d3 str r3, [r2, #44] @ 0x2c /* FDCAN clock source configuration done later after clock selection check */ break; 8006720: e00f b.n 8006742 case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 8006722: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006726: 3308 adds r3, #8 8006728: 2101 movs r1, #1 800672a: 4618 mov r0, r3 800672c: f002 f81e bl 800876c 8006730: 4603 mov r3, r0 8006732: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* FDCAN clock source configuration done later after clock selection check */ break; 8006736: e004 b.n 8006742 /* HSE is used as clock source for FDCAN*/ /* FDCAN clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8006738: 2301 movs r3, #1 800673a: f887 3127 strb.w r3, [r7, #295] @ 0x127 break; 800673e: e000 b.n 8006742 break; 8006740: bf00 nop } if (ret == HAL_OK) 8006742: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8006746: 2b00 cmp r3, #0 8006748: d10a bne.n 8006760 { /* Set the source of FDCAN clock*/ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 800674a: 4b7f ldr r3, [pc, #508] @ (8006948 ) 800674c: 6d1b ldr r3, [r3, #80] @ 0x50 800674e: f023 5140 bic.w r1, r3, #805306368 @ 0x30000000 8006752: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006756: 6f1b ldr r3, [r3, #112] @ 0x70 8006758: 4a7b ldr r2, [pc, #492] @ (8006948 ) 800675a: 430b orrs r3, r1 800675c: 6513 str r3, [r2, #80] @ 0x50 800675e: e003 b.n 8006768 } else { /* set overall return value */ status = ret; 8006760: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8006764: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } #endif /*FDCAN1 || FDCAN2*/ /*---------------------------- FMC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) 8006768: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800676c: e9d3 2300 ldrd r2, r3, [r3] 8006770: f002 7380 and.w r3, r2, #16777216 @ 0x1000000 8006774: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8006778: 2300 movs r3, #0 800677a: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 800677e: e9d7 1234 ldrd r1, r2, [r7, #208] @ 0xd0 8006782: 460b mov r3, r1 8006784: 4313 orrs r3, r2 8006786: d039 beq.n 80067fc { switch (PeriphClkInit->FmcClockSelection) 8006788: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800678c: 6c9b ldr r3, [r3, #72] @ 0x48 800678e: 2b03 cmp r3, #3 8006790: d81c bhi.n 80067cc 8006792: a201 add r2, pc, #4 @ (adr r2, 8006798 ) 8006794: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8006798: 080067d5 .word 0x080067d5 800679c: 080067a9 .word 0x080067a9 80067a0: 080067b7 .word 0x080067b7 80067a4: 080067d5 .word 0x080067d5 { case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/ /* Enable FMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80067a8: 4b67 ldr r3, [pc, #412] @ (8006948 ) 80067aa: 6adb ldr r3, [r3, #44] @ 0x2c 80067ac: 4a66 ldr r2, [pc, #408] @ (8006948 ) 80067ae: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80067b2: 62d3 str r3, [r2, #44] @ 0x2c /* FMC clock source configuration done later after clock selection check */ break; 80067b4: e00f b.n 80067d6 case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 80067b6: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80067ba: 3308 adds r3, #8 80067bc: 2102 movs r1, #2 80067be: 4618 mov r0, r3 80067c0: f001 ffd4 bl 800876c 80067c4: 4603 mov r3, r0 80067c6: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* FMC clock source configuration done later after clock selection check */ break; 80067ca: e004 b.n 80067d6 case RCC_FMCCLKSOURCE_HCLK: /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ break; default: ret = HAL_ERROR; 80067cc: 2301 movs r3, #1 80067ce: f887 3127 strb.w r3, [r7, #295] @ 0x127 break; 80067d2: e000 b.n 80067d6 break; 80067d4: bf00 nop } if (ret == HAL_OK) 80067d6: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 80067da: 2b00 cmp r3, #0 80067dc: d10a bne.n 80067f4 { /* Set the source of FMC clock*/ __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); 80067de: 4b5a ldr r3, [pc, #360] @ (8006948 ) 80067e0: 6cdb ldr r3, [r3, #76] @ 0x4c 80067e2: f023 0103 bic.w r1, r3, #3 80067e6: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80067ea: 6c9b ldr r3, [r3, #72] @ 0x48 80067ec: 4a56 ldr r2, [pc, #344] @ (8006948 ) 80067ee: 430b orrs r3, r1 80067f0: 64d3 str r3, [r2, #76] @ 0x4c 80067f2: e003 b.n 80067fc } else { /* set overall return value */ status = ret; 80067f4: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 80067f8: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } /*---------------------------- RTC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 80067fc: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006800: e9d3 2300 ldrd r2, r3, [r3] 8006804: f402 0380 and.w r3, r2, #4194304 @ 0x400000 8006808: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 800680c: 2300 movs r3, #0 800680e: f8c7 30cc str.w r3, [r7, #204] @ 0xcc 8006812: e9d7 1232 ldrd r1, r2, [r7, #200] @ 0xc8 8006816: 460b mov r3, r1 8006818: 4313 orrs r3, r2 800681a: f000 809f beq.w 800695c { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 800681e: 4b4b ldr r3, [pc, #300] @ (800694c ) 8006820: 681b ldr r3, [r3, #0] 8006822: 4a4a ldr r2, [pc, #296] @ (800694c ) 8006824: f443 7380 orr.w r3, r3, #256 @ 0x100 8006828: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800682a: f7fa ff5b bl 80016e4 800682e: f8c7 0120 str.w r0, [r7, #288] @ 0x120 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 8006832: e00b b.n 800684c { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8006834: f7fa ff56 bl 80016e4 8006838: 4602 mov r2, r0 800683a: f8d7 3120 ldr.w r3, [r7, #288] @ 0x120 800683e: 1ad3 subs r3, r2, r3 8006840: 2b64 cmp r3, #100 @ 0x64 8006842: d903 bls.n 800684c { ret = HAL_TIMEOUT; 8006844: 2303 movs r3, #3 8006846: f887 3127 strb.w r3, [r7, #295] @ 0x127 break; 800684a: e005 b.n 8006858 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800684c: 4b3f ldr r3, [pc, #252] @ (800694c ) 800684e: 681b ldr r3, [r3, #0] 8006850: f403 7380 and.w r3, r3, #256 @ 0x100 8006854: 2b00 cmp r3, #0 8006856: d0ed beq.n 8006834 } } if (ret == HAL_OK) 8006858: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 800685c: 2b00 cmp r3, #0 800685e: d179 bne.n 8006954 { /* Reset the Backup domain only if the RTC Clock source selection is modified */ if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) 8006860: 4b39 ldr r3, [pc, #228] @ (8006948 ) 8006862: 6f1a ldr r2, [r3, #112] @ 0x70 8006864: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006868: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800686c: 4053 eors r3, r2 800686e: f403 7340 and.w r3, r3, #768 @ 0x300 8006872: 2b00 cmp r3, #0 8006874: d015 beq.n 80068a2 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8006876: 4b34 ldr r3, [pc, #208] @ (8006948 ) 8006878: 6f1b ldr r3, [r3, #112] @ 0x70 800687a: f423 7340 bic.w r3, r3, #768 @ 0x300 800687e: f8c7 311c str.w r3, [r7, #284] @ 0x11c /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8006882: 4b31 ldr r3, [pc, #196] @ (8006948 ) 8006884: 6f1b ldr r3, [r3, #112] @ 0x70 8006886: 4a30 ldr r2, [pc, #192] @ (8006948 ) 8006888: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800688c: 6713 str r3, [r2, #112] @ 0x70 __HAL_RCC_BACKUPRESET_RELEASE(); 800688e: 4b2e ldr r3, [pc, #184] @ (8006948 ) 8006890: 6f1b ldr r3, [r3, #112] @ 0x70 8006892: 4a2d ldr r2, [pc, #180] @ (8006948 ) 8006894: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8006898: 6713 str r3, [r2, #112] @ 0x70 /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg; 800689a: 4a2b ldr r2, [pc, #172] @ (8006948 ) 800689c: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 80068a0: 6713 str r3, [r2, #112] @ 0x70 } /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) 80068a2: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80068a6: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 80068aa: f5b3 7f80 cmp.w r3, #256 @ 0x100 80068ae: d118 bne.n 80068e2 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80068b0: f7fa ff18 bl 80016e4 80068b4: f8c7 0120 str.w r0, [r7, #288] @ 0x120 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 80068b8: e00d b.n 80068d6 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80068ba: f7fa ff13 bl 80016e4 80068be: 4602 mov r2, r0 80068c0: f8d7 3120 ldr.w r3, [r7, #288] @ 0x120 80068c4: 1ad2 subs r2, r2, r3 80068c6: f241 3388 movw r3, #5000 @ 0x1388 80068ca: 429a cmp r2, r3 80068cc: d903 bls.n 80068d6 { ret = HAL_TIMEOUT; 80068ce: 2303 movs r3, #3 80068d0: f887 3127 strb.w r3, [r7, #295] @ 0x127 break; 80068d4: e005 b.n 80068e2 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 80068d6: 4b1c ldr r3, [pc, #112] @ (8006948 ) 80068d8: 6f1b ldr r3, [r3, #112] @ 0x70 80068da: f003 0302 and.w r3, r3, #2 80068de: 2b00 cmp r3, #0 80068e0: d0eb beq.n 80068ba } } } if (ret == HAL_OK) 80068e2: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 80068e6: 2b00 cmp r3, #0 80068e8: d129 bne.n 800693e { __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 80068ea: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80068ee: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 80068f2: f403 7340 and.w r3, r3, #768 @ 0x300 80068f6: f5b3 7f40 cmp.w r3, #768 @ 0x300 80068fa: d10e bne.n 800691a 80068fc: 4b12 ldr r3, [pc, #72] @ (8006948 ) 80068fe: 691b ldr r3, [r3, #16] 8006900: f423 517c bic.w r1, r3, #16128 @ 0x3f00 8006904: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006908: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800690c: 091a lsrs r2, r3, #4 800690e: 4b10 ldr r3, [pc, #64] @ (8006950 ) 8006910: 4013 ands r3, r2 8006912: 4a0d ldr r2, [pc, #52] @ (8006948 ) 8006914: 430b orrs r3, r1 8006916: 6113 str r3, [r2, #16] 8006918: e005 b.n 8006926 800691a: 4b0b ldr r3, [pc, #44] @ (8006948 ) 800691c: 691b ldr r3, [r3, #16] 800691e: 4a0a ldr r2, [pc, #40] @ (8006948 ) 8006920: f423 537c bic.w r3, r3, #16128 @ 0x3f00 8006924: 6113 str r3, [r2, #16] 8006926: 4b08 ldr r3, [pc, #32] @ (8006948 ) 8006928: 6f19 ldr r1, [r3, #112] @ 0x70 800692a: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800692e: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 8006932: f3c3 030b ubfx r3, r3, #0, #12 8006936: 4a04 ldr r2, [pc, #16] @ (8006948 ) 8006938: 430b orrs r3, r1 800693a: 6713 str r3, [r2, #112] @ 0x70 800693c: e00e b.n 800695c } else { /* set overall return value */ status = ret; 800693e: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8006942: f887 3126 strb.w r3, [r7, #294] @ 0x126 8006946: e009 b.n 800695c 8006948: 58024400 .word 0x58024400 800694c: 58024800 .word 0x58024800 8006950: 00ffffcf .word 0x00ffffcf } } else { /* set overall return value */ status = ret; 8006954: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8006958: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } /*-------------------------- USART1/6 configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) 800695c: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006960: e9d3 2300 ldrd r2, r3, [r3] 8006964: f002 0301 and.w r3, r2, #1 8006968: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 800696c: 2300 movs r3, #0 800696e: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 8006972: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0 8006976: 460b mov r3, r1 8006978: 4313 orrs r3, r2 800697a: f000 8089 beq.w 8006a90 { switch (PeriphClkInit->Usart16ClockSelection) 800697e: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006982: 6fdb ldr r3, [r3, #124] @ 0x7c 8006984: 2b28 cmp r3, #40 @ 0x28 8006986: d86b bhi.n 8006a60 8006988: a201 add r2, pc, #4 @ (adr r2, 8006990 ) 800698a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800698e: bf00 nop 8006990: 08006a69 .word 0x08006a69 8006994: 08006a61 .word 0x08006a61 8006998: 08006a61 .word 0x08006a61 800699c: 08006a61 .word 0x08006a61 80069a0: 08006a61 .word 0x08006a61 80069a4: 08006a61 .word 0x08006a61 80069a8: 08006a61 .word 0x08006a61 80069ac: 08006a61 .word 0x08006a61 80069b0: 08006a35 .word 0x08006a35 80069b4: 08006a61 .word 0x08006a61 80069b8: 08006a61 .word 0x08006a61 80069bc: 08006a61 .word 0x08006a61 80069c0: 08006a61 .word 0x08006a61 80069c4: 08006a61 .word 0x08006a61 80069c8: 08006a61 .word 0x08006a61 80069cc: 08006a61 .word 0x08006a61 80069d0: 08006a4b .word 0x08006a4b 80069d4: 08006a61 .word 0x08006a61 80069d8: 08006a61 .word 0x08006a61 80069dc: 08006a61 .word 0x08006a61 80069e0: 08006a61 .word 0x08006a61 80069e4: 08006a61 .word 0x08006a61 80069e8: 08006a61 .word 0x08006a61 80069ec: 08006a61 .word 0x08006a61 80069f0: 08006a69 .word 0x08006a69 80069f4: 08006a61 .word 0x08006a61 80069f8: 08006a61 .word 0x08006a61 80069fc: 08006a61 .word 0x08006a61 8006a00: 08006a61 .word 0x08006a61 8006a04: 08006a61 .word 0x08006a61 8006a08: 08006a61 .word 0x08006a61 8006a0c: 08006a61 .word 0x08006a61 8006a10: 08006a69 .word 0x08006a69 8006a14: 08006a61 .word 0x08006a61 8006a18: 08006a61 .word 0x08006a61 8006a1c: 08006a61 .word 0x08006a61 8006a20: 08006a61 .word 0x08006a61 8006a24: 08006a61 .word 0x08006a61 8006a28: 08006a61 .word 0x08006a61 8006a2c: 08006a61 .word 0x08006a61 8006a30: 08006a69 .word 0x08006a69 case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ /* USART1/6 clock source configuration done later after clock selection check */ break; case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 8006a34: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006a38: 3308 adds r3, #8 8006a3a: 2101 movs r1, #1 8006a3c: 4618 mov r0, r3 8006a3e: f001 fe95 bl 800876c 8006a42: 4603 mov r3, r0 8006a44: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* USART1/6 clock source configuration done later after clock selection check */ break; 8006a48: e00f b.n 8006a6a case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 8006a4a: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006a4e: 3328 adds r3, #40 @ 0x28 8006a50: 2101 movs r1, #1 8006a52: 4618 mov r0, r3 8006a54: f001 ff3c bl 80088d0 8006a58: 4603 mov r3, r0 8006a5a: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* USART1/6 clock source configuration done later after clock selection check */ break; 8006a5e: e004 b.n 8006a6a /* LSE, oscillator is used as source of USART1/6 clock */ /* USART1/6 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8006a60: 2301 movs r3, #1 8006a62: f887 3127 strb.w r3, [r7, #295] @ 0x127 break; 8006a66: e000 b.n 8006a6a break; 8006a68: bf00 nop } if (ret == HAL_OK) 8006a6a: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8006a6e: 2b00 cmp r3, #0 8006a70: d10a bne.n 8006a88 { /* Set the source of USART1/6 clock */ __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); 8006a72: 4bbf ldr r3, [pc, #764] @ (8006d70 ) 8006a74: 6d5b ldr r3, [r3, #84] @ 0x54 8006a76: f023 0138 bic.w r1, r3, #56 @ 0x38 8006a7a: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006a7e: 6fdb ldr r3, [r3, #124] @ 0x7c 8006a80: 4abb ldr r2, [pc, #748] @ (8006d70 ) 8006a82: 430b orrs r3, r1 8006a84: 6553 str r3, [r2, #84] @ 0x54 8006a86: e003 b.n 8006a90 } else { /* set overall return value */ status = ret; 8006a88: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8006a8c: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) 8006a90: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006a94: e9d3 2300 ldrd r2, r3, [r3] 8006a98: f002 0302 and.w r3, r2, #2 8006a9c: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8006aa0: 2300 movs r3, #0 8006aa2: f8c7 30bc str.w r3, [r7, #188] @ 0xbc 8006aa6: e9d7 122e ldrd r1, r2, [r7, #184] @ 0xb8 8006aaa: 460b mov r3, r1 8006aac: 4313 orrs r3, r2 8006aae: d041 beq.n 8006b34 { switch (PeriphClkInit->Usart234578ClockSelection) 8006ab0: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006ab4: 6f9b ldr r3, [r3, #120] @ 0x78 8006ab6: 2b05 cmp r3, #5 8006ab8: d824 bhi.n 8006b04 8006aba: a201 add r2, pc, #4 @ (adr r2, 8006ac0 ) 8006abc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8006ac0: 08006b0d .word 0x08006b0d 8006ac4: 08006ad9 .word 0x08006ad9 8006ac8: 08006aef .word 0x08006aef 8006acc: 08006b0d .word 0x08006b0d 8006ad0: 08006b0d .word 0x08006b0d 8006ad4: 08006b0d .word 0x08006b0d case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 8006ad8: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006adc: 3308 adds r3, #8 8006ade: 2101 movs r1, #1 8006ae0: 4618 mov r0, r3 8006ae2: f001 fe43 bl 800876c 8006ae6: 4603 mov r3, r0 8006ae8: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 8006aec: e00f b.n 8006b0e case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 8006aee: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006af2: 3328 adds r3, #40 @ 0x28 8006af4: 2101 movs r1, #1 8006af6: 4618 mov r0, r3 8006af8: f001 feea bl 80088d0 8006afc: 4603 mov r3, r0 8006afe: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 8006b02: e004 b.n 8006b0e /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8006b04: 2301 movs r3, #1 8006b06: f887 3127 strb.w r3, [r7, #295] @ 0x127 break; 8006b0a: e000 b.n 8006b0e break; 8006b0c: bf00 nop } if (ret == HAL_OK) 8006b0e: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8006b12: 2b00 cmp r3, #0 8006b14: d10a bne.n 8006b2c { /* Set the source of USART2/3/4/5/7/8 clock */ __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); 8006b16: 4b96 ldr r3, [pc, #600] @ (8006d70 ) 8006b18: 6d5b ldr r3, [r3, #84] @ 0x54 8006b1a: f023 0107 bic.w r1, r3, #7 8006b1e: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006b22: 6f9b ldr r3, [r3, #120] @ 0x78 8006b24: 4a92 ldr r2, [pc, #584] @ (8006d70 ) 8006b26: 430b orrs r3, r1 8006b28: 6553 str r3, [r2, #84] @ 0x54 8006b2a: e003 b.n 8006b34 } else { /* set overall return value */ status = ret; 8006b2c: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8006b30: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } /*-------------------------- LPUART1 Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 8006b34: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006b38: e9d3 2300 ldrd r2, r3, [r3] 8006b3c: f002 0304 and.w r3, r2, #4 8006b40: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8006b44: 2300 movs r3, #0 8006b46: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8006b4a: e9d7 122c ldrd r1, r2, [r7, #176] @ 0xb0 8006b4e: 460b mov r3, r1 8006b50: 4313 orrs r3, r2 8006b52: d044 beq.n 8006bde { switch (PeriphClkInit->Lpuart1ClockSelection) 8006b54: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006b58: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8006b5c: 2b05 cmp r3, #5 8006b5e: d825 bhi.n 8006bac 8006b60: a201 add r2, pc, #4 @ (adr r2, 8006b68 ) 8006b62: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8006b66: bf00 nop 8006b68: 08006bb5 .word 0x08006bb5 8006b6c: 08006b81 .word 0x08006b81 8006b70: 08006b97 .word 0x08006b97 8006b74: 08006bb5 .word 0x08006bb5 8006b78: 08006bb5 .word 0x08006bb5 8006b7c: 08006bb5 .word 0x08006bb5 case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ /* LPUART1 clock source configuration done later after clock selection check */ break; case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 8006b80: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006b84: 3308 adds r3, #8 8006b86: 2101 movs r1, #1 8006b88: 4618 mov r0, r3 8006b8a: f001 fdef bl 800876c 8006b8e: 4603 mov r3, r0 8006b90: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* LPUART1 clock source configuration done later after clock selection check */ break; 8006b94: e00f b.n 8006bb6 case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 8006b96: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006b9a: 3328 adds r3, #40 @ 0x28 8006b9c: 2101 movs r1, #1 8006b9e: 4618 mov r0, r3 8006ba0: f001 fe96 bl 80088d0 8006ba4: 4603 mov r3, r0 8006ba6: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* LPUART1 clock source configuration done later after clock selection check */ break; 8006baa: e004 b.n 8006bb6 /* LSE, oscillator is used as source of LPUART1 clock */ /* LPUART1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8006bac: 2301 movs r3, #1 8006bae: f887 3127 strb.w r3, [r7, #295] @ 0x127 break; 8006bb2: e000 b.n 8006bb6 break; 8006bb4: bf00 nop } if (ret == HAL_OK) 8006bb6: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8006bba: 2b00 cmp r3, #0 8006bbc: d10b bne.n 8006bd6 { /* Set the source of LPUART1 clock */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 8006bbe: 4b6c ldr r3, [pc, #432] @ (8006d70 ) 8006bc0: 6d9b ldr r3, [r3, #88] @ 0x58 8006bc2: f023 0107 bic.w r1, r3, #7 8006bc6: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006bca: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8006bce: 4a68 ldr r2, [pc, #416] @ (8006d70 ) 8006bd0: 430b orrs r3, r1 8006bd2: 6593 str r3, [r2, #88] @ 0x58 8006bd4: e003 b.n 8006bde } else { /* set overall return value */ status = ret; 8006bd6: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8006bda: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } /*---------------------------- LPTIM1 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 8006bde: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006be2: e9d3 2300 ldrd r2, r3, [r3] 8006be6: f002 0320 and.w r3, r2, #32 8006bea: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 8006bee: 2300 movs r3, #0 8006bf0: f8c7 30ac str.w r3, [r7, #172] @ 0xac 8006bf4: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8 8006bf8: 460b mov r3, r1 8006bfa: 4313 orrs r3, r2 8006bfc: d055 beq.n 8006caa { switch (PeriphClkInit->Lptim1ClockSelection) 8006bfe: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006c02: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8006c06: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8006c0a: d033 beq.n 8006c74 8006c0c: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8006c10: d82c bhi.n 8006c6c 8006c12: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8006c16: d02f beq.n 8006c78 8006c18: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8006c1c: d826 bhi.n 8006c6c 8006c1e: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 8006c22: d02b beq.n 8006c7c 8006c24: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 8006c28: d820 bhi.n 8006c6c 8006c2a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8006c2e: d012 beq.n 8006c56 8006c30: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8006c34: d81a bhi.n 8006c6c 8006c36: 2b00 cmp r3, #0 8006c38: d022 beq.n 8006c80 8006c3a: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8006c3e: d115 bne.n 8006c6c /* LPTIM1 clock source configuration done later after clock selection check */ break; case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 8006c40: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006c44: 3308 adds r3, #8 8006c46: 2100 movs r1, #0 8006c48: 4618 mov r0, r3 8006c4a: f001 fd8f bl 800876c 8006c4e: 4603 mov r3, r0 8006c50: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* LPTIM1 clock source configuration done later after clock selection check */ break; 8006c54: e015 b.n 8006c82 case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 8006c56: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006c5a: 3328 adds r3, #40 @ 0x28 8006c5c: 2102 movs r1, #2 8006c5e: 4618 mov r0, r3 8006c60: f001 fe36 bl 80088d0 8006c64: 4603 mov r3, r0 8006c66: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* LPTIM1 clock source configuration done later after clock selection check */ break; 8006c6a: e00a b.n 8006c82 /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */ /* LPTIM1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8006c6c: 2301 movs r3, #1 8006c6e: f887 3127 strb.w r3, [r7, #295] @ 0x127 break; 8006c72: e006 b.n 8006c82 break; 8006c74: bf00 nop 8006c76: e004 b.n 8006c82 break; 8006c78: bf00 nop 8006c7a: e002 b.n 8006c82 break; 8006c7c: bf00 nop 8006c7e: e000 b.n 8006c82 break; 8006c80: bf00 nop } if (ret == HAL_OK) 8006c82: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8006c86: 2b00 cmp r3, #0 8006c88: d10b bne.n 8006ca2 { /* Set the source of LPTIM1 clock*/ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 8006c8a: 4b39 ldr r3, [pc, #228] @ (8006d70 ) 8006c8c: 6d5b ldr r3, [r3, #84] @ 0x54 8006c8e: f023 41e0 bic.w r1, r3, #1879048192 @ 0x70000000 8006c92: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006c96: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8006c9a: 4a35 ldr r2, [pc, #212] @ (8006d70 ) 8006c9c: 430b orrs r3, r1 8006c9e: 6553 str r3, [r2, #84] @ 0x54 8006ca0: e003 b.n 8006caa } else { /* set overall return value */ status = ret; 8006ca2: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8006ca6: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } /*---------------------------- LPTIM2 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) 8006caa: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006cae: e9d3 2300 ldrd r2, r3, [r3] 8006cb2: f002 0340 and.w r3, r2, #64 @ 0x40 8006cb6: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 8006cba: 2300 movs r3, #0 8006cbc: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 8006cc0: e9d7 1228 ldrd r1, r2, [r7, #160] @ 0xa0 8006cc4: 460b mov r3, r1 8006cc6: 4313 orrs r3, r2 8006cc8: d058 beq.n 8006d7c { switch (PeriphClkInit->Lptim2ClockSelection) 8006cca: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006cce: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 8006cd2: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 8006cd6: d033 beq.n 8006d40 8006cd8: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 8006cdc: d82c bhi.n 8006d38 8006cde: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8006ce2: d02f beq.n 8006d44 8006ce4: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8006ce8: d826 bhi.n 8006d38 8006cea: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 8006cee: d02b beq.n 8006d48 8006cf0: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 8006cf4: d820 bhi.n 8006d38 8006cf6: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8006cfa: d012 beq.n 8006d22 8006cfc: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8006d00: d81a bhi.n 8006d38 8006d02: 2b00 cmp r3, #0 8006d04: d022 beq.n 8006d4c 8006d06: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8006d0a: d115 bne.n 8006d38 /* LPTIM2 clock source configuration done later after clock selection check */ break; case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 8006d0c: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006d10: 3308 adds r3, #8 8006d12: 2100 movs r1, #0 8006d14: 4618 mov r0, r3 8006d16: f001 fd29 bl 800876c 8006d1a: 4603 mov r3, r0 8006d1c: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* LPTIM2 clock source configuration done later after clock selection check */ break; 8006d20: e015 b.n 8006d4e case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 8006d22: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006d26: 3328 adds r3, #40 @ 0x28 8006d28: 2102 movs r1, #2 8006d2a: 4618 mov r0, r3 8006d2c: f001 fdd0 bl 80088d0 8006d30: 4603 mov r3, r0 8006d32: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* LPTIM2 clock source configuration done later after clock selection check */ break; 8006d36: e00a b.n 8006d4e /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ /* LPTIM2 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8006d38: 2301 movs r3, #1 8006d3a: f887 3127 strb.w r3, [r7, #295] @ 0x127 break; 8006d3e: e006 b.n 8006d4e break; 8006d40: bf00 nop 8006d42: e004 b.n 8006d4e break; 8006d44: bf00 nop 8006d46: e002 b.n 8006d4e break; 8006d48: bf00 nop 8006d4a: e000 b.n 8006d4e break; 8006d4c: bf00 nop } if (ret == HAL_OK) 8006d4e: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8006d52: 2b00 cmp r3, #0 8006d54: d10e bne.n 8006d74 { /* Set the source of LPTIM2 clock*/ __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 8006d56: 4b06 ldr r3, [pc, #24] @ (8006d70 ) 8006d58: 6d9b ldr r3, [r3, #88] @ 0x58 8006d5a: f423 51e0 bic.w r1, r3, #7168 @ 0x1c00 8006d5e: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006d62: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 8006d66: 4a02 ldr r2, [pc, #8] @ (8006d70 ) 8006d68: 430b orrs r3, r1 8006d6a: 6593 str r3, [r2, #88] @ 0x58 8006d6c: e006 b.n 8006d7c 8006d6e: bf00 nop 8006d70: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 8006d74: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8006d78: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } /*---------------------------- LPTIM345 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) 8006d7c: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006d80: e9d3 2300 ldrd r2, r3, [r3] 8006d84: f002 0380 and.w r3, r2, #128 @ 0x80 8006d88: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8006d8c: 2300 movs r3, #0 8006d8e: f8c7 309c str.w r3, [r7, #156] @ 0x9c 8006d92: e9d7 1226 ldrd r1, r2, [r7, #152] @ 0x98 8006d96: 460b mov r3, r1 8006d98: 4313 orrs r3, r2 8006d9a: d055 beq.n 8006e48 { switch (PeriphClkInit->Lptim345ClockSelection) 8006d9c: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006da0: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8006da4: f5b3 4f20 cmp.w r3, #40960 @ 0xa000 8006da8: d033 beq.n 8006e12 8006daa: f5b3 4f20 cmp.w r3, #40960 @ 0xa000 8006dae: d82c bhi.n 8006e0a 8006db0: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8006db4: d02f beq.n 8006e16 8006db6: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8006dba: d826 bhi.n 8006e0a 8006dbc: f5b3 4fc0 cmp.w r3, #24576 @ 0x6000 8006dc0: d02b beq.n 8006e1a 8006dc2: f5b3 4fc0 cmp.w r3, #24576 @ 0x6000 8006dc6: d820 bhi.n 8006e0a 8006dc8: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 8006dcc: d012 beq.n 8006df4 8006dce: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 8006dd2: d81a bhi.n 8006e0a 8006dd4: 2b00 cmp r3, #0 8006dd6: d022 beq.n 8006e1e 8006dd8: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8006ddc: d115 bne.n 8006e0a case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 8006dde: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006de2: 3308 adds r3, #8 8006de4: 2100 movs r1, #0 8006de6: 4618 mov r0, r3 8006de8: f001 fcc0 bl 800876c 8006dec: 4603 mov r3, r0 8006dee: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 8006df2: e015 b.n 8006e20 case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 8006df4: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006df8: 3328 adds r3, #40 @ 0x28 8006dfa: 2102 movs r1, #2 8006dfc: 4618 mov r0, r3 8006dfe: f001 fd67 bl 80088d0 8006e02: 4603 mov r3, r0 8006e04: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 8006e08: e00a b.n 8006e20 /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8006e0a: 2301 movs r3, #1 8006e0c: f887 3127 strb.w r3, [r7, #295] @ 0x127 break; 8006e10: e006 b.n 8006e20 break; 8006e12: bf00 nop 8006e14: e004 b.n 8006e20 break; 8006e16: bf00 nop 8006e18: e002 b.n 8006e20 break; 8006e1a: bf00 nop 8006e1c: e000 b.n 8006e20 break; 8006e1e: bf00 nop } if (ret == HAL_OK) 8006e20: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8006e24: 2b00 cmp r3, #0 8006e26: d10b bne.n 8006e40 { /* Set the source of LPTIM3/4/5 clock */ __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); 8006e28: 4ba1 ldr r3, [pc, #644] @ (80070b0 ) 8006e2a: 6d9b ldr r3, [r3, #88] @ 0x58 8006e2c: f423 4160 bic.w r1, r3, #57344 @ 0xe000 8006e30: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006e34: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8006e38: 4a9d ldr r2, [pc, #628] @ (80070b0 ) 8006e3a: 430b orrs r3, r1 8006e3c: 6593 str r3, [r2, #88] @ 0x58 8006e3e: e003 b.n 8006e48 } else { /* set overall return value */ status = ret; 8006e40: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8006e44: f887 3126 strb.w r3, [r7, #294] @ 0x126 __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); } #else if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) 8006e48: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006e4c: e9d3 2300 ldrd r2, r3, [r3] 8006e50: f002 0308 and.w r3, r2, #8 8006e54: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8006e58: 2300 movs r3, #0 8006e5a: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8006e5e: e9d7 1224 ldrd r1, r2, [r7, #144] @ 0x90 8006e62: 460b mov r3, r1 8006e64: 4313 orrs r3, r2 8006e66: d01e beq.n 8006ea6 { /* Check the parameters */ assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection)); if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3) 8006e68: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006e6c: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8006e70: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8006e74: d10c bne.n 8006e90 { if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 8006e76: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006e7a: 3328 adds r3, #40 @ 0x28 8006e7c: 2102 movs r1, #2 8006e7e: 4618 mov r0, r3 8006e80: f001 fd26 bl 80088d0 8006e84: 4603 mov r3, r0 8006e86: 2b00 cmp r3, #0 8006e88: d002 beq.n 8006e90 { status = HAL_ERROR; 8006e8a: 2301 movs r3, #1 8006e8c: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); 8006e90: 4b87 ldr r3, [pc, #540] @ (80070b0 ) 8006e92: 6d5b ldr r3, [r3, #84] @ 0x54 8006e94: f423 5140 bic.w r1, r3, #12288 @ 0x3000 8006e98: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006e9c: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8006ea0: 4a83 ldr r2, [pc, #524] @ (80070b0 ) 8006ea2: 430b orrs r3, r1 8006ea4: 6553 str r3, [r2, #84] @ 0x54 } #endif /* I2C5 */ /*------------------------------ I2C4 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 8006ea6: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006eaa: e9d3 2300 ldrd r2, r3, [r3] 8006eae: f002 0310 and.w r3, r2, #16 8006eb2: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8006eb6: 2300 movs r3, #0 8006eb8: f8c7 308c str.w r3, [r7, #140] @ 0x8c 8006ebc: e9d7 1222 ldrd r1, r2, [r7, #136] @ 0x88 8006ec0: 460b mov r3, r1 8006ec2: 4313 orrs r3, r2 8006ec4: d01e beq.n 8006f04 { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3) 8006ec6: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006eca: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 8006ece: f5b3 7f80 cmp.w r3, #256 @ 0x100 8006ed2: d10c bne.n 8006eee { if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 8006ed4: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006ed8: 3328 adds r3, #40 @ 0x28 8006eda: 2102 movs r1, #2 8006edc: 4618 mov r0, r3 8006ede: f001 fcf7 bl 80088d0 8006ee2: 4603 mov r3, r0 8006ee4: 2b00 cmp r3, #0 8006ee6: d002 beq.n 8006eee { status = HAL_ERROR; 8006ee8: 2301 movs r3, #1 8006eea: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 8006eee: 4b70 ldr r3, [pc, #448] @ (80070b0 ) 8006ef0: 6d9b ldr r3, [r3, #88] @ 0x58 8006ef2: f423 7140 bic.w r1, r3, #768 @ 0x300 8006ef6: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006efa: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 8006efe: 4a6c ldr r2, [pc, #432] @ (80070b0 ) 8006f00: 430b orrs r3, r1 8006f02: 6593 str r3, [r2, #88] @ 0x58 } /*---------------------------- ADC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8006f04: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006f08: e9d3 2300 ldrd r2, r3, [r3] 8006f0c: f402 2300 and.w r3, r2, #524288 @ 0x80000 8006f10: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8006f14: 2300 movs r3, #0 8006f16: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8006f1a: e9d7 1220 ldrd r1, r2, [r7, #128] @ 0x80 8006f1e: 460b mov r3, r1 8006f20: 4313 orrs r3, r2 8006f22: d03e beq.n 8006fa2 { switch (PeriphClkInit->AdcClockSelection) 8006f24: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006f28: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 8006f2c: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8006f30: d022 beq.n 8006f78 8006f32: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8006f36: d81b bhi.n 8006f70 8006f38: 2b00 cmp r3, #0 8006f3a: d003 beq.n 8006f44 8006f3c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8006f40: d00b beq.n 8006f5a 8006f42: e015 b.n 8006f70 { case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 8006f44: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006f48: 3308 adds r3, #8 8006f4a: 2100 movs r1, #0 8006f4c: 4618 mov r0, r3 8006f4e: f001 fc0d bl 800876c 8006f52: 4603 mov r3, r0 8006f54: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* ADC clock source configuration done later after clock selection check */ break; 8006f58: e00f b.n 8006f7a case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 8006f5a: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006f5e: 3328 adds r3, #40 @ 0x28 8006f60: 2102 movs r1, #2 8006f62: 4618 mov r0, r3 8006f64: f001 fcb4 bl 80088d0 8006f68: 4603 mov r3, r0 8006f6a: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* ADC clock source configuration done later after clock selection check */ break; 8006f6e: e004 b.n 8006f7a /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ /* ADC clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8006f70: 2301 movs r3, #1 8006f72: f887 3127 strb.w r3, [r7, #295] @ 0x127 break; 8006f76: e000 b.n 8006f7a break; 8006f78: bf00 nop } if (ret == HAL_OK) 8006f7a: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8006f7e: 2b00 cmp r3, #0 8006f80: d10b bne.n 8006f9a { /* Set the source of ADC clock*/ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8006f82: 4b4b ldr r3, [pc, #300] @ (80070b0 ) 8006f84: 6d9b ldr r3, [r3, #88] @ 0x58 8006f86: f423 3140 bic.w r1, r3, #196608 @ 0x30000 8006f8a: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006f8e: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 8006f92: 4a47 ldr r2, [pc, #284] @ (80070b0 ) 8006f94: 430b orrs r3, r1 8006f96: 6593 str r3, [r2, #88] @ 0x58 8006f98: e003 b.n 8006fa2 } else { /* set overall return value */ status = ret; 8006f9a: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8006f9e: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } /*------------------------------ USB Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 8006fa2: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006fa6: e9d3 2300 ldrd r2, r3, [r3] 8006faa: f402 2380 and.w r3, r2, #262144 @ 0x40000 8006fae: 67bb str r3, [r7, #120] @ 0x78 8006fb0: 2300 movs r3, #0 8006fb2: 67fb str r3, [r7, #124] @ 0x7c 8006fb4: e9d7 121e ldrd r1, r2, [r7, #120] @ 0x78 8006fb8: 460b mov r3, r1 8006fba: 4313 orrs r3, r2 8006fbc: d03b beq.n 8007036 { switch (PeriphClkInit->UsbClockSelection) 8006fbe: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006fc2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8006fc6: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 8006fca: d01f beq.n 800700c 8006fcc: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 8006fd0: d818 bhi.n 8007004 8006fd2: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8006fd6: d003 beq.n 8006fe0 8006fd8: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8006fdc: d007 beq.n 8006fee 8006fde: e011 b.n 8007004 { case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/ /* Enable USB Clock output generated form System USB . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8006fe0: 4b33 ldr r3, [pc, #204] @ (80070b0 ) 8006fe2: 6adb ldr r3, [r3, #44] @ 0x2c 8006fe4: 4a32 ldr r2, [pc, #200] @ (80070b0 ) 8006fe6: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8006fea: 62d3 str r3, [r2, #44] @ 0x2c /* USB clock source configuration done later after clock selection check */ break; 8006fec: e00f b.n 800700e case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 8006fee: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006ff2: 3328 adds r3, #40 @ 0x28 8006ff4: 2101 movs r1, #1 8006ff6: 4618 mov r0, r3 8006ff8: f001 fc6a bl 80088d0 8006ffc: 4603 mov r3, r0 8006ffe: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* USB clock source configuration done later after clock selection check */ break; 8007002: e004 b.n 800700e /* HSI48 oscillator is used as source of USB clock */ /* USB clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8007004: 2301 movs r3, #1 8007006: f887 3127 strb.w r3, [r7, #295] @ 0x127 break; 800700a: e000 b.n 800700e break; 800700c: bf00 nop } if (ret == HAL_OK) 800700e: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8007012: 2b00 cmp r3, #0 8007014: d10b bne.n 800702e { /* Set the source of USB clock*/ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 8007016: 4b26 ldr r3, [pc, #152] @ (80070b0 ) 8007018: 6d5b ldr r3, [r3, #84] @ 0x54 800701a: f423 1140 bic.w r1, r3, #3145728 @ 0x300000 800701e: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8007022: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8007026: 4a22 ldr r2, [pc, #136] @ (80070b0 ) 8007028: 430b orrs r3, r1 800702a: 6553 str r3, [r2, #84] @ 0x54 800702c: e003 b.n 8007036 } else { /* set overall return value */ status = ret; 800702e: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8007032: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } /*------------------------------------- SDMMC Configuration ------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) 8007036: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800703a: e9d3 2300 ldrd r2, r3, [r3] 800703e: f402 3380 and.w r3, r2, #65536 @ 0x10000 8007042: 673b str r3, [r7, #112] @ 0x70 8007044: 2300 movs r3, #0 8007046: 677b str r3, [r7, #116] @ 0x74 8007048: e9d7 121c ldrd r1, r2, [r7, #112] @ 0x70 800704c: 460b mov r3, r1 800704e: 4313 orrs r3, r2 8007050: d034 beq.n 80070bc { /* Check the parameters */ assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection)); switch (PeriphClkInit->SdmmcClockSelection) 8007052: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8007056: 6d1b ldr r3, [r3, #80] @ 0x50 8007058: 2b00 cmp r3, #0 800705a: d003 beq.n 8007064 800705c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8007060: d007 beq.n 8007072 8007062: e011 b.n 8007088 { case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/ /* Enable SDMMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8007064: 4b12 ldr r3, [pc, #72] @ (80070b0 ) 8007066: 6adb ldr r3, [r3, #44] @ 0x2c 8007068: 4a11 ldr r2, [pc, #68] @ (80070b0 ) 800706a: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800706e: 62d3 str r3, [r2, #44] @ 0x2c /* SDMMC clock source configuration done later after clock selection check */ break; 8007070: e00e b.n 8007090 case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 8007072: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8007076: 3308 adds r3, #8 8007078: 2102 movs r1, #2 800707a: 4618 mov r0, r3 800707c: f001 fb76 bl 800876c 8007080: 4603 mov r3, r0 8007082: f887 3127 strb.w r3, [r7, #295] @ 0x127 /* SDMMC clock source configuration done later after clock selection check */ break; 8007086: e003 b.n 8007090 default: ret = HAL_ERROR; 8007088: 2301 movs r3, #1 800708a: f887 3127 strb.w r3, [r7, #295] @ 0x127 break; 800708e: bf00 nop } if (ret == HAL_OK) 8007090: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8007094: 2b00 cmp r3, #0 8007096: d10d bne.n 80070b4 { /* Set the source of SDMMC clock*/ __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); 8007098: 4b05 ldr r3, [pc, #20] @ (80070b0 ) 800709a: 6cdb ldr r3, [r3, #76] @ 0x4c 800709c: f423 3180 bic.w r1, r3, #65536 @ 0x10000 80070a0: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80070a4: 6d1b ldr r3, [r3, #80] @ 0x50 80070a6: 4a02 ldr r2, [pc, #8] @ (80070b0 ) 80070a8: 430b orrs r3, r1 80070aa: 64d3 str r3, [r2, #76] @ 0x4c 80070ac: e006 b.n 80070bc 80070ae: bf00 nop 80070b0: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 80070b4: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 80070b8: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } #if defined(LTDC) /*-------------------------------------- LTDC Configuration -----------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) 80070bc: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80070c0: e9d3 2300 ldrd r2, r3, [r3] 80070c4: f002 5300 and.w r3, r2, #536870912 @ 0x20000000 80070c8: 66bb str r3, [r7, #104] @ 0x68 80070ca: 2300 movs r3, #0 80070cc: 66fb str r3, [r7, #108] @ 0x6c 80070ce: e9d7 121a ldrd r1, r2, [r7, #104] @ 0x68 80070d2: 460b mov r3, r1 80070d4: 4313 orrs r3, r2 80070d6: d00c beq.n 80070f2 { if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 80070d8: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80070dc: 3328 adds r3, #40 @ 0x28 80070de: 2102 movs r1, #2 80070e0: 4618 mov r0, r3 80070e2: f001 fbf5 bl 80088d0 80070e6: 4603 mov r3, r0 80070e8: 2b00 cmp r3, #0 80070ea: d002 beq.n 80070f2 { status = HAL_ERROR; 80070ec: 2301 movs r3, #1 80070ee: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } #endif /* LTDC */ /*------------------------------ RNG Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) 80070f2: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80070f6: e9d3 2300 ldrd r2, r3, [r3] 80070fa: f402 3300 and.w r3, r2, #131072 @ 0x20000 80070fe: 663b str r3, [r7, #96] @ 0x60 8007100: 2300 movs r3, #0 8007102: 667b str r3, [r7, #100] @ 0x64 8007104: e9d7 1218 ldrd r1, r2, [r7, #96] @ 0x60 8007108: 460b mov r3, r1 800710a: 4313 orrs r3, r2 800710c: d038 beq.n 8007180 { switch (PeriphClkInit->RngClockSelection) 800710e: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8007112: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8007116: f5b3 7f40 cmp.w r3, #768 @ 0x300 800711a: d018 beq.n 800714e 800711c: f5b3 7f40 cmp.w r3, #768 @ 0x300 8007120: d811 bhi.n 8007146 8007122: f5b3 7f00 cmp.w r3, #512 @ 0x200 8007126: d014 beq.n 8007152 8007128: f5b3 7f00 cmp.w r3, #512 @ 0x200 800712c: d80b bhi.n 8007146 800712e: 2b00 cmp r3, #0 8007130: d011 beq.n 8007156 8007132: f5b3 7f80 cmp.w r3, #256 @ 0x100 8007136: d106 bne.n 8007146 { case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/ /* Enable RNG Clock output generated form System RNG . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8007138: 4bc3 ldr r3, [pc, #780] @ (8007448 ) 800713a: 6adb ldr r3, [r3, #44] @ 0x2c 800713c: 4ac2 ldr r2, [pc, #776] @ (8007448 ) 800713e: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8007142: 62d3 str r3, [r2, #44] @ 0x2c /* RNG clock source configuration done later after clock selection check */ break; 8007144: e008 b.n 8007158 /* HSI48 oscillator is used as source of RNG clock */ /* RNG clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8007146: 2301 movs r3, #1 8007148: f887 3127 strb.w r3, [r7, #295] @ 0x127 break; 800714c: e004 b.n 8007158 break; 800714e: bf00 nop 8007150: e002 b.n 8007158 break; 8007152: bf00 nop 8007154: e000 b.n 8007158 break; 8007156: bf00 nop } if (ret == HAL_OK) 8007158: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 800715c: 2b00 cmp r3, #0 800715e: d10b bne.n 8007178 { /* Set the source of RNG clock*/ __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 8007160: 4bb9 ldr r3, [pc, #740] @ (8007448 ) 8007162: 6d5b ldr r3, [r3, #84] @ 0x54 8007164: f423 7140 bic.w r1, r3, #768 @ 0x300 8007168: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800716c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8007170: 4ab5 ldr r2, [pc, #724] @ (8007448 ) 8007172: 430b orrs r3, r1 8007174: 6553 str r3, [r2, #84] @ 0x54 8007176: e003 b.n 8007180 } else { /* set overall return value */ status = ret; 8007178: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 800717c: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } /*------------------------------ SWPMI1 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) 8007180: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8007184: e9d3 2300 ldrd r2, r3, [r3] 8007188: f402 1380 and.w r3, r2, #1048576 @ 0x100000 800718c: 65bb str r3, [r7, #88] @ 0x58 800718e: 2300 movs r3, #0 8007190: 65fb str r3, [r7, #92] @ 0x5c 8007192: e9d7 1216 ldrd r1, r2, [r7, #88] @ 0x58 8007196: 460b mov r3, r1 8007198: 4313 orrs r3, r2 800719a: d009 beq.n 80071b0 { /* Check the parameters */ assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); /* Configure the SWPMI1 interface clock source */ __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); 800719c: 4baa ldr r3, [pc, #680] @ (8007448 ) 800719e: 6d1b ldr r3, [r3, #80] @ 0x50 80071a0: f023 4100 bic.w r1, r3, #2147483648 @ 0x80000000 80071a4: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80071a8: 6f5b ldr r3, [r3, #116] @ 0x74 80071aa: 4aa7 ldr r2, [pc, #668] @ (8007448 ) 80071ac: 430b orrs r3, r1 80071ae: 6513 str r3, [r2, #80] @ 0x50 } #if defined(HRTIM1) /*------------------------------ HRTIM1 clock Configuration ----------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) 80071b0: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80071b4: e9d3 2300 ldrd r2, r3, [r3] 80071b8: f002 5380 and.w r3, r2, #268435456 @ 0x10000000 80071bc: 653b str r3, [r7, #80] @ 0x50 80071be: 2300 movs r3, #0 80071c0: 657b str r3, [r7, #84] @ 0x54 80071c2: e9d7 1214 ldrd r1, r2, [r7, #80] @ 0x50 80071c6: 460b mov r3, r1 80071c8: 4313 orrs r3, r2 80071ca: d00a beq.n 80071e2 { /* Check the parameters */ assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection)); /* Configure the HRTIM1 clock source */ __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); 80071cc: 4b9e ldr r3, [pc, #632] @ (8007448 ) 80071ce: 691b ldr r3, [r3, #16] 80071d0: f423 4180 bic.w r1, r3, #16384 @ 0x4000 80071d4: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80071d8: f8d3 30b8 ldr.w r3, [r3, #184] @ 0xb8 80071dc: 4a9a ldr r2, [pc, #616] @ (8007448 ) 80071de: 430b orrs r3, r1 80071e0: 6113 str r3, [r2, #16] } #endif /*HRTIM1*/ /*------------------------------ DFSDM1 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) 80071e2: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80071e6: e9d3 2300 ldrd r2, r3, [r3] 80071ea: f402 1300 and.w r3, r2, #2097152 @ 0x200000 80071ee: 64bb str r3, [r7, #72] @ 0x48 80071f0: 2300 movs r3, #0 80071f2: 64fb str r3, [r7, #76] @ 0x4c 80071f4: e9d7 1212 ldrd r1, r2, [r7, #72] @ 0x48 80071f8: 460b mov r3, r1 80071fa: 4313 orrs r3, r2 80071fc: d009 beq.n 8007212 { /* Check the parameters */ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); /* Configure the DFSDM1 interface clock source */ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); 80071fe: 4b92 ldr r3, [pc, #584] @ (8007448 ) 8007200: 6d1b ldr r3, [r3, #80] @ 0x50 8007202: f023 7180 bic.w r1, r3, #16777216 @ 0x1000000 8007206: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800720a: 6edb ldr r3, [r3, #108] @ 0x6c 800720c: 4a8e ldr r2, [pc, #568] @ (8007448 ) 800720e: 430b orrs r3, r1 8007210: 6513 str r3, [r2, #80] @ 0x50 __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); } #endif /* DFSDM2 */ /*------------------------------------ TIM configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) 8007212: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8007216: e9d3 2300 ldrd r2, r3, [r3] 800721a: f002 4380 and.w r3, r2, #1073741824 @ 0x40000000 800721e: 643b str r3, [r7, #64] @ 0x40 8007220: 2300 movs r3, #0 8007222: 647b str r3, [r7, #68] @ 0x44 8007224: e9d7 1210 ldrd r1, r2, [r7, #64] @ 0x40 8007228: 460b mov r3, r1 800722a: 4313 orrs r3, r2 800722c: d00e beq.n 800724c { /* Check the parameters */ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 800722e: 4b86 ldr r3, [pc, #536] @ (8007448 ) 8007230: 691b ldr r3, [r3, #16] 8007232: 4a85 ldr r2, [pc, #532] @ (8007448 ) 8007234: f423 4300 bic.w r3, r3, #32768 @ 0x8000 8007238: 6113 str r3, [r2, #16] 800723a: 4b83 ldr r3, [pc, #524] @ (8007448 ) 800723c: 6919 ldr r1, [r3, #16] 800723e: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8007242: f8d3 30bc ldr.w r3, [r3, #188] @ 0xbc 8007246: 4a80 ldr r2, [pc, #512] @ (8007448 ) 8007248: 430b orrs r3, r1 800724a: 6113 str r3, [r2, #16] } /*------------------------------------ CKPER configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) 800724c: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8007250: e9d3 2300 ldrd r2, r3, [r3] 8007254: f002 4300 and.w r3, r2, #2147483648 @ 0x80000000 8007258: 63bb str r3, [r7, #56] @ 0x38 800725a: 2300 movs r3, #0 800725c: 63fb str r3, [r7, #60] @ 0x3c 800725e: e9d7 120e ldrd r1, r2, [r7, #56] @ 0x38 8007262: 460b mov r3, r1 8007264: 4313 orrs r3, r2 8007266: d009 beq.n 800727c { /* Check the parameters */ assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection)); /* Configure the CKPER clock source */ __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); 8007268: 4b77 ldr r3, [pc, #476] @ (8007448 ) 800726a: 6cdb ldr r3, [r3, #76] @ 0x4c 800726c: f023 5140 bic.w r1, r3, #805306368 @ 0x30000000 8007270: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8007274: 6d5b ldr r3, [r3, #84] @ 0x54 8007276: 4a74 ldr r2, [pc, #464] @ (8007448 ) 8007278: 430b orrs r3, r1 800727a: 64d3 str r3, [r2, #76] @ 0x4c } /*------------------------------ CEC Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 800727c: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8007280: e9d3 2300 ldrd r2, r3, [r3] 8007284: f402 0300 and.w r3, r2, #8388608 @ 0x800000 8007288: 633b str r3, [r7, #48] @ 0x30 800728a: 2300 movs r3, #0 800728c: 637b str r3, [r7, #52] @ 0x34 800728e: e9d7 120c ldrd r1, r2, [r7, #48] @ 0x30 8007292: 460b mov r3, r1 8007294: 4313 orrs r3, r2 8007296: d00a beq.n 80072ae { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC interface clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 8007298: 4b6b ldr r3, [pc, #428] @ (8007448 ) 800729a: 6d5b ldr r3, [r3, #84] @ 0x54 800729c: f423 0140 bic.w r1, r3, #12582912 @ 0xc00000 80072a0: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80072a4: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80072a8: 4a67 ldr r2, [pc, #412] @ (8007448 ) 80072aa: 430b orrs r3, r1 80072ac: 6553 str r3, [r2, #84] @ 0x54 } /*---------------------------- PLL2 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP) 80072ae: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80072b2: e9d3 2300 ldrd r2, r3, [r3] 80072b6: 2100 movs r1, #0 80072b8: 62b9 str r1, [r7, #40] @ 0x28 80072ba: f003 0301 and.w r3, r3, #1 80072be: 62fb str r3, [r7, #44] @ 0x2c 80072c0: e9d7 120a ldrd r1, r2, [r7, #40] @ 0x28 80072c4: 460b mov r3, r1 80072c6: 4313 orrs r3, r2 80072c8: d011 beq.n 80072ee { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 80072ca: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80072ce: 3308 adds r3, #8 80072d0: 2100 movs r1, #0 80072d2: 4618 mov r0, r3 80072d4: f001 fa4a bl 800876c 80072d8: 4603 mov r3, r0 80072da: f887 3127 strb.w r3, [r7, #295] @ 0x127 if (ret == HAL_OK) 80072de: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 80072e2: 2b00 cmp r3, #0 80072e4: d003 beq.n 80072ee /*Nothing to do*/ } else { /* set overall return value */ status = ret; 80072e6: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 80072ea: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ) 80072ee: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80072f2: e9d3 2300 ldrd r2, r3, [r3] 80072f6: 2100 movs r1, #0 80072f8: 6239 str r1, [r7, #32] 80072fa: f003 0302 and.w r3, r3, #2 80072fe: 627b str r3, [r7, #36] @ 0x24 8007300: e9d7 1208 ldrd r1, r2, [r7, #32] 8007304: 460b mov r3, r1 8007306: 4313 orrs r3, r2 8007308: d011 beq.n 800732e { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800730a: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800730e: 3308 adds r3, #8 8007310: 2101 movs r1, #1 8007312: 4618 mov r0, r3 8007314: f001 fa2a bl 800876c 8007318: 4603 mov r3, r0 800731a: f887 3127 strb.w r3, [r7, #295] @ 0x127 if (ret == HAL_OK) 800731e: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8007322: 2b00 cmp r3, #0 8007324: d003 beq.n 800732e /*Nothing to do*/ } else { /* set overall return value */ status = ret; 8007326: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 800732a: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR) 800732e: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8007332: e9d3 2300 ldrd r2, r3, [r3] 8007336: 2100 movs r1, #0 8007338: 61b9 str r1, [r7, #24] 800733a: f003 0304 and.w r3, r3, #4 800733e: 61fb str r3, [r7, #28] 8007340: e9d7 1206 ldrd r1, r2, [r7, #24] 8007344: 460b mov r3, r1 8007346: 4313 orrs r3, r2 8007348: d011 beq.n 800736e { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800734a: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800734e: 3308 adds r3, #8 8007350: 2102 movs r1, #2 8007352: 4618 mov r0, r3 8007354: f001 fa0a bl 800876c 8007358: 4603 mov r3, r0 800735a: f887 3127 strb.w r3, [r7, #295] @ 0x127 if (ret == HAL_OK) 800735e: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8007362: 2b00 cmp r3, #0 8007364: d003 beq.n 800736e /*Nothing to do*/ } else { /* set overall return value */ status = ret; 8007366: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 800736a: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } /*---------------------------- PLL3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP) 800736e: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8007372: e9d3 2300 ldrd r2, r3, [r3] 8007376: 2100 movs r1, #0 8007378: 6139 str r1, [r7, #16] 800737a: f003 0308 and.w r3, r3, #8 800737e: 617b str r3, [r7, #20] 8007380: e9d7 1204 ldrd r1, r2, [r7, #16] 8007384: 460b mov r3, r1 8007386: 4313 orrs r3, r2 8007388: d011 beq.n 80073ae { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800738a: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800738e: 3328 adds r3, #40 @ 0x28 8007390: 2100 movs r1, #0 8007392: 4618 mov r0, r3 8007394: f001 fa9c bl 80088d0 8007398: 4603 mov r3, r0 800739a: f887 3127 strb.w r3, [r7, #295] @ 0x127 if (ret == HAL_OK) 800739e: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 80073a2: 2b00 cmp r3, #0 80073a4: d003 beq.n 80073ae /*Nothing to do*/ } else { /* set overall return value */ status = ret; 80073a6: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 80073aa: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ) 80073ae: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80073b2: e9d3 2300 ldrd r2, r3, [r3] 80073b6: 2100 movs r1, #0 80073b8: 60b9 str r1, [r7, #8] 80073ba: f003 0310 and.w r3, r3, #16 80073be: 60fb str r3, [r7, #12] 80073c0: e9d7 1202 ldrd r1, r2, [r7, #8] 80073c4: 460b mov r3, r1 80073c6: 4313 orrs r3, r2 80073c8: d011 beq.n 80073ee { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 80073ca: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80073ce: 3328 adds r3, #40 @ 0x28 80073d0: 2101 movs r1, #1 80073d2: 4618 mov r0, r3 80073d4: f001 fa7c bl 80088d0 80073d8: 4603 mov r3, r0 80073da: f887 3127 strb.w r3, [r7, #295] @ 0x127 if (ret == HAL_OK) 80073de: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 80073e2: 2b00 cmp r3, #0 80073e4: d003 beq.n 80073ee /*Nothing to do*/ } else { /* set overall return value */ status = ret; 80073e6: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 80073ea: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR) 80073ee: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 80073f2: e9d3 2300 ldrd r2, r3, [r3] 80073f6: 2100 movs r1, #0 80073f8: 6039 str r1, [r7, #0] 80073fa: f003 0320 and.w r3, r3, #32 80073fe: 607b str r3, [r7, #4] 8007400: e9d7 1200 ldrd r1, r2, [r7] 8007404: 460b mov r3, r1 8007406: 4313 orrs r3, r2 8007408: d011 beq.n 800742e { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800740a: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800740e: 3328 adds r3, #40 @ 0x28 8007410: 2102 movs r1, #2 8007412: 4618 mov r0, r3 8007414: f001 fa5c bl 80088d0 8007418: 4603 mov r3, r0 800741a: f887 3127 strb.w r3, [r7, #295] @ 0x127 if (ret == HAL_OK) 800741e: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 8007422: 2b00 cmp r3, #0 8007424: d003 beq.n 800742e /*Nothing to do*/ } else { /* set overall return value */ status = ret; 8007426: f897 3127 ldrb.w r3, [r7, #295] @ 0x127 800742a: f887 3126 strb.w r3, [r7, #294] @ 0x126 } } if (status == HAL_OK) 800742e: f897 3126 ldrb.w r3, [r7, #294] @ 0x126 8007432: 2b00 cmp r3, #0 8007434: d101 bne.n 800743a { return HAL_OK; 8007436: 2300 movs r3, #0 8007438: e000 b.n 800743c } return HAL_ERROR; 800743a: 2301 movs r3, #1 } 800743c: 4618 mov r0, r3 800743e: f507 7794 add.w r7, r7, #296 @ 0x128 8007442: 46bd mov sp, r7 8007444: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8007448: 58024400 .word 0x58024400 0800744c : * @retval Frequency in KHz * * (*) : Available on some STM32H7 lines only. */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) { 800744c: b580 push {r7, lr} 800744e: b090 sub sp, #64 @ 0x40 8007450: af00 add r7, sp, #0 8007452: e9c7 0100 strd r0, r1, [r7] /* This variable is used to store the SAI and CKP clock source */ uint32_t saiclocksource; uint32_t ckpclocksource; uint32_t srcclk; if (PeriphClk == RCC_PERIPHCLK_SAI1) 8007456: e9d7 2300 ldrd r2, r3, [r7] 800745a: f5a2 7180 sub.w r1, r2, #256 @ 0x100 800745e: 430b orrs r3, r1 8007460: f040 8094 bne.w 800758c { saiclocksource = __HAL_RCC_GET_SAI1_SOURCE(); 8007464: 4b9e ldr r3, [pc, #632] @ (80076e0 ) 8007466: 6d1b ldr r3, [r3, #80] @ 0x50 8007468: f003 0307 and.w r3, r3, #7 800746c: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800746e: 6b3b ldr r3, [r7, #48] @ 0x30 8007470: 2b04 cmp r3, #4 8007472: f200 8087 bhi.w 8007584 8007476: a201 add r2, pc, #4 @ (adr r2, 800747c ) 8007478: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800747c: 08007491 .word 0x08007491 8007480: 080074b9 .word 0x080074b9 8007484: 080074e1 .word 0x080074e1 8007488: 0800757d .word 0x0800757d 800748c: 08007509 .word 0x08007509 { case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 8007490: 4b93 ldr r3, [pc, #588] @ (80076e0 ) 8007492: 681b ldr r3, [r3, #0] 8007494: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8007498: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800749c: d108 bne.n 80074b0 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800749e: f107 0324 add.w r3, r7, #36 @ 0x24 80074a2: 4618 mov r0, r3 80074a4: f001 f810 bl 80084c8 frequency = pll1_clocks.PLL1_Q_Frequency; 80074a8: 6abb ldr r3, [r7, #40] @ 0x28 80074aa: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 80074ac: f000 bd45 b.w 8007f3a frequency = 0; 80074b0: 2300 movs r3, #0 80074b2: 63fb str r3, [r7, #60] @ 0x3c break; 80074b4: f000 bd41 b.w 8007f3a } case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 80074b8: 4b89 ldr r3, [pc, #548] @ (80076e0 ) 80074ba: 681b ldr r3, [r3, #0] 80074bc: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 80074c0: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 80074c4: d108 bne.n 80074d8 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 80074c6: f107 0318 add.w r3, r7, #24 80074ca: 4618 mov r0, r3 80074cc: f000 fd54 bl 8007f78 frequency = pll2_clocks.PLL2_P_Frequency; 80074d0: 69bb ldr r3, [r7, #24] 80074d2: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 80074d4: f000 bd31 b.w 8007f3a frequency = 0; 80074d8: 2300 movs r3, #0 80074da: 63fb str r3, [r7, #60] @ 0x3c break; 80074dc: f000 bd2d b.w 8007f3a } case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 80074e0: 4b7f ldr r3, [pc, #508] @ (80076e0 ) 80074e2: 681b ldr r3, [r3, #0] 80074e4: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 80074e8: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80074ec: d108 bne.n 8007500 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 80074ee: f107 030c add.w r3, r7, #12 80074f2: 4618 mov r0, r3 80074f4: f000 fe94 bl 8008220 frequency = pll3_clocks.PLL3_P_Frequency; 80074f8: 68fb ldr r3, [r7, #12] 80074fa: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 80074fc: f000 bd1d b.w 8007f3a frequency = 0; 8007500: 2300 movs r3, #0 8007502: 63fb str r3, [r7, #60] @ 0x3c break; 8007504: f000 bd19 b.w 8007f3a } case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 8007508: 4b75 ldr r3, [pc, #468] @ (80076e0 ) 800750a: 6cdb ldr r3, [r3, #76] @ 0x4c 800750c: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 8007510: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 8007512: 4b73 ldr r3, [pc, #460] @ (80076e0 ) 8007514: 681b ldr r3, [r3, #0] 8007516: f003 0304 and.w r3, r3, #4 800751a: 2b04 cmp r3, #4 800751c: d10c bne.n 8007538 800751e: 6b7b ldr r3, [r7, #52] @ 0x34 8007520: 2b00 cmp r3, #0 8007522: d109 bne.n 8007538 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8007524: 4b6e ldr r3, [pc, #440] @ (80076e0 ) 8007526: 681b ldr r3, [r3, #0] 8007528: 08db lsrs r3, r3, #3 800752a: f003 0303 and.w r3, r3, #3 800752e: 4a6d ldr r2, [pc, #436] @ (80076e4 ) 8007530: fa22 f303 lsr.w r3, r2, r3 8007534: 63fb str r3, [r7, #60] @ 0x3c 8007536: e01f b.n 8007578 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 8007538: 4b69 ldr r3, [pc, #420] @ (80076e0 ) 800753a: 681b ldr r3, [r3, #0] 800753c: f403 7380 and.w r3, r3, #256 @ 0x100 8007540: f5b3 7f80 cmp.w r3, #256 @ 0x100 8007544: d106 bne.n 8007554 8007546: 6b7b ldr r3, [r7, #52] @ 0x34 8007548: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800754c: d102 bne.n 8007554 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800754e: 4b66 ldr r3, [pc, #408] @ (80076e8 ) 8007550: 63fb str r3, [r7, #60] @ 0x3c 8007552: e011 b.n 8007578 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 8007554: 4b62 ldr r3, [pc, #392] @ (80076e0 ) 8007556: 681b ldr r3, [r3, #0] 8007558: f403 3300 and.w r3, r3, #131072 @ 0x20000 800755c: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8007560: d106 bne.n 8007570 8007562: 6b7b ldr r3, [r7, #52] @ 0x34 8007564: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8007568: d102 bne.n 8007570 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800756a: 4b60 ldr r3, [pc, #384] @ (80076ec ) 800756c: 63fb str r3, [r7, #60] @ 0x3c 800756e: e003 b.n 8007578 } else { /* In Case the CKPER is disabled*/ frequency = 0; 8007570: 2300 movs r3, #0 8007572: 63fb str r3, [r7, #60] @ 0x3c } break; 8007574: f000 bce1 b.w 8007f3a 8007578: f000 bcdf b.w 8007f3a } case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */ { frequency = EXTERNAL_CLOCK_VALUE; 800757c: 4b5c ldr r3, [pc, #368] @ (80076f0 ) 800757e: 63fb str r3, [r7, #60] @ 0x3c break; 8007580: f000 bcdb b.w 8007f3a } default : { frequency = 0; 8007584: 2300 movs r3, #0 8007586: 63fb str r3, [r7, #60] @ 0x3c break; 8007588: f000 bcd7 b.w 8007f3a } } } #if defined(SAI3) else if (PeriphClk == RCC_PERIPHCLK_SAI23) 800758c: e9d7 2300 ldrd r2, r3, [r7] 8007590: f5a2 7100 sub.w r1, r2, #512 @ 0x200 8007594: 430b orrs r3, r1 8007596: f040 80ad bne.w 80076f4 { saiclocksource = __HAL_RCC_GET_SAI23_SOURCE(); 800759a: 4b51 ldr r3, [pc, #324] @ (80076e0 ) 800759c: 6d1b ldr r3, [r3, #80] @ 0x50 800759e: f403 73e0 and.w r3, r3, #448 @ 0x1c0 80075a2: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 80075a4: 6b3b ldr r3, [r7, #48] @ 0x30 80075a6: f5b3 7f80 cmp.w r3, #256 @ 0x100 80075aa: d056 beq.n 800765a 80075ac: 6b3b ldr r3, [r7, #48] @ 0x30 80075ae: f5b3 7f80 cmp.w r3, #256 @ 0x100 80075b2: f200 8090 bhi.w 80076d6 80075b6: 6b3b ldr r3, [r7, #48] @ 0x30 80075b8: 2bc0 cmp r3, #192 @ 0xc0 80075ba: f000 8088 beq.w 80076ce 80075be: 6b3b ldr r3, [r7, #48] @ 0x30 80075c0: 2bc0 cmp r3, #192 @ 0xc0 80075c2: f200 8088 bhi.w 80076d6 80075c6: 6b3b ldr r3, [r7, #48] @ 0x30 80075c8: 2b80 cmp r3, #128 @ 0x80 80075ca: d032 beq.n 8007632 80075cc: 6b3b ldr r3, [r7, #48] @ 0x30 80075ce: 2b80 cmp r3, #128 @ 0x80 80075d0: f200 8081 bhi.w 80076d6 80075d4: 6b3b ldr r3, [r7, #48] @ 0x30 80075d6: 2b00 cmp r3, #0 80075d8: d003 beq.n 80075e2 80075da: 6b3b ldr r3, [r7, #48] @ 0x30 80075dc: 2b40 cmp r3, #64 @ 0x40 80075de: d014 beq.n 800760a 80075e0: e079 b.n 80076d6 { case RCC_SAI23CLKSOURCE_PLL: /* PLL1 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 80075e2: 4b3f ldr r3, [pc, #252] @ (80076e0 ) 80075e4: 681b ldr r3, [r3, #0] 80075e6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80075ea: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 80075ee: d108 bne.n 8007602 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 80075f0: f107 0324 add.w r3, r7, #36 @ 0x24 80075f4: 4618 mov r0, r3 80075f6: f000 ff67 bl 80084c8 frequency = pll1_clocks.PLL1_Q_Frequency; 80075fa: 6abb ldr r3, [r7, #40] @ 0x28 80075fc: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 80075fe: f000 bc9c b.w 8007f3a frequency = 0; 8007602: 2300 movs r3, #0 8007604: 63fb str r3, [r7, #60] @ 0x3c break; 8007606: f000 bc98 b.w 8007f3a } case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800760a: 4b35 ldr r3, [pc, #212] @ (80076e0 ) 800760c: 681b ldr r3, [r3, #0] 800760e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8007612: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8007616: d108 bne.n 800762a { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8007618: f107 0318 add.w r3, r7, #24 800761c: 4618 mov r0, r3 800761e: f000 fcab bl 8007f78 frequency = pll2_clocks.PLL2_P_Frequency; 8007622: 69bb ldr r3, [r7, #24] 8007624: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 8007626: f000 bc88 b.w 8007f3a frequency = 0; 800762a: 2300 movs r3, #0 800762c: 63fb str r3, [r7, #60] @ 0x3c break; 800762e: f000 bc84 b.w 8007f3a } case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 8007632: 4b2b ldr r3, [pc, #172] @ (80076e0 ) 8007634: 681b ldr r3, [r3, #0] 8007636: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800763a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800763e: d108 bne.n 8007652 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8007640: f107 030c add.w r3, r7, #12 8007644: 4618 mov r0, r3 8007646: f000 fdeb bl 8008220 frequency = pll3_clocks.PLL3_P_Frequency; 800764a: 68fb ldr r3, [r7, #12] 800764c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800764e: f000 bc74 b.w 8007f3a frequency = 0; 8007652: 2300 movs r3, #0 8007654: 63fb str r3, [r7, #60] @ 0x3c break; 8007656: f000 bc70 b.w 8007f3a } case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800765a: 4b21 ldr r3, [pc, #132] @ (80076e0 ) 800765c: 6cdb ldr r3, [r3, #76] @ 0x4c 800765e: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 8007662: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 8007664: 4b1e ldr r3, [pc, #120] @ (80076e0 ) 8007666: 681b ldr r3, [r3, #0] 8007668: f003 0304 and.w r3, r3, #4 800766c: 2b04 cmp r3, #4 800766e: d10c bne.n 800768a 8007670: 6b7b ldr r3, [r7, #52] @ 0x34 8007672: 2b00 cmp r3, #0 8007674: d109 bne.n 800768a { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8007676: 4b1a ldr r3, [pc, #104] @ (80076e0 ) 8007678: 681b ldr r3, [r3, #0] 800767a: 08db lsrs r3, r3, #3 800767c: f003 0303 and.w r3, r3, #3 8007680: 4a18 ldr r2, [pc, #96] @ (80076e4 ) 8007682: fa22 f303 lsr.w r3, r2, r3 8007686: 63fb str r3, [r7, #60] @ 0x3c 8007688: e01f b.n 80076ca } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800768a: 4b15 ldr r3, [pc, #84] @ (80076e0 ) 800768c: 681b ldr r3, [r3, #0] 800768e: f403 7380 and.w r3, r3, #256 @ 0x100 8007692: f5b3 7f80 cmp.w r3, #256 @ 0x100 8007696: d106 bne.n 80076a6 8007698: 6b7b ldr r3, [r7, #52] @ 0x34 800769a: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800769e: d102 bne.n 80076a6 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 80076a0: 4b11 ldr r3, [pc, #68] @ (80076e8 ) 80076a2: 63fb str r3, [r7, #60] @ 0x3c 80076a4: e011 b.n 80076ca } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 80076a6: 4b0e ldr r3, [pc, #56] @ (80076e0 ) 80076a8: 681b ldr r3, [r3, #0] 80076aa: f403 3300 and.w r3, r3, #131072 @ 0x20000 80076ae: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 80076b2: d106 bne.n 80076c2 80076b4: 6b7b ldr r3, [r7, #52] @ 0x34 80076b6: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80076ba: d102 bne.n 80076c2 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 80076bc: 4b0b ldr r3, [pc, #44] @ (80076ec ) 80076be: 63fb str r3, [r7, #60] @ 0x3c 80076c0: e003 b.n 80076ca } else { /* In Case the CKPER is disabled*/ frequency = 0; 80076c2: 2300 movs r3, #0 80076c4: 63fb str r3, [r7, #60] @ 0x3c } break; 80076c6: f000 bc38 b.w 8007f3a 80076ca: f000 bc36 b.w 8007f3a } case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */ { frequency = EXTERNAL_CLOCK_VALUE; 80076ce: 4b08 ldr r3, [pc, #32] @ (80076f0 ) 80076d0: 63fb str r3, [r7, #60] @ 0x3c break; 80076d2: f000 bc32 b.w 8007f3a } default : { frequency = 0; 80076d6: 2300 movs r3, #0 80076d8: 63fb str r3, [r7, #60] @ 0x3c break; 80076da: f000 bc2e b.w 8007f3a 80076de: bf00 nop 80076e0: 58024400 .word 0x58024400 80076e4: 03d09000 .word 0x03d09000 80076e8: 003d0900 .word 0x003d0900 80076ec: 007a1200 .word 0x007a1200 80076f0: 00bb8000 .word 0x00bb8000 } } #endif #if defined(SAI4) else if (PeriphClk == RCC_PERIPHCLK_SAI4A) 80076f4: e9d7 2300 ldrd r2, r3, [r7] 80076f8: f5a2 6180 sub.w r1, r2, #1024 @ 0x400 80076fc: 430b orrs r3, r1 80076fe: f040 809c bne.w 800783a { saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE(); 8007702: 4b9e ldr r3, [pc, #632] @ (800797c ) 8007704: 6d9b ldr r3, [r3, #88] @ 0x58 8007706: f403 0360 and.w r3, r3, #14680064 @ 0xe00000 800770a: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800770c: 6b3b ldr r3, [r7, #48] @ 0x30 800770e: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 8007712: d054 beq.n 80077be 8007714: 6b3b ldr r3, [r7, #48] @ 0x30 8007716: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800771a: f200 808b bhi.w 8007834 800771e: 6b3b ldr r3, [r7, #48] @ 0x30 8007720: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 8007724: f000 8083 beq.w 800782e 8007728: 6b3b ldr r3, [r7, #48] @ 0x30 800772a: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800772e: f200 8081 bhi.w 8007834 8007732: 6b3b ldr r3, [r7, #48] @ 0x30 8007734: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8007738: d02f beq.n 800779a 800773a: 6b3b ldr r3, [r7, #48] @ 0x30 800773c: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8007740: d878 bhi.n 8007834 8007742: 6b3b ldr r3, [r7, #48] @ 0x30 8007744: 2b00 cmp r3, #0 8007746: d004 beq.n 8007752 8007748: 6b3b ldr r3, [r7, #48] @ 0x30 800774a: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800774e: d012 beq.n 8007776 8007750: e070 b.n 8007834 { case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 8007752: 4b8a ldr r3, [pc, #552] @ (800797c ) 8007754: 681b ldr r3, [r3, #0] 8007756: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800775a: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800775e: d107 bne.n 8007770 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 8007760: f107 0324 add.w r3, r7, #36 @ 0x24 8007764: 4618 mov r0, r3 8007766: f000 feaf bl 80084c8 frequency = pll1_clocks.PLL1_Q_Frequency; 800776a: 6abb ldr r3, [r7, #40] @ 0x28 800776c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800776e: e3e4 b.n 8007f3a frequency = 0; 8007770: 2300 movs r3, #0 8007772: 63fb str r3, [r7, #60] @ 0x3c break; 8007774: e3e1 b.n 8007f3a } case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 8007776: 4b81 ldr r3, [pc, #516] @ (800797c ) 8007778: 681b ldr r3, [r3, #0] 800777a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800777e: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8007782: d107 bne.n 8007794 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8007784: f107 0318 add.w r3, r7, #24 8007788: 4618 mov r0, r3 800778a: f000 fbf5 bl 8007f78 frequency = pll2_clocks.PLL2_P_Frequency; 800778e: 69bb ldr r3, [r7, #24] 8007790: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 8007792: e3d2 b.n 8007f3a frequency = 0; 8007794: 2300 movs r3, #0 8007796: 63fb str r3, [r7, #60] @ 0x3c break; 8007798: e3cf b.n 8007f3a } case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800779a: 4b78 ldr r3, [pc, #480] @ (800797c ) 800779c: 681b ldr r3, [r3, #0] 800779e: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 80077a2: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80077a6: d107 bne.n 80077b8 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 80077a8: f107 030c add.w r3, r7, #12 80077ac: 4618 mov r0, r3 80077ae: f000 fd37 bl 8008220 frequency = pll3_clocks.PLL3_P_Frequency; 80077b2: 68fb ldr r3, [r7, #12] 80077b4: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 80077b6: e3c0 b.n 8007f3a frequency = 0; 80077b8: 2300 movs r3, #0 80077ba: 63fb str r3, [r7, #60] @ 0x3c break; 80077bc: e3bd b.n 8007f3a } case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 80077be: 4b6f ldr r3, [pc, #444] @ (800797c ) 80077c0: 6cdb ldr r3, [r3, #76] @ 0x4c 80077c2: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 80077c6: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 80077c8: 4b6c ldr r3, [pc, #432] @ (800797c ) 80077ca: 681b ldr r3, [r3, #0] 80077cc: f003 0304 and.w r3, r3, #4 80077d0: 2b04 cmp r3, #4 80077d2: d10c bne.n 80077ee 80077d4: 6b7b ldr r3, [r7, #52] @ 0x34 80077d6: 2b00 cmp r3, #0 80077d8: d109 bne.n 80077ee { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 80077da: 4b68 ldr r3, [pc, #416] @ (800797c ) 80077dc: 681b ldr r3, [r3, #0] 80077de: 08db lsrs r3, r3, #3 80077e0: f003 0303 and.w r3, r3, #3 80077e4: 4a66 ldr r2, [pc, #408] @ (8007980 ) 80077e6: fa22 f303 lsr.w r3, r2, r3 80077ea: 63fb str r3, [r7, #60] @ 0x3c 80077ec: e01e b.n 800782c } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 80077ee: 4b63 ldr r3, [pc, #396] @ (800797c ) 80077f0: 681b ldr r3, [r3, #0] 80077f2: f403 7380 and.w r3, r3, #256 @ 0x100 80077f6: f5b3 7f80 cmp.w r3, #256 @ 0x100 80077fa: d106 bne.n 800780a 80077fc: 6b7b ldr r3, [r7, #52] @ 0x34 80077fe: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8007802: d102 bne.n 800780a { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 8007804: 4b5f ldr r3, [pc, #380] @ (8007984 ) 8007806: 63fb str r3, [r7, #60] @ 0x3c 8007808: e010 b.n 800782c } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800780a: 4b5c ldr r3, [pc, #368] @ (800797c ) 800780c: 681b ldr r3, [r3, #0] 800780e: f403 3300 and.w r3, r3, #131072 @ 0x20000 8007812: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8007816: d106 bne.n 8007826 8007818: 6b7b ldr r3, [r7, #52] @ 0x34 800781a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800781e: d102 bne.n 8007826 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 8007820: 4b59 ldr r3, [pc, #356] @ (8007988 ) 8007822: 63fb str r3, [r7, #60] @ 0x3c 8007824: e002 b.n 800782c } else { /* In Case the CKPER is disabled*/ frequency = 0; 8007826: 2300 movs r3, #0 8007828: 63fb str r3, [r7, #60] @ 0x3c } break; 800782a: e386 b.n 8007f3a 800782c: e385 b.n 8007f3a } case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */ { frequency = EXTERNAL_CLOCK_VALUE; 800782e: 4b57 ldr r3, [pc, #348] @ (800798c ) 8007830: 63fb str r3, [r7, #60] @ 0x3c break; 8007832: e382 b.n 8007f3a } default : { frequency = 0; 8007834: 2300 movs r3, #0 8007836: 63fb str r3, [r7, #60] @ 0x3c break; 8007838: e37f b.n 8007f3a } } } else if (PeriphClk == RCC_PERIPHCLK_SAI4B) 800783a: e9d7 2300 ldrd r2, r3, [r7] 800783e: f5a2 6100 sub.w r1, r2, #2048 @ 0x800 8007842: 430b orrs r3, r1 8007844: f040 80a7 bne.w 8007996 { saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE(); 8007848: 4b4c ldr r3, [pc, #304] @ (800797c ) 800784a: 6d9b ldr r3, [r3, #88] @ 0x58 800784c: f003 63e0 and.w r3, r3, #117440512 @ 0x7000000 8007850: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 8007852: 6b3b ldr r3, [r7, #48] @ 0x30 8007854: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 8007858: d055 beq.n 8007906 800785a: 6b3b ldr r3, [r7, #48] @ 0x30 800785c: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 8007860: f200 8096 bhi.w 8007990 8007864: 6b3b ldr r3, [r7, #48] @ 0x30 8007866: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800786a: f000 8084 beq.w 8007976 800786e: 6b3b ldr r3, [r7, #48] @ 0x30 8007870: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 8007874: f200 808c bhi.w 8007990 8007878: 6b3b ldr r3, [r7, #48] @ 0x30 800787a: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800787e: d030 beq.n 80078e2 8007880: 6b3b ldr r3, [r7, #48] @ 0x30 8007882: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 8007886: f200 8083 bhi.w 8007990 800788a: 6b3b ldr r3, [r7, #48] @ 0x30 800788c: 2b00 cmp r3, #0 800788e: d004 beq.n 800789a 8007890: 6b3b ldr r3, [r7, #48] @ 0x30 8007892: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8007896: d012 beq.n 80078be 8007898: e07a b.n 8007990 { case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800789a: 4b38 ldr r3, [pc, #224] @ (800797c ) 800789c: 681b ldr r3, [r3, #0] 800789e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80078a2: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 80078a6: d107 bne.n 80078b8 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 80078a8: f107 0324 add.w r3, r7, #36 @ 0x24 80078ac: 4618 mov r0, r3 80078ae: f000 fe0b bl 80084c8 frequency = pll1_clocks.PLL1_Q_Frequency; 80078b2: 6abb ldr r3, [r7, #40] @ 0x28 80078b4: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 80078b6: e340 b.n 8007f3a frequency = 0; 80078b8: 2300 movs r3, #0 80078ba: 63fb str r3, [r7, #60] @ 0x3c break; 80078bc: e33d b.n 8007f3a } case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 80078be: 4b2f ldr r3, [pc, #188] @ (800797c ) 80078c0: 681b ldr r3, [r3, #0] 80078c2: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 80078c6: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 80078ca: d107 bne.n 80078dc { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 80078cc: f107 0318 add.w r3, r7, #24 80078d0: 4618 mov r0, r3 80078d2: f000 fb51 bl 8007f78 frequency = pll2_clocks.PLL2_P_Frequency; 80078d6: 69bb ldr r3, [r7, #24] 80078d8: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 80078da: e32e b.n 8007f3a frequency = 0; 80078dc: 2300 movs r3, #0 80078de: 63fb str r3, [r7, #60] @ 0x3c break; 80078e0: e32b b.n 8007f3a } case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 80078e2: 4b26 ldr r3, [pc, #152] @ (800797c ) 80078e4: 681b ldr r3, [r3, #0] 80078e6: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 80078ea: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80078ee: d107 bne.n 8007900 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 80078f0: f107 030c add.w r3, r7, #12 80078f4: 4618 mov r0, r3 80078f6: f000 fc93 bl 8008220 frequency = pll3_clocks.PLL3_P_Frequency; 80078fa: 68fb ldr r3, [r7, #12] 80078fc: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 80078fe: e31c b.n 8007f3a frequency = 0; 8007900: 2300 movs r3, #0 8007902: 63fb str r3, [r7, #60] @ 0x3c break; 8007904: e319 b.n 8007f3a } case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 8007906: 4b1d ldr r3, [pc, #116] @ (800797c ) 8007908: 6cdb ldr r3, [r3, #76] @ 0x4c 800790a: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800790e: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 8007910: 4b1a ldr r3, [pc, #104] @ (800797c ) 8007912: 681b ldr r3, [r3, #0] 8007914: f003 0304 and.w r3, r3, #4 8007918: 2b04 cmp r3, #4 800791a: d10c bne.n 8007936 800791c: 6b7b ldr r3, [r7, #52] @ 0x34 800791e: 2b00 cmp r3, #0 8007920: d109 bne.n 8007936 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8007922: 4b16 ldr r3, [pc, #88] @ (800797c ) 8007924: 681b ldr r3, [r3, #0] 8007926: 08db lsrs r3, r3, #3 8007928: f003 0303 and.w r3, r3, #3 800792c: 4a14 ldr r2, [pc, #80] @ (8007980 ) 800792e: fa22 f303 lsr.w r3, r2, r3 8007932: 63fb str r3, [r7, #60] @ 0x3c 8007934: e01e b.n 8007974 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 8007936: 4b11 ldr r3, [pc, #68] @ (800797c ) 8007938: 681b ldr r3, [r3, #0] 800793a: f403 7380 and.w r3, r3, #256 @ 0x100 800793e: f5b3 7f80 cmp.w r3, #256 @ 0x100 8007942: d106 bne.n 8007952 8007944: 6b7b ldr r3, [r7, #52] @ 0x34 8007946: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800794a: d102 bne.n 8007952 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800794c: 4b0d ldr r3, [pc, #52] @ (8007984 ) 800794e: 63fb str r3, [r7, #60] @ 0x3c 8007950: e010 b.n 8007974 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 8007952: 4b0a ldr r3, [pc, #40] @ (800797c ) 8007954: 681b ldr r3, [r3, #0] 8007956: f403 3300 and.w r3, r3, #131072 @ 0x20000 800795a: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800795e: d106 bne.n 800796e 8007960: 6b7b ldr r3, [r7, #52] @ 0x34 8007962: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8007966: d102 bne.n 800796e { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 8007968: 4b07 ldr r3, [pc, #28] @ (8007988 ) 800796a: 63fb str r3, [r7, #60] @ 0x3c 800796c: e002 b.n 8007974 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800796e: 2300 movs r3, #0 8007970: 63fb str r3, [r7, #60] @ 0x3c } break; 8007972: e2e2 b.n 8007f3a 8007974: e2e1 b.n 8007f3a } case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */ { frequency = EXTERNAL_CLOCK_VALUE; 8007976: 4b05 ldr r3, [pc, #20] @ (800798c ) 8007978: 63fb str r3, [r7, #60] @ 0x3c break; 800797a: e2de b.n 8007f3a 800797c: 58024400 .word 0x58024400 8007980: 03d09000 .word 0x03d09000 8007984: 003d0900 .word 0x003d0900 8007988: 007a1200 .word 0x007a1200 800798c: 00bb8000 .word 0x00bb8000 } default : { frequency = 0; 8007990: 2300 movs r3, #0 8007992: 63fb str r3, [r7, #60] @ 0x3c break; 8007994: e2d1 b.n 8007f3a } } } #endif /*SAI4*/ else if (PeriphClk == RCC_PERIPHCLK_SPI123) 8007996: e9d7 2300 ldrd r2, r3, [r7] 800799a: f5a2 5180 sub.w r1, r2, #4096 @ 0x1000 800799e: 430b orrs r3, r1 80079a0: f040 809c bne.w 8007adc { /* Get SPI1/2/3 clock source */ srcclk = __HAL_RCC_GET_SPI123_SOURCE(); 80079a4: 4b93 ldr r3, [pc, #588] @ (8007bf4 ) 80079a6: 6d1b ldr r3, [r3, #80] @ 0x50 80079a8: f403 43e0 and.w r3, r3, #28672 @ 0x7000 80079ac: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 80079ae: 6bbb ldr r3, [r7, #56] @ 0x38 80079b0: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 80079b4: d054 beq.n 8007a60 80079b6: 6bbb ldr r3, [r7, #56] @ 0x38 80079b8: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 80079bc: f200 808b bhi.w 8007ad6 80079c0: 6bbb ldr r3, [r7, #56] @ 0x38 80079c2: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 80079c6: f000 8083 beq.w 8007ad0 80079ca: 6bbb ldr r3, [r7, #56] @ 0x38 80079cc: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 80079d0: f200 8081 bhi.w 8007ad6 80079d4: 6bbb ldr r3, [r7, #56] @ 0x38 80079d6: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80079da: d02f beq.n 8007a3c 80079dc: 6bbb ldr r3, [r7, #56] @ 0x38 80079de: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80079e2: d878 bhi.n 8007ad6 80079e4: 6bbb ldr r3, [r7, #56] @ 0x38 80079e6: 2b00 cmp r3, #0 80079e8: d004 beq.n 80079f4 80079ea: 6bbb ldr r3, [r7, #56] @ 0x38 80079ec: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80079f0: d012 beq.n 8007a18 80079f2: e070 b.n 8007ad6 { case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 80079f4: 4b7f ldr r3, [pc, #508] @ (8007bf4 ) 80079f6: 681b ldr r3, [r3, #0] 80079f8: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80079fc: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 8007a00: d107 bne.n 8007a12 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 8007a02: f107 0324 add.w r3, r7, #36 @ 0x24 8007a06: 4618 mov r0, r3 8007a08: f000 fd5e bl 80084c8 frequency = pll1_clocks.PLL1_Q_Frequency; 8007a0c: 6abb ldr r3, [r7, #40] @ 0x28 8007a0e: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 8007a10: e293 b.n 8007f3a frequency = 0; 8007a12: 2300 movs r3, #0 8007a14: 63fb str r3, [r7, #60] @ 0x3c break; 8007a16: e290 b.n 8007f3a } case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 8007a18: 4b76 ldr r3, [pc, #472] @ (8007bf4 ) 8007a1a: 681b ldr r3, [r3, #0] 8007a1c: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8007a20: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8007a24: d107 bne.n 8007a36 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8007a26: f107 0318 add.w r3, r7, #24 8007a2a: 4618 mov r0, r3 8007a2c: f000 faa4 bl 8007f78 frequency = pll2_clocks.PLL2_P_Frequency; 8007a30: 69bb ldr r3, [r7, #24] 8007a32: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 8007a34: e281 b.n 8007f3a frequency = 0; 8007a36: 2300 movs r3, #0 8007a38: 63fb str r3, [r7, #60] @ 0x3c break; 8007a3a: e27e b.n 8007f3a } case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 8007a3c: 4b6d ldr r3, [pc, #436] @ (8007bf4 ) 8007a3e: 681b ldr r3, [r3, #0] 8007a40: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8007a44: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8007a48: d107 bne.n 8007a5a { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8007a4a: f107 030c add.w r3, r7, #12 8007a4e: 4618 mov r0, r3 8007a50: f000 fbe6 bl 8008220 frequency = pll3_clocks.PLL3_P_Frequency; 8007a54: 68fb ldr r3, [r7, #12] 8007a56: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 8007a58: e26f b.n 8007f3a frequency = 0; 8007a5a: 2300 movs r3, #0 8007a5c: 63fb str r3, [r7, #60] @ 0x3c break; 8007a5e: e26c b.n 8007f3a } case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 8007a60: 4b64 ldr r3, [pc, #400] @ (8007bf4 ) 8007a62: 6cdb ldr r3, [r3, #76] @ 0x4c 8007a64: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 8007a68: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 8007a6a: 4b62 ldr r3, [pc, #392] @ (8007bf4 ) 8007a6c: 681b ldr r3, [r3, #0] 8007a6e: f003 0304 and.w r3, r3, #4 8007a72: 2b04 cmp r3, #4 8007a74: d10c bne.n 8007a90 8007a76: 6b7b ldr r3, [r7, #52] @ 0x34 8007a78: 2b00 cmp r3, #0 8007a7a: d109 bne.n 8007a90 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8007a7c: 4b5d ldr r3, [pc, #372] @ (8007bf4 ) 8007a7e: 681b ldr r3, [r3, #0] 8007a80: 08db lsrs r3, r3, #3 8007a82: f003 0303 and.w r3, r3, #3 8007a86: 4a5c ldr r2, [pc, #368] @ (8007bf8 ) 8007a88: fa22 f303 lsr.w r3, r2, r3 8007a8c: 63fb str r3, [r7, #60] @ 0x3c 8007a8e: e01e b.n 8007ace } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 8007a90: 4b58 ldr r3, [pc, #352] @ (8007bf4 ) 8007a92: 681b ldr r3, [r3, #0] 8007a94: f403 7380 and.w r3, r3, #256 @ 0x100 8007a98: f5b3 7f80 cmp.w r3, #256 @ 0x100 8007a9c: d106 bne.n 8007aac 8007a9e: 6b7b ldr r3, [r7, #52] @ 0x34 8007aa0: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8007aa4: d102 bne.n 8007aac { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 8007aa6: 4b55 ldr r3, [pc, #340] @ (8007bfc ) 8007aa8: 63fb str r3, [r7, #60] @ 0x3c 8007aaa: e010 b.n 8007ace } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 8007aac: 4b51 ldr r3, [pc, #324] @ (8007bf4 ) 8007aae: 681b ldr r3, [r3, #0] 8007ab0: f403 3300 and.w r3, r3, #131072 @ 0x20000 8007ab4: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8007ab8: d106 bne.n 8007ac8 8007aba: 6b7b ldr r3, [r7, #52] @ 0x34 8007abc: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8007ac0: d102 bne.n 8007ac8 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 8007ac2: 4b4f ldr r3, [pc, #316] @ (8007c00 ) 8007ac4: 63fb str r3, [r7, #60] @ 0x3c 8007ac6: e002 b.n 8007ace } else { /* In Case the CKPER is disabled*/ frequency = 0; 8007ac8: 2300 movs r3, #0 8007aca: 63fb str r3, [r7, #60] @ 0x3c } break; 8007acc: e235 b.n 8007f3a 8007ace: e234 b.n 8007f3a } case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */ { frequency = EXTERNAL_CLOCK_VALUE; 8007ad0: 4b4c ldr r3, [pc, #304] @ (8007c04 ) 8007ad2: 63fb str r3, [r7, #60] @ 0x3c break; 8007ad4: e231 b.n 8007f3a } default : { frequency = 0; 8007ad6: 2300 movs r3, #0 8007ad8: 63fb str r3, [r7, #60] @ 0x3c break; 8007ada: e22e b.n 8007f3a } } } else if (PeriphClk == RCC_PERIPHCLK_SPI45) 8007adc: e9d7 2300 ldrd r2, r3, [r7] 8007ae0: f5a2 5100 sub.w r1, r2, #8192 @ 0x2000 8007ae4: 430b orrs r3, r1 8007ae6: f040 808f bne.w 8007c08 { /* Get SPI45 clock source */ srcclk = __HAL_RCC_GET_SPI45_SOURCE(); 8007aea: 4b42 ldr r3, [pc, #264] @ (8007bf4 ) 8007aec: 6d1b ldr r3, [r3, #80] @ 0x50 8007aee: f403 23e0 and.w r3, r3, #458752 @ 0x70000 8007af2: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 8007af4: 6bbb ldr r3, [r7, #56] @ 0x38 8007af6: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8007afa: d06b beq.n 8007bd4 8007afc: 6bbb ldr r3, [r7, #56] @ 0x38 8007afe: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8007b02: d874 bhi.n 8007bee 8007b04: 6bbb ldr r3, [r7, #56] @ 0x38 8007b06: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8007b0a: d056 beq.n 8007bba 8007b0c: 6bbb ldr r3, [r7, #56] @ 0x38 8007b0e: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8007b12: d86c bhi.n 8007bee 8007b14: 6bbb ldr r3, [r7, #56] @ 0x38 8007b16: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8007b1a: d03b beq.n 8007b94 8007b1c: 6bbb ldr r3, [r7, #56] @ 0x38 8007b1e: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8007b22: d864 bhi.n 8007bee 8007b24: 6bbb ldr r3, [r7, #56] @ 0x38 8007b26: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8007b2a: d021 beq.n 8007b70 8007b2c: 6bbb ldr r3, [r7, #56] @ 0x38 8007b2e: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8007b32: d85c bhi.n 8007bee 8007b34: 6bbb ldr r3, [r7, #56] @ 0x38 8007b36: 2b00 cmp r3, #0 8007b38: d004 beq.n 8007b44 8007b3a: 6bbb ldr r3, [r7, #56] @ 0x38 8007b3c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8007b40: d004 beq.n 8007b4c 8007b42: e054 b.n 8007bee { case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 is the clock source for SPI4/5 */ { frequency = HAL_RCC_GetPCLK1Freq(); 8007b44: f7fe fa4c bl 8005fe0 8007b48: 63f8 str r0, [r7, #60] @ 0x3c break; 8007b4a: e1f6 b.n 8007f3a } case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 8007b4c: 4b29 ldr r3, [pc, #164] @ (8007bf4 ) 8007b4e: 681b ldr r3, [r3, #0] 8007b50: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8007b54: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8007b58: d107 bne.n 8007b6a { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8007b5a: f107 0318 add.w r3, r7, #24 8007b5e: 4618 mov r0, r3 8007b60: f000 fa0a bl 8007f78 frequency = pll2_clocks.PLL2_Q_Frequency; 8007b64: 69fb ldr r3, [r7, #28] 8007b66: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 8007b68: e1e7 b.n 8007f3a frequency = 0; 8007b6a: 2300 movs r3, #0 8007b6c: 63fb str r3, [r7, #60] @ 0x3c break; 8007b6e: e1e4 b.n 8007f3a } case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 8007b70: 4b20 ldr r3, [pc, #128] @ (8007bf4 ) 8007b72: 681b ldr r3, [r3, #0] 8007b74: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8007b78: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8007b7c: d107 bne.n 8007b8e { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8007b7e: f107 030c add.w r3, r7, #12 8007b82: 4618 mov r0, r3 8007b84: f000 fb4c bl 8008220 frequency = pll3_clocks.PLL3_Q_Frequency; 8007b88: 693b ldr r3, [r7, #16] 8007b8a: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 8007b8c: e1d5 b.n 8007f3a frequency = 0; 8007b8e: 2300 movs r3, #0 8007b90: 63fb str r3, [r7, #60] @ 0x3c break; 8007b92: e1d2 b.n 8007f3a } case RCC_SPI45CLKSOURCE_HSI: /* HSI is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 8007b94: 4b17 ldr r3, [pc, #92] @ (8007bf4 ) 8007b96: 681b ldr r3, [r3, #0] 8007b98: f003 0304 and.w r3, r3, #4 8007b9c: 2b04 cmp r3, #4 8007b9e: d109 bne.n 8007bb4 { frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8007ba0: 4b14 ldr r3, [pc, #80] @ (8007bf4 ) 8007ba2: 681b ldr r3, [r3, #0] 8007ba4: 08db lsrs r3, r3, #3 8007ba6: f003 0303 and.w r3, r3, #3 8007baa: 4a13 ldr r2, [pc, #76] @ (8007bf8 ) 8007bac: fa22 f303 lsr.w r3, r2, r3 8007bb0: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 8007bb2: e1c2 b.n 8007f3a frequency = 0; 8007bb4: 2300 movs r3, #0 8007bb6: 63fb str r3, [r7, #60] @ 0x3c break; 8007bb8: e1bf b.n 8007f3a } case RCC_SPI45CLKSOURCE_CSI: /* CSI is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 8007bba: 4b0e ldr r3, [pc, #56] @ (8007bf4 ) 8007bbc: 681b ldr r3, [r3, #0] 8007bbe: f403 7380 and.w r3, r3, #256 @ 0x100 8007bc2: f5b3 7f80 cmp.w r3, #256 @ 0x100 8007bc6: d102 bne.n 8007bce { frequency = CSI_VALUE; 8007bc8: 4b0c ldr r3, [pc, #48] @ (8007bfc ) 8007bca: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 8007bcc: e1b5 b.n 8007f3a frequency = 0; 8007bce: 2300 movs r3, #0 8007bd0: 63fb str r3, [r7, #60] @ 0x3c break; 8007bd2: e1b2 b.n 8007f3a } case RCC_SPI45CLKSOURCE_HSE: /* HSE is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 8007bd4: 4b07 ldr r3, [pc, #28] @ (8007bf4 ) 8007bd6: 681b ldr r3, [r3, #0] 8007bd8: f403 3300 and.w r3, r3, #131072 @ 0x20000 8007bdc: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8007be0: d102 bne.n 8007be8 { frequency = HSE_VALUE; 8007be2: 4b07 ldr r3, [pc, #28] @ (8007c00 ) 8007be4: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 8007be6: e1a8 b.n 8007f3a frequency = 0; 8007be8: 2300 movs r3, #0 8007bea: 63fb str r3, [r7, #60] @ 0x3c break; 8007bec: e1a5 b.n 8007f3a } default : { frequency = 0; 8007bee: 2300 movs r3, #0 8007bf0: 63fb str r3, [r7, #60] @ 0x3c break; 8007bf2: e1a2 b.n 8007f3a 8007bf4: 58024400 .word 0x58024400 8007bf8: 03d09000 .word 0x03d09000 8007bfc: 003d0900 .word 0x003d0900 8007c00: 007a1200 .word 0x007a1200 8007c04: 00bb8000 .word 0x00bb8000 } } } else if (PeriphClk == RCC_PERIPHCLK_ADC) 8007c08: e9d7 2300 ldrd r2, r3, [r7] 8007c0c: f5a2 2100 sub.w r1, r2, #524288 @ 0x80000 8007c10: 430b orrs r3, r1 8007c12: d173 bne.n 8007cfc { /* Get ADC clock source */ srcclk = __HAL_RCC_GET_ADC_SOURCE(); 8007c14: 4b9c ldr r3, [pc, #624] @ (8007e88 ) 8007c16: 6d9b ldr r3, [r3, #88] @ 0x58 8007c18: f403 3340 and.w r3, r3, #196608 @ 0x30000 8007c1c: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 8007c1e: 6bbb ldr r3, [r7, #56] @ 0x38 8007c20: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8007c24: d02f beq.n 8007c86 8007c26: 6bbb ldr r3, [r7, #56] @ 0x38 8007c28: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8007c2c: d863 bhi.n 8007cf6 8007c2e: 6bbb ldr r3, [r7, #56] @ 0x38 8007c30: 2b00 cmp r3, #0 8007c32: d004 beq.n 8007c3e 8007c34: 6bbb ldr r3, [r7, #56] @ 0x38 8007c36: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8007c3a: d012 beq.n 8007c62 8007c3c: e05b b.n 8007cf6 { case RCC_ADCCLKSOURCE_PLL2: { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 8007c3e: 4b92 ldr r3, [pc, #584] @ (8007e88 ) 8007c40: 681b ldr r3, [r3, #0] 8007c42: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8007c46: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8007c4a: d107 bne.n 8007c5c { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8007c4c: f107 0318 add.w r3, r7, #24 8007c50: 4618 mov r0, r3 8007c52: f000 f991 bl 8007f78 frequency = pll2_clocks.PLL2_P_Frequency; 8007c56: 69bb ldr r3, [r7, #24] 8007c58: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 8007c5a: e16e b.n 8007f3a frequency = 0; 8007c5c: 2300 movs r3, #0 8007c5e: 63fb str r3, [r7, #60] @ 0x3c break; 8007c60: e16b b.n 8007f3a } case RCC_ADCCLKSOURCE_PLL3: { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 8007c62: 4b89 ldr r3, [pc, #548] @ (8007e88 ) 8007c64: 681b ldr r3, [r3, #0] 8007c66: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8007c6a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8007c6e: d107 bne.n 8007c80 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8007c70: f107 030c add.w r3, r7, #12 8007c74: 4618 mov r0, r3 8007c76: f000 fad3 bl 8008220 frequency = pll3_clocks.PLL3_R_Frequency; 8007c7a: 697b ldr r3, [r7, #20] 8007c7c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 8007c7e: e15c b.n 8007f3a frequency = 0; 8007c80: 2300 movs r3, #0 8007c82: 63fb str r3, [r7, #60] @ 0x3c break; 8007c84: e159 b.n 8007f3a } case RCC_ADCCLKSOURCE_CLKP: { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 8007c86: 4b80 ldr r3, [pc, #512] @ (8007e88 ) 8007c88: 6cdb ldr r3, [r3, #76] @ 0x4c 8007c8a: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 8007c8e: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 8007c90: 4b7d ldr r3, [pc, #500] @ (8007e88 ) 8007c92: 681b ldr r3, [r3, #0] 8007c94: f003 0304 and.w r3, r3, #4 8007c98: 2b04 cmp r3, #4 8007c9a: d10c bne.n 8007cb6 8007c9c: 6b7b ldr r3, [r7, #52] @ 0x34 8007c9e: 2b00 cmp r3, #0 8007ca0: d109 bne.n 8007cb6 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8007ca2: 4b79 ldr r3, [pc, #484] @ (8007e88 ) 8007ca4: 681b ldr r3, [r3, #0] 8007ca6: 08db lsrs r3, r3, #3 8007ca8: f003 0303 and.w r3, r3, #3 8007cac: 4a77 ldr r2, [pc, #476] @ (8007e8c ) 8007cae: fa22 f303 lsr.w r3, r2, r3 8007cb2: 63fb str r3, [r7, #60] @ 0x3c 8007cb4: e01e b.n 8007cf4 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 8007cb6: 4b74 ldr r3, [pc, #464] @ (8007e88 ) 8007cb8: 681b ldr r3, [r3, #0] 8007cba: f403 7380 and.w r3, r3, #256 @ 0x100 8007cbe: f5b3 7f80 cmp.w r3, #256 @ 0x100 8007cc2: d106 bne.n 8007cd2 8007cc4: 6b7b ldr r3, [r7, #52] @ 0x34 8007cc6: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8007cca: d102 bne.n 8007cd2 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 8007ccc: 4b70 ldr r3, [pc, #448] @ (8007e90 ) 8007cce: 63fb str r3, [r7, #60] @ 0x3c 8007cd0: e010 b.n 8007cf4 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 8007cd2: 4b6d ldr r3, [pc, #436] @ (8007e88 ) 8007cd4: 681b ldr r3, [r3, #0] 8007cd6: f403 3300 and.w r3, r3, #131072 @ 0x20000 8007cda: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8007cde: d106 bne.n 8007cee 8007ce0: 6b7b ldr r3, [r7, #52] @ 0x34 8007ce2: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8007ce6: d102 bne.n 8007cee { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 8007ce8: 4b6a ldr r3, [pc, #424] @ (8007e94 ) 8007cea: 63fb str r3, [r7, #60] @ 0x3c 8007cec: e002 b.n 8007cf4 } else { /* In Case the CKPER is disabled*/ frequency = 0; 8007cee: 2300 movs r3, #0 8007cf0: 63fb str r3, [r7, #60] @ 0x3c } break; 8007cf2: e122 b.n 8007f3a 8007cf4: e121 b.n 8007f3a } default : { frequency = 0; 8007cf6: 2300 movs r3, #0 8007cf8: 63fb str r3, [r7, #60] @ 0x3c break; 8007cfa: e11e b.n 8007f3a } } } else if (PeriphClk == RCC_PERIPHCLK_SDMMC) 8007cfc: e9d7 2300 ldrd r2, r3, [r7] 8007d00: f5a2 3180 sub.w r1, r2, #65536 @ 0x10000 8007d04: 430b orrs r3, r1 8007d06: d133 bne.n 8007d70 { /* Get SDMMC clock source */ srcclk = __HAL_RCC_GET_SDMMC_SOURCE(); 8007d08: 4b5f ldr r3, [pc, #380] @ (8007e88 ) 8007d0a: 6cdb ldr r3, [r3, #76] @ 0x4c 8007d0c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8007d10: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 8007d12: 6bbb ldr r3, [r7, #56] @ 0x38 8007d14: 2b00 cmp r3, #0 8007d16: d004 beq.n 8007d22 8007d18: 6bbb ldr r3, [r7, #56] @ 0x38 8007d1a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8007d1e: d012 beq.n 8007d46 8007d20: e023 b.n 8007d6a { case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 8007d22: 4b59 ldr r3, [pc, #356] @ (8007e88 ) 8007d24: 681b ldr r3, [r3, #0] 8007d26: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8007d2a: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 8007d2e: d107 bne.n 8007d40 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 8007d30: f107 0324 add.w r3, r7, #36 @ 0x24 8007d34: 4618 mov r0, r3 8007d36: f000 fbc7 bl 80084c8 frequency = pll1_clocks.PLL1_Q_Frequency; 8007d3a: 6abb ldr r3, [r7, #40] @ 0x28 8007d3c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 8007d3e: e0fc b.n 8007f3a frequency = 0; 8007d40: 2300 movs r3, #0 8007d42: 63fb str r3, [r7, #60] @ 0x3c break; 8007d44: e0f9 b.n 8007f3a } case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 8007d46: 4b50 ldr r3, [pc, #320] @ (8007e88 ) 8007d48: 681b ldr r3, [r3, #0] 8007d4a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8007d4e: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8007d52: d107 bne.n 8007d64 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8007d54: f107 0318 add.w r3, r7, #24 8007d58: 4618 mov r0, r3 8007d5a: f000 f90d bl 8007f78 frequency = pll2_clocks.PLL2_R_Frequency; 8007d5e: 6a3b ldr r3, [r7, #32] 8007d60: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 8007d62: e0ea b.n 8007f3a frequency = 0; 8007d64: 2300 movs r3, #0 8007d66: 63fb str r3, [r7, #60] @ 0x3c break; 8007d68: e0e7 b.n 8007f3a } default : { frequency = 0; 8007d6a: 2300 movs r3, #0 8007d6c: 63fb str r3, [r7, #60] @ 0x3c break; 8007d6e: e0e4 b.n 8007f3a } } } else if (PeriphClk == RCC_PERIPHCLK_SPI6) 8007d70: e9d7 2300 ldrd r2, r3, [r7] 8007d74: f5a2 4180 sub.w r1, r2, #16384 @ 0x4000 8007d78: 430b orrs r3, r1 8007d7a: f040 808d bne.w 8007e98 { /* Get SPI6 clock source */ srcclk = __HAL_RCC_GET_SPI6_SOURCE(); 8007d7e: 4b42 ldr r3, [pc, #264] @ (8007e88 ) 8007d80: 6d9b ldr r3, [r3, #88] @ 0x58 8007d82: f003 43e0 and.w r3, r3, #1879048192 @ 0x70000000 8007d86: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 8007d88: 6bbb ldr r3, [r7, #56] @ 0x38 8007d8a: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8007d8e: d06b beq.n 8007e68 8007d90: 6bbb ldr r3, [r7, #56] @ 0x38 8007d92: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8007d96: d874 bhi.n 8007e82 8007d98: 6bbb ldr r3, [r7, #56] @ 0x38 8007d9a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8007d9e: d056 beq.n 8007e4e 8007da0: 6bbb ldr r3, [r7, #56] @ 0x38 8007da2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8007da6: d86c bhi.n 8007e82 8007da8: 6bbb ldr r3, [r7, #56] @ 0x38 8007daa: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 8007dae: d03b beq.n 8007e28 8007db0: 6bbb ldr r3, [r7, #56] @ 0x38 8007db2: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 8007db6: d864 bhi.n 8007e82 8007db8: 6bbb ldr r3, [r7, #56] @ 0x38 8007dba: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8007dbe: d021 beq.n 8007e04 8007dc0: 6bbb ldr r3, [r7, #56] @ 0x38 8007dc2: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8007dc6: d85c bhi.n 8007e82 8007dc8: 6bbb ldr r3, [r7, #56] @ 0x38 8007dca: 2b00 cmp r3, #0 8007dcc: d004 beq.n 8007dd8 8007dce: 6bbb ldr r3, [r7, #56] @ 0x38 8007dd0: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8007dd4: d004 beq.n 8007de0 8007dd6: e054 b.n 8007e82 { case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */ { frequency = HAL_RCCEx_GetD3PCLK1Freq(); 8007dd8: f000 f8b8 bl 8007f4c 8007ddc: 63f8 str r0, [r7, #60] @ 0x3c break; 8007dde: e0ac b.n 8007f3a } case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 8007de0: 4b29 ldr r3, [pc, #164] @ (8007e88 ) 8007de2: 681b ldr r3, [r3, #0] 8007de4: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8007de8: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8007dec: d107 bne.n 8007dfe { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8007dee: f107 0318 add.w r3, r7, #24 8007df2: 4618 mov r0, r3 8007df4: f000 f8c0 bl 8007f78 frequency = pll2_clocks.PLL2_Q_Frequency; 8007df8: 69fb ldr r3, [r7, #28] 8007dfa: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 8007dfc: e09d b.n 8007f3a frequency = 0; 8007dfe: 2300 movs r3, #0 8007e00: 63fb str r3, [r7, #60] @ 0x3c break; 8007e02: e09a b.n 8007f3a } case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 8007e04: 4b20 ldr r3, [pc, #128] @ (8007e88 ) 8007e06: 681b ldr r3, [r3, #0] 8007e08: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8007e0c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8007e10: d107 bne.n 8007e22 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8007e12: f107 030c add.w r3, r7, #12 8007e16: 4618 mov r0, r3 8007e18: f000 fa02 bl 8008220 frequency = pll3_clocks.PLL3_Q_Frequency; 8007e1c: 693b ldr r3, [r7, #16] 8007e1e: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 8007e20: e08b b.n 8007f3a frequency = 0; 8007e22: 2300 movs r3, #0 8007e24: 63fb str r3, [r7, #60] @ 0x3c break; 8007e26: e088 b.n 8007f3a } case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 8007e28: 4b17 ldr r3, [pc, #92] @ (8007e88 ) 8007e2a: 681b ldr r3, [r3, #0] 8007e2c: f003 0304 and.w r3, r3, #4 8007e30: 2b04 cmp r3, #4 8007e32: d109 bne.n 8007e48 { frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8007e34: 4b14 ldr r3, [pc, #80] @ (8007e88 ) 8007e36: 681b ldr r3, [r3, #0] 8007e38: 08db lsrs r3, r3, #3 8007e3a: f003 0303 and.w r3, r3, #3 8007e3e: 4a13 ldr r2, [pc, #76] @ (8007e8c ) 8007e40: fa22 f303 lsr.w r3, r2, r3 8007e44: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 8007e46: e078 b.n 8007f3a frequency = 0; 8007e48: 2300 movs r3, #0 8007e4a: 63fb str r3, [r7, #60] @ 0x3c break; 8007e4c: e075 b.n 8007f3a } case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 8007e4e: 4b0e ldr r3, [pc, #56] @ (8007e88 ) 8007e50: 681b ldr r3, [r3, #0] 8007e52: f403 7380 and.w r3, r3, #256 @ 0x100 8007e56: f5b3 7f80 cmp.w r3, #256 @ 0x100 8007e5a: d102 bne.n 8007e62 { frequency = CSI_VALUE; 8007e5c: 4b0c ldr r3, [pc, #48] @ (8007e90 ) 8007e5e: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 8007e60: e06b b.n 8007f3a frequency = 0; 8007e62: 2300 movs r3, #0 8007e64: 63fb str r3, [r7, #60] @ 0x3c break; 8007e66: e068 b.n 8007f3a } case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 8007e68: 4b07 ldr r3, [pc, #28] @ (8007e88 ) 8007e6a: 681b ldr r3, [r3, #0] 8007e6c: f403 3300 and.w r3, r3, #131072 @ 0x20000 8007e70: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8007e74: d102 bne.n 8007e7c { frequency = HSE_VALUE; 8007e76: 4b07 ldr r3, [pc, #28] @ (8007e94 ) 8007e78: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 8007e7a: e05e b.n 8007f3a frequency = 0; 8007e7c: 2300 movs r3, #0 8007e7e: 63fb str r3, [r7, #60] @ 0x3c break; 8007e80: e05b b.n 8007f3a break; } #endif /* RCC_SPI6CLKSOURCE_PIN */ default : { frequency = 0; 8007e82: 2300 movs r3, #0 8007e84: 63fb str r3, [r7, #60] @ 0x3c break; 8007e86: e058 b.n 8007f3a 8007e88: 58024400 .word 0x58024400 8007e8c: 03d09000 .word 0x03d09000 8007e90: 003d0900 .word 0x003d0900 8007e94: 007a1200 .word 0x007a1200 } } } else if (PeriphClk == RCC_PERIPHCLK_FDCAN) 8007e98: e9d7 2300 ldrd r2, r3, [r7] 8007e9c: f5a2 4100 sub.w r1, r2, #32768 @ 0x8000 8007ea0: 430b orrs r3, r1 8007ea2: d148 bne.n 8007f36 { /* Get FDCAN clock source */ srcclk = __HAL_RCC_GET_FDCAN_SOURCE(); 8007ea4: 4b27 ldr r3, [pc, #156] @ (8007f44 ) 8007ea6: 6d1b ldr r3, [r3, #80] @ 0x50 8007ea8: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 8007eac: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 8007eae: 6bbb ldr r3, [r7, #56] @ 0x38 8007eb0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8007eb4: d02a beq.n 8007f0c 8007eb6: 6bbb ldr r3, [r7, #56] @ 0x38 8007eb8: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8007ebc: d838 bhi.n 8007f30 8007ebe: 6bbb ldr r3, [r7, #56] @ 0x38 8007ec0: 2b00 cmp r3, #0 8007ec2: d004 beq.n 8007ece 8007ec4: 6bbb ldr r3, [r7, #56] @ 0x38 8007ec6: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8007eca: d00d beq.n 8007ee8 8007ecc: e030 b.n 8007f30 { case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 8007ece: 4b1d ldr r3, [pc, #116] @ (8007f44 ) 8007ed0: 681b ldr r3, [r3, #0] 8007ed2: f403 3300 and.w r3, r3, #131072 @ 0x20000 8007ed6: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8007eda: d102 bne.n 8007ee2 { frequency = HSE_VALUE; 8007edc: 4b1a ldr r3, [pc, #104] @ (8007f48 ) 8007ede: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 8007ee0: e02b b.n 8007f3a frequency = 0; 8007ee2: 2300 movs r3, #0 8007ee4: 63fb str r3, [r7, #60] @ 0x3c break; 8007ee6: e028 b.n 8007f3a } case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 8007ee8: 4b16 ldr r3, [pc, #88] @ (8007f44 ) 8007eea: 681b ldr r3, [r3, #0] 8007eec: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8007ef0: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 8007ef4: d107 bne.n 8007f06 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 8007ef6: f107 0324 add.w r3, r7, #36 @ 0x24 8007efa: 4618 mov r0, r3 8007efc: f000 fae4 bl 80084c8 frequency = pll1_clocks.PLL1_Q_Frequency; 8007f00: 6abb ldr r3, [r7, #40] @ 0x28 8007f02: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 8007f04: e019 b.n 8007f3a frequency = 0; 8007f06: 2300 movs r3, #0 8007f08: 63fb str r3, [r7, #60] @ 0x3c break; 8007f0a: e016 b.n 8007f3a } case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 8007f0c: 4b0d ldr r3, [pc, #52] @ (8007f44 ) 8007f0e: 681b ldr r3, [r3, #0] 8007f10: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8007f14: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8007f18: d107 bne.n 8007f2a { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8007f1a: f107 0318 add.w r3, r7, #24 8007f1e: 4618 mov r0, r3 8007f20: f000 f82a bl 8007f78 frequency = pll2_clocks.PLL2_Q_Frequency; 8007f24: 69fb ldr r3, [r7, #28] 8007f26: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 8007f28: e007 b.n 8007f3a frequency = 0; 8007f2a: 2300 movs r3, #0 8007f2c: 63fb str r3, [r7, #60] @ 0x3c break; 8007f2e: e004 b.n 8007f3a } default : { frequency = 0; 8007f30: 2300 movs r3, #0 8007f32: 63fb str r3, [r7, #60] @ 0x3c break; 8007f34: e001 b.n 8007f3a } } } else { frequency = 0; 8007f36: 2300 movs r3, #0 8007f38: 63fb str r3, [r7, #60] @ 0x3c } return frequency; 8007f3a: 6bfb ldr r3, [r7, #60] @ 0x3c } 8007f3c: 4618 mov r0, r3 8007f3e: 3740 adds r7, #64 @ 0x40 8007f40: 46bd mov sp, r7 8007f42: bd80 pop {r7, pc} 8007f44: 58024400 .word 0x58024400 8007f48: 007a1200 .word 0x007a1200 08007f4c : * @note Each time D3PCLK1 changes, this function must be called to update the * right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval D3PCLK1 frequency */ uint32_t HAL_RCCEx_GetD3PCLK1Freq(void) { 8007f4c: b580 push {r7, lr} 8007f4e: af00 add r7, sp, #0 #if defined(RCC_D3CFGR_D3PPRE) /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU)); 8007f50: f7fe f816 bl 8005f80 8007f54: 4602 mov r2, r0 8007f56: 4b06 ldr r3, [pc, #24] @ (8007f70 ) 8007f58: 6a1b ldr r3, [r3, #32] 8007f5a: 091b lsrs r3, r3, #4 8007f5c: f003 0307 and.w r3, r3, #7 8007f60: 4904 ldr r1, [pc, #16] @ (8007f74 ) 8007f62: 5ccb ldrb r3, [r1, r3] 8007f64: f003 031f and.w r3, r3, #31 8007f68: fa22 f303 lsr.w r3, r2, r3 #else /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU)); #endif } 8007f6c: 4618 mov r0, r3 8007f6e: bd80 pop {r7, pc} 8007f70: 58024400 .word 0x58024400 8007f74: 0800aab4 .word 0x0800aab4 08007f78 : * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL2_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks) { 8007f78: b480 push {r7} 8007f7a: b089 sub sp, #36 @ 0x24 8007f7c: af00 add r7, sp, #0 8007f7e: 6078 str r0, [r7, #4] float_t fracn2, pll2vco; /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N PLL2xCLK = PLL2_VCO / PLL2x */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 8007f80: 4ba1 ldr r3, [pc, #644] @ (8008208 ) 8007f82: 6a9b ldr r3, [r3, #40] @ 0x28 8007f84: f003 0303 and.w r3, r3, #3 8007f88: 61bb str r3, [r7, #24] pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12); 8007f8a: 4b9f ldr r3, [pc, #636] @ (8008208 ) 8007f8c: 6a9b ldr r3, [r3, #40] @ 0x28 8007f8e: 0b1b lsrs r3, r3, #12 8007f90: f003 033f and.w r3, r3, #63 @ 0x3f 8007f94: 617b str r3, [r7, #20] pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; 8007f96: 4b9c ldr r3, [pc, #624] @ (8008208 ) 8007f98: 6adb ldr r3, [r3, #44] @ 0x2c 8007f9a: 091b lsrs r3, r3, #4 8007f9c: f003 0301 and.w r3, r3, #1 8007fa0: 613b str r3, [r7, #16] fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3)); 8007fa2: 4b99 ldr r3, [pc, #612] @ (8008208 ) 8007fa4: 6bdb ldr r3, [r3, #60] @ 0x3c 8007fa6: 08db lsrs r3, r3, #3 8007fa8: f3c3 030c ubfx r3, r3, #0, #13 8007fac: 693a ldr r2, [r7, #16] 8007fae: fb02 f303 mul.w r3, r2, r3 8007fb2: ee07 3a90 vmov s15, r3 8007fb6: eef8 7a67 vcvt.f32.u32 s15, s15 8007fba: edc7 7a03 vstr s15, [r7, #12] if (pll2m != 0U) 8007fbe: 697b ldr r3, [r7, #20] 8007fc0: 2b00 cmp r3, #0 8007fc2: f000 8111 beq.w 80081e8 { switch (pllsource) 8007fc6: 69bb ldr r3, [r7, #24] 8007fc8: 2b02 cmp r3, #2 8007fca: f000 8083 beq.w 80080d4 8007fce: 69bb ldr r3, [r7, #24] 8007fd0: 2b02 cmp r3, #2 8007fd2: f200 80a1 bhi.w 8008118 8007fd6: 69bb ldr r3, [r7, #24] 8007fd8: 2b00 cmp r3, #0 8007fda: d003 beq.n 8007fe4 8007fdc: 69bb ldr r3, [r7, #24] 8007fde: 2b01 cmp r3, #1 8007fe0: d056 beq.n 8008090 8007fe2: e099 b.n 8008118 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8007fe4: 4b88 ldr r3, [pc, #544] @ (8008208 ) 8007fe6: 681b ldr r3, [r3, #0] 8007fe8: f003 0320 and.w r3, r3, #32 8007fec: 2b00 cmp r3, #0 8007fee: d02d beq.n 800804c { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8007ff0: 4b85 ldr r3, [pc, #532] @ (8008208 ) 8007ff2: 681b ldr r3, [r3, #0] 8007ff4: 08db lsrs r3, r3, #3 8007ff6: f003 0303 and.w r3, r3, #3 8007ffa: 4a84 ldr r2, [pc, #528] @ (800820c ) 8007ffc: fa22 f303 lsr.w r3, r2, r3 8008000: 60bb str r3, [r7, #8] pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 8008002: 68bb ldr r3, [r7, #8] 8008004: ee07 3a90 vmov s15, r3 8008008: eef8 6a67 vcvt.f32.u32 s13, s15 800800c: 697b ldr r3, [r7, #20] 800800e: ee07 3a90 vmov s15, r3 8008012: eef8 7a67 vcvt.f32.u32 s15, s15 8008016: ee86 7aa7 vdiv.f32 s14, s13, s15 800801a: 4b7b ldr r3, [pc, #492] @ (8008208 ) 800801c: 6b9b ldr r3, [r3, #56] @ 0x38 800801e: f3c3 0308 ubfx r3, r3, #0, #9 8008022: ee07 3a90 vmov s15, r3 8008026: eef8 6a67 vcvt.f32.u32 s13, s15 800802a: ed97 6a03 vldr s12, [r7, #12] 800802e: eddf 5a78 vldr s11, [pc, #480] @ 8008210 8008032: eec6 7a25 vdiv.f32 s15, s12, s11 8008036: ee76 7aa7 vadd.f32 s15, s13, s15 800803a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800803e: ee77 7aa6 vadd.f32 s15, s15, s13 8008042: ee67 7a27 vmul.f32 s15, s14, s15 8008046: edc7 7a07 vstr s15, [r7, #28] } else { pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); } break; 800804a: e087 b.n 800815c pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800804c: 697b ldr r3, [r7, #20] 800804e: ee07 3a90 vmov s15, r3 8008052: eef8 7a67 vcvt.f32.u32 s15, s15 8008056: eddf 6a6f vldr s13, [pc, #444] @ 8008214 800805a: ee86 7aa7 vdiv.f32 s14, s13, s15 800805e: 4b6a ldr r3, [pc, #424] @ (8008208 ) 8008060: 6b9b ldr r3, [r3, #56] @ 0x38 8008062: f3c3 0308 ubfx r3, r3, #0, #9 8008066: ee07 3a90 vmov s15, r3 800806a: eef8 6a67 vcvt.f32.u32 s13, s15 800806e: ed97 6a03 vldr s12, [r7, #12] 8008072: eddf 5a67 vldr s11, [pc, #412] @ 8008210 8008076: eec6 7a25 vdiv.f32 s15, s12, s11 800807a: ee76 7aa7 vadd.f32 s15, s13, s15 800807e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8008082: ee77 7aa6 vadd.f32 s15, s15, s13 8008086: ee67 7a27 vmul.f32 s15, s14, s15 800808a: edc7 7a07 vstr s15, [r7, #28] break; 800808e: e065 b.n 800815c case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 8008090: 697b ldr r3, [r7, #20] 8008092: ee07 3a90 vmov s15, r3 8008096: eef8 7a67 vcvt.f32.u32 s15, s15 800809a: eddf 6a5f vldr s13, [pc, #380] @ 8008218 800809e: ee86 7aa7 vdiv.f32 s14, s13, s15 80080a2: 4b59 ldr r3, [pc, #356] @ (8008208 ) 80080a4: 6b9b ldr r3, [r3, #56] @ 0x38 80080a6: f3c3 0308 ubfx r3, r3, #0, #9 80080aa: ee07 3a90 vmov s15, r3 80080ae: eef8 6a67 vcvt.f32.u32 s13, s15 80080b2: ed97 6a03 vldr s12, [r7, #12] 80080b6: eddf 5a56 vldr s11, [pc, #344] @ 8008210 80080ba: eec6 7a25 vdiv.f32 s15, s12, s11 80080be: ee76 7aa7 vadd.f32 s15, s13, s15 80080c2: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 80080c6: ee77 7aa6 vadd.f32 s15, s15, s13 80080ca: ee67 7a27 vmul.f32 s15, s14, s15 80080ce: edc7 7a07 vstr s15, [r7, #28] break; 80080d2: e043 b.n 800815c case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 80080d4: 697b ldr r3, [r7, #20] 80080d6: ee07 3a90 vmov s15, r3 80080da: eef8 7a67 vcvt.f32.u32 s15, s15 80080de: eddf 6a4f vldr s13, [pc, #316] @ 800821c 80080e2: ee86 7aa7 vdiv.f32 s14, s13, s15 80080e6: 4b48 ldr r3, [pc, #288] @ (8008208 ) 80080e8: 6b9b ldr r3, [r3, #56] @ 0x38 80080ea: f3c3 0308 ubfx r3, r3, #0, #9 80080ee: ee07 3a90 vmov s15, r3 80080f2: eef8 6a67 vcvt.f32.u32 s13, s15 80080f6: ed97 6a03 vldr s12, [r7, #12] 80080fa: eddf 5a45 vldr s11, [pc, #276] @ 8008210 80080fe: eec6 7a25 vdiv.f32 s15, s12, s11 8008102: ee76 7aa7 vadd.f32 s15, s13, s15 8008106: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800810a: ee77 7aa6 vadd.f32 s15, s15, s13 800810e: ee67 7a27 vmul.f32 s15, s14, s15 8008112: edc7 7a07 vstr s15, [r7, #28] break; 8008116: e021 b.n 800815c default: pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 8008118: 697b ldr r3, [r7, #20] 800811a: ee07 3a90 vmov s15, r3 800811e: eef8 7a67 vcvt.f32.u32 s15, s15 8008122: eddf 6a3d vldr s13, [pc, #244] @ 8008218 8008126: ee86 7aa7 vdiv.f32 s14, s13, s15 800812a: 4b37 ldr r3, [pc, #220] @ (8008208 ) 800812c: 6b9b ldr r3, [r3, #56] @ 0x38 800812e: f3c3 0308 ubfx r3, r3, #0, #9 8008132: ee07 3a90 vmov s15, r3 8008136: eef8 6a67 vcvt.f32.u32 s13, s15 800813a: ed97 6a03 vldr s12, [r7, #12] 800813e: eddf 5a34 vldr s11, [pc, #208] @ 8008210 8008142: eec6 7a25 vdiv.f32 s15, s12, s11 8008146: ee76 7aa7 vadd.f32 s15, s13, s15 800814a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800814e: ee77 7aa6 vadd.f32 s15, s15, s13 8008152: ee67 7a27 vmul.f32 s15, s14, s15 8008156: edc7 7a07 vstr s15, [r7, #28] break; 800815a: bf00 nop } PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ; 800815c: 4b2a ldr r3, [pc, #168] @ (8008208 ) 800815e: 6b9b ldr r3, [r3, #56] @ 0x38 8008160: 0a5b lsrs r3, r3, #9 8008162: f003 037f and.w r3, r3, #127 @ 0x7f 8008166: ee07 3a90 vmov s15, r3 800816a: eef8 7a67 vcvt.f32.u32 s15, s15 800816e: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 8008172: ee37 7a87 vadd.f32 s14, s15, s14 8008176: edd7 6a07 vldr s13, [r7, #28] 800817a: eec6 7a87 vdiv.f32 s15, s13, s14 800817e: eefc 7ae7 vcvt.u32.f32 s15, s15 8008182: ee17 2a90 vmov r2, s15 8008186: 687b ldr r3, [r7, #4] 8008188: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ; 800818a: 4b1f ldr r3, [pc, #124] @ (8008208 ) 800818c: 6b9b ldr r3, [r3, #56] @ 0x38 800818e: 0c1b lsrs r3, r3, #16 8008190: f003 037f and.w r3, r3, #127 @ 0x7f 8008194: ee07 3a90 vmov s15, r3 8008198: eef8 7a67 vcvt.f32.u32 s15, s15 800819c: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 80081a0: ee37 7a87 vadd.f32 s14, s15, s14 80081a4: edd7 6a07 vldr s13, [r7, #28] 80081a8: eec6 7a87 vdiv.f32 s15, s13, s14 80081ac: eefc 7ae7 vcvt.u32.f32 s15, s15 80081b0: ee17 2a90 vmov r2, s15 80081b4: 687b ldr r3, [r7, #4] 80081b6: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ; 80081b8: 4b13 ldr r3, [pc, #76] @ (8008208 ) 80081ba: 6b9b ldr r3, [r3, #56] @ 0x38 80081bc: 0e1b lsrs r3, r3, #24 80081be: f003 037f and.w r3, r3, #127 @ 0x7f 80081c2: ee07 3a90 vmov s15, r3 80081c6: eef8 7a67 vcvt.f32.u32 s15, s15 80081ca: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 80081ce: ee37 7a87 vadd.f32 s14, s15, s14 80081d2: edd7 6a07 vldr s13, [r7, #28] 80081d6: eec6 7a87 vdiv.f32 s15, s13, s14 80081da: eefc 7ae7 vcvt.u32.f32 s15, s15 80081de: ee17 2a90 vmov r2, s15 80081e2: 687b ldr r3, [r7, #4] 80081e4: 609a str r2, [r3, #8] { PLL2_Clocks->PLL2_P_Frequency = 0U; PLL2_Clocks->PLL2_Q_Frequency = 0U; PLL2_Clocks->PLL2_R_Frequency = 0U; } } 80081e6: e008 b.n 80081fa PLL2_Clocks->PLL2_P_Frequency = 0U; 80081e8: 687b ldr r3, [r7, #4] 80081ea: 2200 movs r2, #0 80081ec: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = 0U; 80081ee: 687b ldr r3, [r7, #4] 80081f0: 2200 movs r2, #0 80081f2: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = 0U; 80081f4: 687b ldr r3, [r7, #4] 80081f6: 2200 movs r2, #0 80081f8: 609a str r2, [r3, #8] } 80081fa: bf00 nop 80081fc: 3724 adds r7, #36 @ 0x24 80081fe: 46bd mov sp, r7 8008200: f85d 7b04 ldr.w r7, [sp], #4 8008204: 4770 bx lr 8008206: bf00 nop 8008208: 58024400 .word 0x58024400 800820c: 03d09000 .word 0x03d09000 8008210: 46000000 .word 0x46000000 8008214: 4c742400 .word 0x4c742400 8008218: 4a742400 .word 0x4a742400 800821c: 4af42400 .word 0x4af42400 08008220 : * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL3_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks) { 8008220: b480 push {r7} 8008222: b089 sub sp, #36 @ 0x24 8008224: af00 add r7, sp, #0 8008226: 6078 str r0, [r7, #4] float_t fracn3, pll3vco; /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N PLL3xCLK = PLL3_VCO / PLLxR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 8008228: 4ba1 ldr r3, [pc, #644] @ (80084b0 ) 800822a: 6a9b ldr r3, [r3, #40] @ 0x28 800822c: f003 0303 and.w r3, r3, #3 8008230: 61bb str r3, [r7, #24] pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ; 8008232: 4b9f ldr r3, [pc, #636] @ (80084b0 ) 8008234: 6a9b ldr r3, [r3, #40] @ 0x28 8008236: 0d1b lsrs r3, r3, #20 8008238: f003 033f and.w r3, r3, #63 @ 0x3f 800823c: 617b str r3, [r7, #20] pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; 800823e: 4b9c ldr r3, [pc, #624] @ (80084b0 ) 8008240: 6adb ldr r3, [r3, #44] @ 0x2c 8008242: 0a1b lsrs r3, r3, #8 8008244: f003 0301 and.w r3, r3, #1 8008248: 613b str r3, [r7, #16] fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3)); 800824a: 4b99 ldr r3, [pc, #612] @ (80084b0 ) 800824c: 6c5b ldr r3, [r3, #68] @ 0x44 800824e: 08db lsrs r3, r3, #3 8008250: f3c3 030c ubfx r3, r3, #0, #13 8008254: 693a ldr r2, [r7, #16] 8008256: fb02 f303 mul.w r3, r2, r3 800825a: ee07 3a90 vmov s15, r3 800825e: eef8 7a67 vcvt.f32.u32 s15, s15 8008262: edc7 7a03 vstr s15, [r7, #12] if (pll3m != 0U) 8008266: 697b ldr r3, [r7, #20] 8008268: 2b00 cmp r3, #0 800826a: f000 8111 beq.w 8008490 { switch (pllsource) 800826e: 69bb ldr r3, [r7, #24] 8008270: 2b02 cmp r3, #2 8008272: f000 8083 beq.w 800837c 8008276: 69bb ldr r3, [r7, #24] 8008278: 2b02 cmp r3, #2 800827a: f200 80a1 bhi.w 80083c0 800827e: 69bb ldr r3, [r7, #24] 8008280: 2b00 cmp r3, #0 8008282: d003 beq.n 800828c 8008284: 69bb ldr r3, [r7, #24] 8008286: 2b01 cmp r3, #1 8008288: d056 beq.n 8008338 800828a: e099 b.n 80083c0 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800828c: 4b88 ldr r3, [pc, #544] @ (80084b0 ) 800828e: 681b ldr r3, [r3, #0] 8008290: f003 0320 and.w r3, r3, #32 8008294: 2b00 cmp r3, #0 8008296: d02d beq.n 80082f4 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8008298: 4b85 ldr r3, [pc, #532] @ (80084b0 ) 800829a: 681b ldr r3, [r3, #0] 800829c: 08db lsrs r3, r3, #3 800829e: f003 0303 and.w r3, r3, #3 80082a2: 4a84 ldr r2, [pc, #528] @ (80084b4 ) 80082a4: fa22 f303 lsr.w r3, r2, r3 80082a8: 60bb str r3, [r7, #8] pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 80082aa: 68bb ldr r3, [r7, #8] 80082ac: ee07 3a90 vmov s15, r3 80082b0: eef8 6a67 vcvt.f32.u32 s13, s15 80082b4: 697b ldr r3, [r7, #20] 80082b6: ee07 3a90 vmov s15, r3 80082ba: eef8 7a67 vcvt.f32.u32 s15, s15 80082be: ee86 7aa7 vdiv.f32 s14, s13, s15 80082c2: 4b7b ldr r3, [pc, #492] @ (80084b0 ) 80082c4: 6c1b ldr r3, [r3, #64] @ 0x40 80082c6: f3c3 0308 ubfx r3, r3, #0, #9 80082ca: ee07 3a90 vmov s15, r3 80082ce: eef8 6a67 vcvt.f32.u32 s13, s15 80082d2: ed97 6a03 vldr s12, [r7, #12] 80082d6: eddf 5a78 vldr s11, [pc, #480] @ 80084b8 80082da: eec6 7a25 vdiv.f32 s15, s12, s11 80082de: ee76 7aa7 vadd.f32 s15, s13, s15 80082e2: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 80082e6: ee77 7aa6 vadd.f32 s15, s15, s13 80082ea: ee67 7a27 vmul.f32 s15, s14, s15 80082ee: edc7 7a07 vstr s15, [r7, #28] } else { pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); } break; 80082f2: e087 b.n 8008404 pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 80082f4: 697b ldr r3, [r7, #20] 80082f6: ee07 3a90 vmov s15, r3 80082fa: eef8 7a67 vcvt.f32.u32 s15, s15 80082fe: eddf 6a6f vldr s13, [pc, #444] @ 80084bc 8008302: ee86 7aa7 vdiv.f32 s14, s13, s15 8008306: 4b6a ldr r3, [pc, #424] @ (80084b0 ) 8008308: 6c1b ldr r3, [r3, #64] @ 0x40 800830a: f3c3 0308 ubfx r3, r3, #0, #9 800830e: ee07 3a90 vmov s15, r3 8008312: eef8 6a67 vcvt.f32.u32 s13, s15 8008316: ed97 6a03 vldr s12, [r7, #12] 800831a: eddf 5a67 vldr s11, [pc, #412] @ 80084b8 800831e: eec6 7a25 vdiv.f32 s15, s12, s11 8008322: ee76 7aa7 vadd.f32 s15, s13, s15 8008326: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800832a: ee77 7aa6 vadd.f32 s15, s15, s13 800832e: ee67 7a27 vmul.f32 s15, s14, s15 8008332: edc7 7a07 vstr s15, [r7, #28] break; 8008336: e065 b.n 8008404 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 8008338: 697b ldr r3, [r7, #20] 800833a: ee07 3a90 vmov s15, r3 800833e: eef8 7a67 vcvt.f32.u32 s15, s15 8008342: eddf 6a5f vldr s13, [pc, #380] @ 80084c0 8008346: ee86 7aa7 vdiv.f32 s14, s13, s15 800834a: 4b59 ldr r3, [pc, #356] @ (80084b0 ) 800834c: 6c1b ldr r3, [r3, #64] @ 0x40 800834e: f3c3 0308 ubfx r3, r3, #0, #9 8008352: ee07 3a90 vmov s15, r3 8008356: eef8 6a67 vcvt.f32.u32 s13, s15 800835a: ed97 6a03 vldr s12, [r7, #12] 800835e: eddf 5a56 vldr s11, [pc, #344] @ 80084b8 8008362: eec6 7a25 vdiv.f32 s15, s12, s11 8008366: ee76 7aa7 vadd.f32 s15, s13, s15 800836a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800836e: ee77 7aa6 vadd.f32 s15, s15, s13 8008372: ee67 7a27 vmul.f32 s15, s14, s15 8008376: edc7 7a07 vstr s15, [r7, #28] break; 800837a: e043 b.n 8008404 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800837c: 697b ldr r3, [r7, #20] 800837e: ee07 3a90 vmov s15, r3 8008382: eef8 7a67 vcvt.f32.u32 s15, s15 8008386: eddf 6a4f vldr s13, [pc, #316] @ 80084c4 800838a: ee86 7aa7 vdiv.f32 s14, s13, s15 800838e: 4b48 ldr r3, [pc, #288] @ (80084b0 ) 8008390: 6c1b ldr r3, [r3, #64] @ 0x40 8008392: f3c3 0308 ubfx r3, r3, #0, #9 8008396: ee07 3a90 vmov s15, r3 800839a: eef8 6a67 vcvt.f32.u32 s13, s15 800839e: ed97 6a03 vldr s12, [r7, #12] 80083a2: eddf 5a45 vldr s11, [pc, #276] @ 80084b8 80083a6: eec6 7a25 vdiv.f32 s15, s12, s11 80083aa: ee76 7aa7 vadd.f32 s15, s13, s15 80083ae: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 80083b2: ee77 7aa6 vadd.f32 s15, s15, s13 80083b6: ee67 7a27 vmul.f32 s15, s14, s15 80083ba: edc7 7a07 vstr s15, [r7, #28] break; 80083be: e021 b.n 8008404 default: pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 80083c0: 697b ldr r3, [r7, #20] 80083c2: ee07 3a90 vmov s15, r3 80083c6: eef8 7a67 vcvt.f32.u32 s15, s15 80083ca: eddf 6a3d vldr s13, [pc, #244] @ 80084c0 80083ce: ee86 7aa7 vdiv.f32 s14, s13, s15 80083d2: 4b37 ldr r3, [pc, #220] @ (80084b0 ) 80083d4: 6c1b ldr r3, [r3, #64] @ 0x40 80083d6: f3c3 0308 ubfx r3, r3, #0, #9 80083da: ee07 3a90 vmov s15, r3 80083de: eef8 6a67 vcvt.f32.u32 s13, s15 80083e2: ed97 6a03 vldr s12, [r7, #12] 80083e6: eddf 5a34 vldr s11, [pc, #208] @ 80084b8 80083ea: eec6 7a25 vdiv.f32 s15, s12, s11 80083ee: ee76 7aa7 vadd.f32 s15, s13, s15 80083f2: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 80083f6: ee77 7aa6 vadd.f32 s15, s15, s13 80083fa: ee67 7a27 vmul.f32 s15, s14, s15 80083fe: edc7 7a07 vstr s15, [r7, #28] break; 8008402: bf00 nop } PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ; 8008404: 4b2a ldr r3, [pc, #168] @ (80084b0 ) 8008406: 6c1b ldr r3, [r3, #64] @ 0x40 8008408: 0a5b lsrs r3, r3, #9 800840a: f003 037f and.w r3, r3, #127 @ 0x7f 800840e: ee07 3a90 vmov s15, r3 8008412: eef8 7a67 vcvt.f32.u32 s15, s15 8008416: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800841a: ee37 7a87 vadd.f32 s14, s15, s14 800841e: edd7 6a07 vldr s13, [r7, #28] 8008422: eec6 7a87 vdiv.f32 s15, s13, s14 8008426: eefc 7ae7 vcvt.u32.f32 s15, s15 800842a: ee17 2a90 vmov r2, s15 800842e: 687b ldr r3, [r7, #4] 8008430: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ; 8008432: 4b1f ldr r3, [pc, #124] @ (80084b0 ) 8008434: 6c1b ldr r3, [r3, #64] @ 0x40 8008436: 0c1b lsrs r3, r3, #16 8008438: f003 037f and.w r3, r3, #127 @ 0x7f 800843c: ee07 3a90 vmov s15, r3 8008440: eef8 7a67 vcvt.f32.u32 s15, s15 8008444: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 8008448: ee37 7a87 vadd.f32 s14, s15, s14 800844c: edd7 6a07 vldr s13, [r7, #28] 8008450: eec6 7a87 vdiv.f32 s15, s13, s14 8008454: eefc 7ae7 vcvt.u32.f32 s15, s15 8008458: ee17 2a90 vmov r2, s15 800845c: 687b ldr r3, [r7, #4] 800845e: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ; 8008460: 4b13 ldr r3, [pc, #76] @ (80084b0 ) 8008462: 6c1b ldr r3, [r3, #64] @ 0x40 8008464: 0e1b lsrs r3, r3, #24 8008466: f003 037f and.w r3, r3, #127 @ 0x7f 800846a: ee07 3a90 vmov s15, r3 800846e: eef8 7a67 vcvt.f32.u32 s15, s15 8008472: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 8008476: ee37 7a87 vadd.f32 s14, s15, s14 800847a: edd7 6a07 vldr s13, [r7, #28] 800847e: eec6 7a87 vdiv.f32 s15, s13, s14 8008482: eefc 7ae7 vcvt.u32.f32 s15, s15 8008486: ee17 2a90 vmov r2, s15 800848a: 687b ldr r3, [r7, #4] 800848c: 609a str r2, [r3, #8] PLL3_Clocks->PLL3_P_Frequency = 0U; PLL3_Clocks->PLL3_Q_Frequency = 0U; PLL3_Clocks->PLL3_R_Frequency = 0U; } } 800848e: e008 b.n 80084a2 PLL3_Clocks->PLL3_P_Frequency = 0U; 8008490: 687b ldr r3, [r7, #4] 8008492: 2200 movs r2, #0 8008494: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = 0U; 8008496: 687b ldr r3, [r7, #4] 8008498: 2200 movs r2, #0 800849a: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = 0U; 800849c: 687b ldr r3, [r7, #4] 800849e: 2200 movs r2, #0 80084a0: 609a str r2, [r3, #8] } 80084a2: bf00 nop 80084a4: 3724 adds r7, #36 @ 0x24 80084a6: 46bd mov sp, r7 80084a8: f85d 7b04 ldr.w r7, [sp], #4 80084ac: 4770 bx lr 80084ae: bf00 nop 80084b0: 58024400 .word 0x58024400 80084b4: 03d09000 .word 0x03d09000 80084b8: 46000000 .word 0x46000000 80084bc: 4c742400 .word 0x4c742400 80084c0: 4a742400 .word 0x4a742400 80084c4: 4af42400 .word 0x4af42400 080084c8 : * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL1_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks) { 80084c8: b480 push {r7} 80084ca: b089 sub sp, #36 @ 0x24 80084cc: af00 add r7, sp, #0 80084ce: 6078 str r0, [r7, #4] uint32_t pllsource, pll1m, pll1fracen, hsivalue; float_t fracn1, pll1vco; pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 80084d0: 4ba0 ldr r3, [pc, #640] @ (8008754 ) 80084d2: 6a9b ldr r3, [r3, #40] @ 0x28 80084d4: f003 0303 and.w r3, r3, #3 80084d8: 61bb str r3, [r7, #24] pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4); 80084da: 4b9e ldr r3, [pc, #632] @ (8008754 ) 80084dc: 6a9b ldr r3, [r3, #40] @ 0x28 80084de: 091b lsrs r3, r3, #4 80084e0: f003 033f and.w r3, r3, #63 @ 0x3f 80084e4: 617b str r3, [r7, #20] pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; 80084e6: 4b9b ldr r3, [pc, #620] @ (8008754 ) 80084e8: 6adb ldr r3, [r3, #44] @ 0x2c 80084ea: f003 0301 and.w r3, r3, #1 80084ee: 613b str r3, [r7, #16] fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 80084f0: 4b98 ldr r3, [pc, #608] @ (8008754 ) 80084f2: 6b5b ldr r3, [r3, #52] @ 0x34 80084f4: 08db lsrs r3, r3, #3 80084f6: f3c3 030c ubfx r3, r3, #0, #13 80084fa: 693a ldr r2, [r7, #16] 80084fc: fb02 f303 mul.w r3, r2, r3 8008500: ee07 3a90 vmov s15, r3 8008504: eef8 7a67 vcvt.f32.u32 s15, s15 8008508: edc7 7a03 vstr s15, [r7, #12] if (pll1m != 0U) 800850c: 697b ldr r3, [r7, #20] 800850e: 2b00 cmp r3, #0 8008510: f000 8111 beq.w 8008736 { switch (pllsource) 8008514: 69bb ldr r3, [r7, #24] 8008516: 2b02 cmp r3, #2 8008518: f000 8083 beq.w 8008622 800851c: 69bb ldr r3, [r7, #24] 800851e: 2b02 cmp r3, #2 8008520: f200 80a1 bhi.w 8008666 8008524: 69bb ldr r3, [r7, #24] 8008526: 2b00 cmp r3, #0 8008528: d003 beq.n 8008532 800852a: 69bb ldr r3, [r7, #24] 800852c: 2b01 cmp r3, #1 800852e: d056 beq.n 80085de 8008530: e099 b.n 8008666 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8008532: 4b88 ldr r3, [pc, #544] @ (8008754 ) 8008534: 681b ldr r3, [r3, #0] 8008536: f003 0320 and.w r3, r3, #32 800853a: 2b00 cmp r3, #0 800853c: d02d beq.n 800859a { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800853e: 4b85 ldr r3, [pc, #532] @ (8008754 ) 8008540: 681b ldr r3, [r3, #0] 8008542: 08db lsrs r3, r3, #3 8008544: f003 0303 and.w r3, r3, #3 8008548: 4a83 ldr r2, [pc, #524] @ (8008758 ) 800854a: fa22 f303 lsr.w r3, r2, r3 800854e: 60bb str r3, [r7, #8] pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8008550: 68bb ldr r3, [r7, #8] 8008552: ee07 3a90 vmov s15, r3 8008556: eef8 6a67 vcvt.f32.u32 s13, s15 800855a: 697b ldr r3, [r7, #20] 800855c: ee07 3a90 vmov s15, r3 8008560: eef8 7a67 vcvt.f32.u32 s15, s15 8008564: ee86 7aa7 vdiv.f32 s14, s13, s15 8008568: 4b7a ldr r3, [pc, #488] @ (8008754 ) 800856a: 6b1b ldr r3, [r3, #48] @ 0x30 800856c: f3c3 0308 ubfx r3, r3, #0, #9 8008570: ee07 3a90 vmov s15, r3 8008574: eef8 6a67 vcvt.f32.u32 s13, s15 8008578: ed97 6a03 vldr s12, [r7, #12] 800857c: eddf 5a77 vldr s11, [pc, #476] @ 800875c 8008580: eec6 7a25 vdiv.f32 s15, s12, s11 8008584: ee76 7aa7 vadd.f32 s15, s13, s15 8008588: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800858c: ee77 7aa6 vadd.f32 s15, s15, s13 8008590: ee67 7a27 vmul.f32 s15, s14, s15 8008594: edc7 7a07 vstr s15, [r7, #28] } else { pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); } break; 8008598: e087 b.n 80086aa pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800859a: 697b ldr r3, [r7, #20] 800859c: ee07 3a90 vmov s15, r3 80085a0: eef8 7a67 vcvt.f32.u32 s15, s15 80085a4: eddf 6a6e vldr s13, [pc, #440] @ 8008760 80085a8: ee86 7aa7 vdiv.f32 s14, s13, s15 80085ac: 4b69 ldr r3, [pc, #420] @ (8008754 ) 80085ae: 6b1b ldr r3, [r3, #48] @ 0x30 80085b0: f3c3 0308 ubfx r3, r3, #0, #9 80085b4: ee07 3a90 vmov s15, r3 80085b8: eef8 6a67 vcvt.f32.u32 s13, s15 80085bc: ed97 6a03 vldr s12, [r7, #12] 80085c0: eddf 5a66 vldr s11, [pc, #408] @ 800875c 80085c4: eec6 7a25 vdiv.f32 s15, s12, s11 80085c8: ee76 7aa7 vadd.f32 s15, s13, s15 80085cc: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 80085d0: ee77 7aa6 vadd.f32 s15, s15, s13 80085d4: ee67 7a27 vmul.f32 s15, s14, s15 80085d8: edc7 7a07 vstr s15, [r7, #28] break; 80085dc: e065 b.n 80086aa case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 80085de: 697b ldr r3, [r7, #20] 80085e0: ee07 3a90 vmov s15, r3 80085e4: eef8 7a67 vcvt.f32.u32 s15, s15 80085e8: eddf 6a5e vldr s13, [pc, #376] @ 8008764 80085ec: ee86 7aa7 vdiv.f32 s14, s13, s15 80085f0: 4b58 ldr r3, [pc, #352] @ (8008754 ) 80085f2: 6b1b ldr r3, [r3, #48] @ 0x30 80085f4: f3c3 0308 ubfx r3, r3, #0, #9 80085f8: ee07 3a90 vmov s15, r3 80085fc: eef8 6a67 vcvt.f32.u32 s13, s15 8008600: ed97 6a03 vldr s12, [r7, #12] 8008604: eddf 5a55 vldr s11, [pc, #340] @ 800875c 8008608: eec6 7a25 vdiv.f32 s15, s12, s11 800860c: ee76 7aa7 vadd.f32 s15, s13, s15 8008610: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8008614: ee77 7aa6 vadd.f32 s15, s15, s13 8008618: ee67 7a27 vmul.f32 s15, s14, s15 800861c: edc7 7a07 vstr s15, [r7, #28] break; 8008620: e043 b.n 80086aa case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8008622: 697b ldr r3, [r7, #20] 8008624: ee07 3a90 vmov s15, r3 8008628: eef8 7a67 vcvt.f32.u32 s15, s15 800862c: eddf 6a4e vldr s13, [pc, #312] @ 8008768 8008630: ee86 7aa7 vdiv.f32 s14, s13, s15 8008634: 4b47 ldr r3, [pc, #284] @ (8008754 ) 8008636: 6b1b ldr r3, [r3, #48] @ 0x30 8008638: f3c3 0308 ubfx r3, r3, #0, #9 800863c: ee07 3a90 vmov s15, r3 8008640: eef8 6a67 vcvt.f32.u32 s13, s15 8008644: ed97 6a03 vldr s12, [r7, #12] 8008648: eddf 5a44 vldr s11, [pc, #272] @ 800875c 800864c: eec6 7a25 vdiv.f32 s15, s12, s11 8008650: ee76 7aa7 vadd.f32 s15, s13, s15 8008654: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8008658: ee77 7aa6 vadd.f32 s15, s15, s13 800865c: ee67 7a27 vmul.f32 s15, s14, s15 8008660: edc7 7a07 vstr s15, [r7, #28] break; 8008664: e021 b.n 80086aa default: pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8008666: 697b ldr r3, [r7, #20] 8008668: ee07 3a90 vmov s15, r3 800866c: eef8 7a67 vcvt.f32.u32 s15, s15 8008670: eddf 6a3b vldr s13, [pc, #236] @ 8008760 8008674: ee86 7aa7 vdiv.f32 s14, s13, s15 8008678: 4b36 ldr r3, [pc, #216] @ (8008754 ) 800867a: 6b1b ldr r3, [r3, #48] @ 0x30 800867c: f3c3 0308 ubfx r3, r3, #0, #9 8008680: ee07 3a90 vmov s15, r3 8008684: eef8 6a67 vcvt.f32.u32 s13, s15 8008688: ed97 6a03 vldr s12, [r7, #12] 800868c: eddf 5a33 vldr s11, [pc, #204] @ 800875c 8008690: eec6 7a25 vdiv.f32 s15, s12, s11 8008694: ee76 7aa7 vadd.f32 s15, s13, s15 8008698: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800869c: ee77 7aa6 vadd.f32 s15, s15, s13 80086a0: ee67 7a27 vmul.f32 s15, s14, s15 80086a4: edc7 7a07 vstr s15, [r7, #28] break; 80086a8: bf00 nop } PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (float_t)1)) ; 80086aa: 4b2a ldr r3, [pc, #168] @ (8008754 ) 80086ac: 6b1b ldr r3, [r3, #48] @ 0x30 80086ae: 0a5b lsrs r3, r3, #9 80086b0: f003 037f and.w r3, r3, #127 @ 0x7f 80086b4: ee07 3a90 vmov s15, r3 80086b8: eef8 7a67 vcvt.f32.u32 s15, s15 80086bc: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 80086c0: ee37 7a87 vadd.f32 s14, s15, s14 80086c4: edd7 6a07 vldr s13, [r7, #28] 80086c8: eec6 7a87 vdiv.f32 s15, s13, s14 80086cc: eefc 7ae7 vcvt.u32.f32 s15, s15 80086d0: ee17 2a90 vmov r2, s15 80086d4: 687b ldr r3, [r7, #4] 80086d6: 601a str r2, [r3, #0] PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ; 80086d8: 4b1e ldr r3, [pc, #120] @ (8008754 ) 80086da: 6b1b ldr r3, [r3, #48] @ 0x30 80086dc: 0c1b lsrs r3, r3, #16 80086de: f003 037f and.w r3, r3, #127 @ 0x7f 80086e2: ee07 3a90 vmov s15, r3 80086e6: eef8 7a67 vcvt.f32.u32 s15, s15 80086ea: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 80086ee: ee37 7a87 vadd.f32 s14, s15, s14 80086f2: edd7 6a07 vldr s13, [r7, #28] 80086f6: eec6 7a87 vdiv.f32 s15, s13, s14 80086fa: eefc 7ae7 vcvt.u32.f32 s15, s15 80086fe: ee17 2a90 vmov r2, s15 8008702: 687b ldr r3, [r7, #4] 8008704: 605a str r2, [r3, #4] PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ; 8008706: 4b13 ldr r3, [pc, #76] @ (8008754 ) 8008708: 6b1b ldr r3, [r3, #48] @ 0x30 800870a: 0e1b lsrs r3, r3, #24 800870c: f003 037f and.w r3, r3, #127 @ 0x7f 8008710: ee07 3a90 vmov s15, r3 8008714: eef8 7a67 vcvt.f32.u32 s15, s15 8008718: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800871c: ee37 7a87 vadd.f32 s14, s15, s14 8008720: edd7 6a07 vldr s13, [r7, #28] 8008724: eec6 7a87 vdiv.f32 s15, s13, s14 8008728: eefc 7ae7 vcvt.u32.f32 s15, s15 800872c: ee17 2a90 vmov r2, s15 8008730: 687b ldr r3, [r7, #4] 8008732: 609a str r2, [r3, #8] PLL1_Clocks->PLL1_P_Frequency = 0U; PLL1_Clocks->PLL1_Q_Frequency = 0U; PLL1_Clocks->PLL1_R_Frequency = 0U; } } 8008734: e008 b.n 8008748 PLL1_Clocks->PLL1_P_Frequency = 0U; 8008736: 687b ldr r3, [r7, #4] 8008738: 2200 movs r2, #0 800873a: 601a str r2, [r3, #0] PLL1_Clocks->PLL1_Q_Frequency = 0U; 800873c: 687b ldr r3, [r7, #4] 800873e: 2200 movs r2, #0 8008740: 605a str r2, [r3, #4] PLL1_Clocks->PLL1_R_Frequency = 0U; 8008742: 687b ldr r3, [r7, #4] 8008744: 2200 movs r2, #0 8008746: 609a str r2, [r3, #8] } 8008748: bf00 nop 800874a: 3724 adds r7, #36 @ 0x24 800874c: 46bd mov sp, r7 800874e: f85d 7b04 ldr.w r7, [sp], #4 8008752: 4770 bx lr 8008754: 58024400 .word 0x58024400 8008758: 03d09000 .word 0x03d09000 800875c: 46000000 .word 0x46000000 8008760: 4c742400 .word 0x4c742400 8008764: 4a742400 .word 0x4a742400 8008768: 4af42400 .word 0x4af42400 0800876c : * @note PLL2 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2, uint32_t Divider) { 800876c: b580 push {r7, lr} 800876e: b084 sub sp, #16 8008770: af00 add r7, sp, #0 8008772: 6078 str r0, [r7, #4] 8008774: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 8008776: 2300 movs r3, #0 8008778: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE)); assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN)); /* Check that PLL2 OSC clock source is already set */ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800877a: 4b53 ldr r3, [pc, #332] @ (80088c8 ) 800877c: 6a9b ldr r3, [r3, #40] @ 0x28 800877e: f003 0303 and.w r3, r3, #3 8008782: 2b03 cmp r3, #3 8008784: d101 bne.n 800878a { return HAL_ERROR; 8008786: 2301 movs r3, #1 8008788: e099 b.n 80088be else { /* Disable PLL2. */ __HAL_RCC_PLL2_DISABLE(); 800878a: 4b4f ldr r3, [pc, #316] @ (80088c8 ) 800878c: 681b ldr r3, [r3, #0] 800878e: 4a4e ldr r2, [pc, #312] @ (80088c8 ) 8008790: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8008794: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8008796: f7f8 ffa5 bl 80016e4 800879a: 60b8 str r0, [r7, #8] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 800879c: e008 b.n 80087b0 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800879e: f7f8 ffa1 bl 80016e4 80087a2: 4602 mov r2, r0 80087a4: 68bb ldr r3, [r7, #8] 80087a6: 1ad3 subs r3, r2, r3 80087a8: 2b02 cmp r3, #2 80087aa: d901 bls.n 80087b0 { return HAL_TIMEOUT; 80087ac: 2303 movs r3, #3 80087ae: e086 b.n 80088be while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 80087b0: 4b45 ldr r3, [pc, #276] @ (80088c8 ) 80087b2: 681b ldr r3, [r3, #0] 80087b4: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 80087b8: 2b00 cmp r3, #0 80087ba: d1f0 bne.n 800879e } } /* Configure PLL2 multiplication and division factors. */ __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, 80087bc: 4b42 ldr r3, [pc, #264] @ (80088c8 ) 80087be: 6a9b ldr r3, [r3, #40] @ 0x28 80087c0: f423 327c bic.w r2, r3, #258048 @ 0x3f000 80087c4: 687b ldr r3, [r7, #4] 80087c6: 681b ldr r3, [r3, #0] 80087c8: 031b lsls r3, r3, #12 80087ca: 493f ldr r1, [pc, #252] @ (80088c8 ) 80087cc: 4313 orrs r3, r2 80087ce: 628b str r3, [r1, #40] @ 0x28 80087d0: 687b ldr r3, [r7, #4] 80087d2: 685b ldr r3, [r3, #4] 80087d4: 3b01 subs r3, #1 80087d6: f3c3 0208 ubfx r2, r3, #0, #9 80087da: 687b ldr r3, [r7, #4] 80087dc: 689b ldr r3, [r3, #8] 80087de: 3b01 subs r3, #1 80087e0: 025b lsls r3, r3, #9 80087e2: b29b uxth r3, r3 80087e4: 431a orrs r2, r3 80087e6: 687b ldr r3, [r7, #4] 80087e8: 68db ldr r3, [r3, #12] 80087ea: 3b01 subs r3, #1 80087ec: 041b lsls r3, r3, #16 80087ee: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 80087f2: 431a orrs r2, r3 80087f4: 687b ldr r3, [r7, #4] 80087f6: 691b ldr r3, [r3, #16] 80087f8: 3b01 subs r3, #1 80087fa: 061b lsls r3, r3, #24 80087fc: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 8008800: 4931 ldr r1, [pc, #196] @ (80088c8 ) 8008802: 4313 orrs r3, r2 8008804: 638b str r3, [r1, #56] @ 0x38 pll2->PLL2P, pll2->PLL2Q, pll2->PLL2R); /* Select PLL2 input reference frequency range: VCI */ __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; 8008806: 4b30 ldr r3, [pc, #192] @ (80088c8 ) 8008808: 6adb ldr r3, [r3, #44] @ 0x2c 800880a: f023 02c0 bic.w r2, r3, #192 @ 0xc0 800880e: 687b ldr r3, [r7, #4] 8008810: 695b ldr r3, [r3, #20] 8008812: 492d ldr r1, [pc, #180] @ (80088c8 ) 8008814: 4313 orrs r3, r2 8008816: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL2 output frequency range : VCO */ __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; 8008818: 4b2b ldr r3, [pc, #172] @ (80088c8 ) 800881a: 6adb ldr r3, [r3, #44] @ 0x2c 800881c: f023 0220 bic.w r2, r3, #32 8008820: 687b ldr r3, [r7, #4] 8008822: 699b ldr r3, [r3, #24] 8008824: 4928 ldr r1, [pc, #160] @ (80088c8 ) 8008826: 4313 orrs r3, r2 8008828: 62cb str r3, [r1, #44] @ 0x2c /* Disable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_DISABLE(); 800882a: 4b27 ldr r3, [pc, #156] @ (80088c8 ) 800882c: 6adb ldr r3, [r3, #44] @ 0x2c 800882e: 4a26 ldr r2, [pc, #152] @ (80088c8 ) 8008830: f023 0310 bic.w r3, r3, #16 8008834: 62d3 str r3, [r2, #44] @ 0x2c /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); 8008836: 4b24 ldr r3, [pc, #144] @ (80088c8 ) 8008838: 6bda ldr r2, [r3, #60] @ 0x3c 800883a: 4b24 ldr r3, [pc, #144] @ (80088cc ) 800883c: 4013 ands r3, r2 800883e: 687a ldr r2, [r7, #4] 8008840: 69d2 ldr r2, [r2, #28] 8008842: 00d2 lsls r2, r2, #3 8008844: 4920 ldr r1, [pc, #128] @ (80088c8 ) 8008846: 4313 orrs r3, r2 8008848: 63cb str r3, [r1, #60] @ 0x3c /* Enable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_ENABLE(); 800884a: 4b1f ldr r3, [pc, #124] @ (80088c8 ) 800884c: 6adb ldr r3, [r3, #44] @ 0x2c 800884e: 4a1e ldr r2, [pc, #120] @ (80088c8 ) 8008850: f043 0310 orr.w r3, r3, #16 8008854: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the PLL2 clock output */ if (Divider == DIVIDER_P_UPDATE) 8008856: 683b ldr r3, [r7, #0] 8008858: 2b00 cmp r3, #0 800885a: d106 bne.n 800886a { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); 800885c: 4b1a ldr r3, [pc, #104] @ (80088c8 ) 800885e: 6adb ldr r3, [r3, #44] @ 0x2c 8008860: 4a19 ldr r2, [pc, #100] @ (80088c8 ) 8008862: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8008866: 62d3 str r3, [r2, #44] @ 0x2c 8008868: e00f b.n 800888a } else if (Divider == DIVIDER_Q_UPDATE) 800886a: 683b ldr r3, [r7, #0] 800886c: 2b01 cmp r3, #1 800886e: d106 bne.n 800887e { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); 8008870: 4b15 ldr r3, [pc, #84] @ (80088c8 ) 8008872: 6adb ldr r3, [r3, #44] @ 0x2c 8008874: 4a14 ldr r2, [pc, #80] @ (80088c8 ) 8008876: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800887a: 62d3 str r3, [r2, #44] @ 0x2c 800887c: e005 b.n 800888a } else { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR); 800887e: 4b12 ldr r3, [pc, #72] @ (80088c8 ) 8008880: 6adb ldr r3, [r3, #44] @ 0x2c 8008882: 4a11 ldr r2, [pc, #68] @ (80088c8 ) 8008884: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8008888: 62d3 str r3, [r2, #44] @ 0x2c } /* Enable PLL2. */ __HAL_RCC_PLL2_ENABLE(); 800888a: 4b0f ldr r3, [pc, #60] @ (80088c8 ) 800888c: 681b ldr r3, [r3, #0] 800888e: 4a0e ldr r2, [pc, #56] @ (80088c8 ) 8008890: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 8008894: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8008896: f7f8 ff25 bl 80016e4 800889a: 60b8 str r0, [r7, #8] /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 800889c: e008 b.n 80088b0 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800889e: f7f8 ff21 bl 80016e4 80088a2: 4602 mov r2, r0 80088a4: 68bb ldr r3, [r7, #8] 80088a6: 1ad3 subs r3, r2, r3 80088a8: 2b02 cmp r3, #2 80088aa: d901 bls.n 80088b0 { return HAL_TIMEOUT; 80088ac: 2303 movs r3, #3 80088ae: e006 b.n 80088be while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 80088b0: 4b05 ldr r3, [pc, #20] @ (80088c8 ) 80088b2: 681b ldr r3, [r3, #0] 80088b4: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 80088b8: 2b00 cmp r3, #0 80088ba: d0f0 beq.n 800889e } } return status; 80088bc: 7bfb ldrb r3, [r7, #15] } 80088be: 4618 mov r0, r3 80088c0: 3710 adds r7, #16 80088c2: 46bd mov sp, r7 80088c4: bd80 pop {r7, pc} 80088c6: bf00 nop 80088c8: 58024400 .word 0x58024400 80088cc: ffff0007 .word 0xffff0007 080088d0 : * @note PLL3 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3, uint32_t Divider) { 80088d0: b580 push {r7, lr} 80088d2: b084 sub sp, #16 80088d4: af00 add r7, sp, #0 80088d6: 6078 str r0, [r7, #4] 80088d8: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 80088da: 2300 movs r3, #0 80088dc: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE)); assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN)); /* Check that PLL3 OSC clock source is already set */ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 80088de: 4b53 ldr r3, [pc, #332] @ (8008a2c ) 80088e0: 6a9b ldr r3, [r3, #40] @ 0x28 80088e2: f003 0303 and.w r3, r3, #3 80088e6: 2b03 cmp r3, #3 80088e8: d101 bne.n 80088ee { return HAL_ERROR; 80088ea: 2301 movs r3, #1 80088ec: e099 b.n 8008a22 else { /* Disable PLL3. */ __HAL_RCC_PLL3_DISABLE(); 80088ee: 4b4f ldr r3, [pc, #316] @ (8008a2c ) 80088f0: 681b ldr r3, [r3, #0] 80088f2: 4a4e ldr r2, [pc, #312] @ (8008a2c ) 80088f4: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80088f8: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80088fa: f7f8 fef3 bl 80016e4 80088fe: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 8008900: e008 b.n 8008914 { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 8008902: f7f8 feef bl 80016e4 8008906: 4602 mov r2, r0 8008908: 68bb ldr r3, [r7, #8] 800890a: 1ad3 subs r3, r2, r3 800890c: 2b02 cmp r3, #2 800890e: d901 bls.n 8008914 { return HAL_TIMEOUT; 8008910: 2303 movs r3, #3 8008912: e086 b.n 8008a22 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 8008914: 4b45 ldr r3, [pc, #276] @ (8008a2c ) 8008916: 681b ldr r3, [r3, #0] 8008918: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800891c: 2b00 cmp r3, #0 800891e: d1f0 bne.n 8008902 } } /* Configure the PLL3 multiplication and division factors. */ __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, 8008920: 4b42 ldr r3, [pc, #264] @ (8008a2c ) 8008922: 6a9b ldr r3, [r3, #40] @ 0x28 8008924: f023 727c bic.w r2, r3, #66060288 @ 0x3f00000 8008928: 687b ldr r3, [r7, #4] 800892a: 681b ldr r3, [r3, #0] 800892c: 051b lsls r3, r3, #20 800892e: 493f ldr r1, [pc, #252] @ (8008a2c ) 8008930: 4313 orrs r3, r2 8008932: 628b str r3, [r1, #40] @ 0x28 8008934: 687b ldr r3, [r7, #4] 8008936: 685b ldr r3, [r3, #4] 8008938: 3b01 subs r3, #1 800893a: f3c3 0208 ubfx r2, r3, #0, #9 800893e: 687b ldr r3, [r7, #4] 8008940: 689b ldr r3, [r3, #8] 8008942: 3b01 subs r3, #1 8008944: 025b lsls r3, r3, #9 8008946: b29b uxth r3, r3 8008948: 431a orrs r2, r3 800894a: 687b ldr r3, [r7, #4] 800894c: 68db ldr r3, [r3, #12] 800894e: 3b01 subs r3, #1 8008950: 041b lsls r3, r3, #16 8008952: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 8008956: 431a orrs r2, r3 8008958: 687b ldr r3, [r7, #4] 800895a: 691b ldr r3, [r3, #16] 800895c: 3b01 subs r3, #1 800895e: 061b lsls r3, r3, #24 8008960: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 8008964: 4931 ldr r1, [pc, #196] @ (8008a2c ) 8008966: 4313 orrs r3, r2 8008968: 640b str r3, [r1, #64] @ 0x40 pll3->PLL3P, pll3->PLL3Q, pll3->PLL3R); /* Select PLL3 input reference frequency range: VCI */ __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; 800896a: 4b30 ldr r3, [pc, #192] @ (8008a2c ) 800896c: 6adb ldr r3, [r3, #44] @ 0x2c 800896e: f423 6240 bic.w r2, r3, #3072 @ 0xc00 8008972: 687b ldr r3, [r7, #4] 8008974: 695b ldr r3, [r3, #20] 8008976: 492d ldr r1, [pc, #180] @ (8008a2c ) 8008978: 4313 orrs r3, r2 800897a: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL3 output frequency range : VCO */ __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; 800897c: 4b2b ldr r3, [pc, #172] @ (8008a2c ) 800897e: 6adb ldr r3, [r3, #44] @ 0x2c 8008980: f423 7200 bic.w r2, r3, #512 @ 0x200 8008984: 687b ldr r3, [r7, #4] 8008986: 699b ldr r3, [r3, #24] 8008988: 4928 ldr r1, [pc, #160] @ (8008a2c ) 800898a: 4313 orrs r3, r2 800898c: 62cb str r3, [r1, #44] @ 0x2c /* Disable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_DISABLE(); 800898e: 4b27 ldr r3, [pc, #156] @ (8008a2c ) 8008990: 6adb ldr r3, [r3, #44] @ 0x2c 8008992: 4a26 ldr r2, [pc, #152] @ (8008a2c ) 8008994: f423 7380 bic.w r3, r3, #256 @ 0x100 8008998: 62d3 str r3, [r2, #44] @ 0x2c /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); 800899a: 4b24 ldr r3, [pc, #144] @ (8008a2c ) 800899c: 6c5a ldr r2, [r3, #68] @ 0x44 800899e: 4b24 ldr r3, [pc, #144] @ (8008a30 ) 80089a0: 4013 ands r3, r2 80089a2: 687a ldr r2, [r7, #4] 80089a4: 69d2 ldr r2, [r2, #28] 80089a6: 00d2 lsls r2, r2, #3 80089a8: 4920 ldr r1, [pc, #128] @ (8008a2c ) 80089aa: 4313 orrs r3, r2 80089ac: 644b str r3, [r1, #68] @ 0x44 /* Enable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_ENABLE(); 80089ae: 4b1f ldr r3, [pc, #124] @ (8008a2c ) 80089b0: 6adb ldr r3, [r3, #44] @ 0x2c 80089b2: 4a1e ldr r2, [pc, #120] @ (8008a2c ) 80089b4: f443 7380 orr.w r3, r3, #256 @ 0x100 80089b8: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the PLL3 clock output */ if (Divider == DIVIDER_P_UPDATE) 80089ba: 683b ldr r3, [r7, #0] 80089bc: 2b00 cmp r3, #0 80089be: d106 bne.n 80089ce { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); 80089c0: 4b1a ldr r3, [pc, #104] @ (8008a2c ) 80089c2: 6adb ldr r3, [r3, #44] @ 0x2c 80089c4: 4a19 ldr r2, [pc, #100] @ (8008a2c ) 80089c6: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 80089ca: 62d3 str r3, [r2, #44] @ 0x2c 80089cc: e00f b.n 80089ee } else if (Divider == DIVIDER_Q_UPDATE) 80089ce: 683b ldr r3, [r7, #0] 80089d0: 2b01 cmp r3, #1 80089d2: d106 bne.n 80089e2 { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); 80089d4: 4b15 ldr r3, [pc, #84] @ (8008a2c ) 80089d6: 6adb ldr r3, [r3, #44] @ 0x2c 80089d8: 4a14 ldr r2, [pc, #80] @ (8008a2c ) 80089da: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 80089de: 62d3 str r3, [r2, #44] @ 0x2c 80089e0: e005 b.n 80089ee } else { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR); 80089e2: 4b12 ldr r3, [pc, #72] @ (8008a2c ) 80089e4: 6adb ldr r3, [r3, #44] @ 0x2c 80089e6: 4a11 ldr r2, [pc, #68] @ (8008a2c ) 80089e8: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 80089ec: 62d3 str r3, [r2, #44] @ 0x2c } /* Enable PLL3. */ __HAL_RCC_PLL3_ENABLE(); 80089ee: 4b0f ldr r3, [pc, #60] @ (8008a2c ) 80089f0: 681b ldr r3, [r3, #0] 80089f2: 4a0e ldr r2, [pc, #56] @ (8008a2c ) 80089f4: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80089f8: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80089fa: f7f8 fe73 bl 80016e4 80089fe: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 8008a00: e008 b.n 8008a14 { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 8008a02: f7f8 fe6f bl 80016e4 8008a06: 4602 mov r2, r0 8008a08: 68bb ldr r3, [r7, #8] 8008a0a: 1ad3 subs r3, r2, r3 8008a0c: 2b02 cmp r3, #2 8008a0e: d901 bls.n 8008a14 { return HAL_TIMEOUT; 8008a10: 2303 movs r3, #3 8008a12: e006 b.n 8008a22 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 8008a14: 4b05 ldr r3, [pc, #20] @ (8008a2c ) 8008a16: 681b ldr r3, [r3, #0] 8008a18: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8008a1c: 2b00 cmp r3, #0 8008a1e: d0f0 beq.n 8008a02 } } return status; 8008a20: 7bfb ldrb r3, [r7, #15] } 8008a22: 4618 mov r0, r3 8008a24: 3710 adds r7, #16 8008a26: 46bd mov sp, r7 8008a28: bd80 pop {r7, pc} 8008a2a: bf00 nop 8008a2c: 58024400 .word 0x58024400 8008a30: ffff0007 .word 0xffff0007 08008a34 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8008a34: b580 push {r7, lr} 8008a36: b082 sub sp, #8 8008a38: af00 add r7, sp, #0 8008a3a: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8008a3c: 687b ldr r3, [r7, #4] 8008a3e: 2b00 cmp r3, #0 8008a40: d101 bne.n 8008a46 { return HAL_ERROR; 8008a42: 2301 movs r3, #1 8008a44: e049 b.n 8008ada assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8008a46: 687b ldr r3, [r7, #4] 8008a48: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8008a4c: b2db uxtb r3, r3 8008a4e: 2b00 cmp r3, #0 8008a50: d106 bne.n 8008a60 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8008a52: 687b ldr r3, [r7, #4] 8008a54: 2200 movs r2, #0 8008a56: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8008a5a: 6878 ldr r0, [r7, #4] 8008a5c: f7f8 fc7a bl 8001354 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8008a60: 687b ldr r3, [r7, #4] 8008a62: 2202 movs r2, #2 8008a64: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8008a68: 687b ldr r3, [r7, #4] 8008a6a: 681a ldr r2, [r3, #0] 8008a6c: 687b ldr r3, [r7, #4] 8008a6e: 3304 adds r3, #4 8008a70: 4619 mov r1, r3 8008a72: 4610 mov r0, r2 8008a74: f000 f96e bl 8008d54 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8008a78: 687b ldr r3, [r7, #4] 8008a7a: 2201 movs r2, #1 8008a7c: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8008a80: 687b ldr r3, [r7, #4] 8008a82: 2201 movs r2, #1 8008a84: f883 203e strb.w r2, [r3, #62] @ 0x3e 8008a88: 687b ldr r3, [r7, #4] 8008a8a: 2201 movs r2, #1 8008a8c: f883 203f strb.w r2, [r3, #63] @ 0x3f 8008a90: 687b ldr r3, [r7, #4] 8008a92: 2201 movs r2, #1 8008a94: f883 2040 strb.w r2, [r3, #64] @ 0x40 8008a98: 687b ldr r3, [r7, #4] 8008a9a: 2201 movs r2, #1 8008a9c: f883 2041 strb.w r2, [r3, #65] @ 0x41 8008aa0: 687b ldr r3, [r7, #4] 8008aa2: 2201 movs r2, #1 8008aa4: f883 2042 strb.w r2, [r3, #66] @ 0x42 8008aa8: 687b ldr r3, [r7, #4] 8008aaa: 2201 movs r2, #1 8008aac: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8008ab0: 687b ldr r3, [r7, #4] 8008ab2: 2201 movs r2, #1 8008ab4: f883 2044 strb.w r2, [r3, #68] @ 0x44 8008ab8: 687b ldr r3, [r7, #4] 8008aba: 2201 movs r2, #1 8008abc: f883 2045 strb.w r2, [r3, #69] @ 0x45 8008ac0: 687b ldr r3, [r7, #4] 8008ac2: 2201 movs r2, #1 8008ac4: f883 2046 strb.w r2, [r3, #70] @ 0x46 8008ac8: 687b ldr r3, [r7, #4] 8008aca: 2201 movs r2, #1 8008acc: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8008ad0: 687b ldr r3, [r7, #4] 8008ad2: 2201 movs r2, #1 8008ad4: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8008ad8: 2300 movs r3, #0 } 8008ada: 4618 mov r0, r3 8008adc: 3708 adds r7, #8 8008ade: 46bd mov sp, r7 8008ae0: bd80 pop {r7, pc} 08008ae2 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 8008ae2: b580 push {r7, lr} 8008ae4: b084 sub sp, #16 8008ae6: af00 add r7, sp, #0 8008ae8: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 8008aea: 687b ldr r3, [r7, #4] 8008aec: 681b ldr r3, [r3, #0] 8008aee: 68db ldr r3, [r3, #12] 8008af0: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 8008af2: 687b ldr r3, [r7, #4] 8008af4: 681b ldr r3, [r3, #0] 8008af6: 691b ldr r3, [r3, #16] 8008af8: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 8008afa: 68bb ldr r3, [r7, #8] 8008afc: f003 0302 and.w r3, r3, #2 8008b00: 2b00 cmp r3, #0 8008b02: d020 beq.n 8008b46 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 8008b04: 68fb ldr r3, [r7, #12] 8008b06: f003 0302 and.w r3, r3, #2 8008b0a: 2b00 cmp r3, #0 8008b0c: d01b beq.n 8008b46 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 8008b0e: 687b ldr r3, [r7, #4] 8008b10: 681b ldr r3, [r3, #0] 8008b12: f06f 0202 mvn.w r2, #2 8008b16: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 8008b18: 687b ldr r3, [r7, #4] 8008b1a: 2201 movs r2, #1 8008b1c: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 8008b1e: 687b ldr r3, [r7, #4] 8008b20: 681b ldr r3, [r3, #0] 8008b22: 699b ldr r3, [r3, #24] 8008b24: f003 0303 and.w r3, r3, #3 8008b28: 2b00 cmp r3, #0 8008b2a: d003 beq.n 8008b34 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8008b2c: 6878 ldr r0, [r7, #4] 8008b2e: f000 f8f3 bl 8008d18 8008b32: e005 b.n 8008b40 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8008b34: 6878 ldr r0, [r7, #4] 8008b36: f000 f8e5 bl 8008d04 HAL_TIM_PWM_PulseFinishedCallback(htim); 8008b3a: 6878 ldr r0, [r7, #4] 8008b3c: f000 f8f6 bl 8008d2c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8008b40: 687b ldr r3, [r7, #4] 8008b42: 2200 movs r2, #0 8008b44: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 8008b46: 68bb ldr r3, [r7, #8] 8008b48: f003 0304 and.w r3, r3, #4 8008b4c: 2b00 cmp r3, #0 8008b4e: d020 beq.n 8008b92 { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 8008b50: 68fb ldr r3, [r7, #12] 8008b52: f003 0304 and.w r3, r3, #4 8008b56: 2b00 cmp r3, #0 8008b58: d01b beq.n 8008b92 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 8008b5a: 687b ldr r3, [r7, #4] 8008b5c: 681b ldr r3, [r3, #0] 8008b5e: f06f 0204 mvn.w r2, #4 8008b62: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 8008b64: 687b ldr r3, [r7, #4] 8008b66: 2202 movs r2, #2 8008b68: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 8008b6a: 687b ldr r3, [r7, #4] 8008b6c: 681b ldr r3, [r3, #0] 8008b6e: 699b ldr r3, [r3, #24] 8008b70: f403 7340 and.w r3, r3, #768 @ 0x300 8008b74: 2b00 cmp r3, #0 8008b76: d003 beq.n 8008b80 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8008b78: 6878 ldr r0, [r7, #4] 8008b7a: f000 f8cd bl 8008d18 8008b7e: e005 b.n 8008b8c { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8008b80: 6878 ldr r0, [r7, #4] 8008b82: f000 f8bf bl 8008d04 HAL_TIM_PWM_PulseFinishedCallback(htim); 8008b86: 6878 ldr r0, [r7, #4] 8008b88: f000 f8d0 bl 8008d2c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8008b8c: 687b ldr r3, [r7, #4] 8008b8e: 2200 movs r2, #0 8008b90: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 8008b92: 68bb ldr r3, [r7, #8] 8008b94: f003 0308 and.w r3, r3, #8 8008b98: 2b00 cmp r3, #0 8008b9a: d020 beq.n 8008bde { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 8008b9c: 68fb ldr r3, [r7, #12] 8008b9e: f003 0308 and.w r3, r3, #8 8008ba2: 2b00 cmp r3, #0 8008ba4: d01b beq.n 8008bde { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 8008ba6: 687b ldr r3, [r7, #4] 8008ba8: 681b ldr r3, [r3, #0] 8008baa: f06f 0208 mvn.w r2, #8 8008bae: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 8008bb0: 687b ldr r3, [r7, #4] 8008bb2: 2204 movs r2, #4 8008bb4: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 8008bb6: 687b ldr r3, [r7, #4] 8008bb8: 681b ldr r3, [r3, #0] 8008bba: 69db ldr r3, [r3, #28] 8008bbc: f003 0303 and.w r3, r3, #3 8008bc0: 2b00 cmp r3, #0 8008bc2: d003 beq.n 8008bcc { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8008bc4: 6878 ldr r0, [r7, #4] 8008bc6: f000 f8a7 bl 8008d18 8008bca: e005 b.n 8008bd8 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8008bcc: 6878 ldr r0, [r7, #4] 8008bce: f000 f899 bl 8008d04 HAL_TIM_PWM_PulseFinishedCallback(htim); 8008bd2: 6878 ldr r0, [r7, #4] 8008bd4: f000 f8aa bl 8008d2c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8008bd8: 687b ldr r3, [r7, #4] 8008bda: 2200 movs r2, #0 8008bdc: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 8008bde: 68bb ldr r3, [r7, #8] 8008be0: f003 0310 and.w r3, r3, #16 8008be4: 2b00 cmp r3, #0 8008be6: d020 beq.n 8008c2a { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 8008be8: 68fb ldr r3, [r7, #12] 8008bea: f003 0310 and.w r3, r3, #16 8008bee: 2b00 cmp r3, #0 8008bf0: d01b beq.n 8008c2a { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 8008bf2: 687b ldr r3, [r7, #4] 8008bf4: 681b ldr r3, [r3, #0] 8008bf6: f06f 0210 mvn.w r2, #16 8008bfa: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 8008bfc: 687b ldr r3, [r7, #4] 8008bfe: 2208 movs r2, #8 8008c00: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 8008c02: 687b ldr r3, [r7, #4] 8008c04: 681b ldr r3, [r3, #0] 8008c06: 69db ldr r3, [r3, #28] 8008c08: f403 7340 and.w r3, r3, #768 @ 0x300 8008c0c: 2b00 cmp r3, #0 8008c0e: d003 beq.n 8008c18 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8008c10: 6878 ldr r0, [r7, #4] 8008c12: f000 f881 bl 8008d18 8008c16: e005 b.n 8008c24 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8008c18: 6878 ldr r0, [r7, #4] 8008c1a: f000 f873 bl 8008d04 HAL_TIM_PWM_PulseFinishedCallback(htim); 8008c1e: 6878 ldr r0, [r7, #4] 8008c20: f000 f884 bl 8008d2c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8008c24: 687b ldr r3, [r7, #4] 8008c26: 2200 movs r2, #0 8008c28: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 8008c2a: 68bb ldr r3, [r7, #8] 8008c2c: f003 0301 and.w r3, r3, #1 8008c30: 2b00 cmp r3, #0 8008c32: d00c beq.n 8008c4e { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 8008c34: 68fb ldr r3, [r7, #12] 8008c36: f003 0301 and.w r3, r3, #1 8008c3a: 2b00 cmp r3, #0 8008c3c: d007 beq.n 8008c4e { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 8008c3e: 687b ldr r3, [r7, #4] 8008c40: 681b ldr r3, [r3, #0] 8008c42: f06f 0201 mvn.w r2, #1 8008c46: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 8008c48: 6878 ldr r0, [r7, #4] 8008c4a: f000 f851 bl 8008cf0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 8008c4e: 68bb ldr r3, [r7, #8] 8008c50: f003 0380 and.w r3, r3, #128 @ 0x80 8008c54: 2b00 cmp r3, #0 8008c56: d104 bne.n 8008c62 ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) 8008c58: 68bb ldr r3, [r7, #8] 8008c5a: f403 5300 and.w r3, r3, #8192 @ 0x2000 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 8008c5e: 2b00 cmp r3, #0 8008c60: d00c beq.n 8008c7c { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 8008c62: 68fb ldr r3, [r7, #12] 8008c64: f003 0380 and.w r3, r3, #128 @ 0x80 8008c68: 2b00 cmp r3, #0 8008c6a: d007 beq.n 8008c7c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); 8008c6c: 687b ldr r3, [r7, #4] 8008c6e: 681b ldr r3, [r3, #0] 8008c70: f46f 5202 mvn.w r2, #8320 @ 0x2080 8008c74: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 8008c76: 6878 ldr r0, [r7, #4] 8008c78: f000 f9a4 bl 8008fc4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) 8008c7c: 68bb ldr r3, [r7, #8] 8008c7e: f403 7380 and.w r3, r3, #256 @ 0x100 8008c82: 2b00 cmp r3, #0 8008c84: d00c beq.n 8008ca0 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 8008c86: 68fb ldr r3, [r7, #12] 8008c88: f003 0380 and.w r3, r3, #128 @ 0x80 8008c8c: 2b00 cmp r3, #0 8008c8e: d007 beq.n 8008ca0 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); 8008c90: 687b ldr r3, [r7, #4] 8008c92: 681b ldr r3, [r3, #0] 8008c94: f46f 7280 mvn.w r2, #256 @ 0x100 8008c98: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); 8008c9a: 6878 ldr r0, [r7, #4] 8008c9c: f000 f99c bl 8008fd8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 8008ca0: 68bb ldr r3, [r7, #8] 8008ca2: f003 0340 and.w r3, r3, #64 @ 0x40 8008ca6: 2b00 cmp r3, #0 8008ca8: d00c beq.n 8008cc4 { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 8008caa: 68fb ldr r3, [r7, #12] 8008cac: f003 0340 and.w r3, r3, #64 @ 0x40 8008cb0: 2b00 cmp r3, #0 8008cb2: d007 beq.n 8008cc4 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 8008cb4: 687b ldr r3, [r7, #4] 8008cb6: 681b ldr r3, [r3, #0] 8008cb8: f06f 0240 mvn.w r2, #64 @ 0x40 8008cbc: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 8008cbe: 6878 ldr r0, [r7, #4] 8008cc0: f000 f83e bl 8008d40 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 8008cc4: 68bb ldr r3, [r7, #8] 8008cc6: f003 0320 and.w r3, r3, #32 8008cca: 2b00 cmp r3, #0 8008ccc: d00c beq.n 8008ce8 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 8008cce: 68fb ldr r3, [r7, #12] 8008cd0: f003 0320 and.w r3, r3, #32 8008cd4: 2b00 cmp r3, #0 8008cd6: d007 beq.n 8008ce8 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 8008cd8: 687b ldr r3, [r7, #4] 8008cda: 681b ldr r3, [r3, #0] 8008cdc: f06f 0220 mvn.w r2, #32 8008ce0: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 8008ce2: 6878 ldr r0, [r7, #4] 8008ce4: f000 f964 bl 8008fb0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 8008ce8: bf00 nop 8008cea: 3710 adds r7, #16 8008cec: 46bd mov sp, r7 8008cee: bd80 pop {r7, pc} 08008cf0 : * @brief Period elapsed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8008cf0: b480 push {r7} 8008cf2: b083 sub sp, #12 8008cf4: af00 add r7, sp, #0 8008cf6: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ } 8008cf8: bf00 nop 8008cfa: 370c adds r7, #12 8008cfc: 46bd mov sp, r7 8008cfe: f85d 7b04 ldr.w r7, [sp], #4 8008d02: 4770 bx lr 08008d04 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 8008d04: b480 push {r7} 8008d06: b083 sub sp, #12 8008d08: af00 add r7, sp, #0 8008d0a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 8008d0c: bf00 nop 8008d0e: 370c adds r7, #12 8008d10: 46bd mov sp, r7 8008d12: f85d 7b04 ldr.w r7, [sp], #4 8008d16: 4770 bx lr 08008d18 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 8008d18: b480 push {r7} 8008d1a: b083 sub sp, #12 8008d1c: af00 add r7, sp, #0 8008d1e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 8008d20: bf00 nop 8008d22: 370c adds r7, #12 8008d24: 46bd mov sp, r7 8008d26: f85d 7b04 ldr.w r7, [sp], #4 8008d2a: 4770 bx lr 08008d2c : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 8008d2c: b480 push {r7} 8008d2e: b083 sub sp, #12 8008d30: af00 add r7, sp, #0 8008d32: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 8008d34: bf00 nop 8008d36: 370c adds r7, #12 8008d38: 46bd mov sp, r7 8008d3a: f85d 7b04 ldr.w r7, [sp], #4 8008d3e: 4770 bx lr 08008d40 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 8008d40: b480 push {r7} 8008d42: b083 sub sp, #12 8008d44: af00 add r7, sp, #0 8008d46: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 8008d48: bf00 nop 8008d4a: 370c adds r7, #12 8008d4c: 46bd mov sp, r7 8008d4e: f85d 7b04 ldr.w r7, [sp], #4 8008d52: 4770 bx lr 08008d54 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 8008d54: b480 push {r7} 8008d56: b085 sub sp, #20 8008d58: af00 add r7, sp, #0 8008d5a: 6078 str r0, [r7, #4] 8008d5c: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 8008d5e: 687b ldr r3, [r7, #4] 8008d60: 681b ldr r3, [r3, #0] 8008d62: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8008d64: 687b ldr r3, [r7, #4] 8008d66: 4a43 ldr r2, [pc, #268] @ (8008e74 ) 8008d68: 4293 cmp r3, r2 8008d6a: d013 beq.n 8008d94 8008d6c: 687b ldr r3, [r7, #4] 8008d6e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8008d72: d00f beq.n 8008d94 8008d74: 687b ldr r3, [r7, #4] 8008d76: 4a40 ldr r2, [pc, #256] @ (8008e78 ) 8008d78: 4293 cmp r3, r2 8008d7a: d00b beq.n 8008d94 8008d7c: 687b ldr r3, [r7, #4] 8008d7e: 4a3f ldr r2, [pc, #252] @ (8008e7c ) 8008d80: 4293 cmp r3, r2 8008d82: d007 beq.n 8008d94 8008d84: 687b ldr r3, [r7, #4] 8008d86: 4a3e ldr r2, [pc, #248] @ (8008e80 ) 8008d88: 4293 cmp r3, r2 8008d8a: d003 beq.n 8008d94 8008d8c: 687b ldr r3, [r7, #4] 8008d8e: 4a3d ldr r2, [pc, #244] @ (8008e84 ) 8008d90: 4293 cmp r3, r2 8008d92: d108 bne.n 8008da6 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8008d94: 68fb ldr r3, [r7, #12] 8008d96: f023 0370 bic.w r3, r3, #112 @ 0x70 8008d9a: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8008d9c: 683b ldr r3, [r7, #0] 8008d9e: 685b ldr r3, [r3, #4] 8008da0: 68fa ldr r2, [r7, #12] 8008da2: 4313 orrs r3, r2 8008da4: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8008da6: 687b ldr r3, [r7, #4] 8008da8: 4a32 ldr r2, [pc, #200] @ (8008e74 ) 8008daa: 4293 cmp r3, r2 8008dac: d01f beq.n 8008dee 8008dae: 687b ldr r3, [r7, #4] 8008db0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8008db4: d01b beq.n 8008dee 8008db6: 687b ldr r3, [r7, #4] 8008db8: 4a2f ldr r2, [pc, #188] @ (8008e78 ) 8008dba: 4293 cmp r3, r2 8008dbc: d017 beq.n 8008dee 8008dbe: 687b ldr r3, [r7, #4] 8008dc0: 4a2e ldr r2, [pc, #184] @ (8008e7c ) 8008dc2: 4293 cmp r3, r2 8008dc4: d013 beq.n 8008dee 8008dc6: 687b ldr r3, [r7, #4] 8008dc8: 4a2d ldr r2, [pc, #180] @ (8008e80 ) 8008dca: 4293 cmp r3, r2 8008dcc: d00f beq.n 8008dee 8008dce: 687b ldr r3, [r7, #4] 8008dd0: 4a2c ldr r2, [pc, #176] @ (8008e84 ) 8008dd2: 4293 cmp r3, r2 8008dd4: d00b beq.n 8008dee 8008dd6: 687b ldr r3, [r7, #4] 8008dd8: 4a2b ldr r2, [pc, #172] @ (8008e88 ) 8008dda: 4293 cmp r3, r2 8008ddc: d007 beq.n 8008dee 8008dde: 687b ldr r3, [r7, #4] 8008de0: 4a2a ldr r2, [pc, #168] @ (8008e8c ) 8008de2: 4293 cmp r3, r2 8008de4: d003 beq.n 8008dee 8008de6: 687b ldr r3, [r7, #4] 8008de8: 4a29 ldr r2, [pc, #164] @ (8008e90 ) 8008dea: 4293 cmp r3, r2 8008dec: d108 bne.n 8008e00 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 8008dee: 68fb ldr r3, [r7, #12] 8008df0: f423 7340 bic.w r3, r3, #768 @ 0x300 8008df4: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8008df6: 683b ldr r3, [r7, #0] 8008df8: 68db ldr r3, [r3, #12] 8008dfa: 68fa ldr r2, [r7, #12] 8008dfc: 4313 orrs r3, r2 8008dfe: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8008e00: 68fb ldr r3, [r7, #12] 8008e02: f023 0280 bic.w r2, r3, #128 @ 0x80 8008e06: 683b ldr r3, [r7, #0] 8008e08: 695b ldr r3, [r3, #20] 8008e0a: 4313 orrs r3, r2 8008e0c: 60fb str r3, [r7, #12] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8008e0e: 683b ldr r3, [r7, #0] 8008e10: 689a ldr r2, [r3, #8] 8008e12: 687b ldr r3, [r7, #4] 8008e14: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8008e16: 683b ldr r3, [r7, #0] 8008e18: 681a ldr r2, [r3, #0] 8008e1a: 687b ldr r3, [r7, #4] 8008e1c: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8008e1e: 687b ldr r3, [r7, #4] 8008e20: 4a14 ldr r2, [pc, #80] @ (8008e74 ) 8008e22: 4293 cmp r3, r2 8008e24: d00f beq.n 8008e46 8008e26: 687b ldr r3, [r7, #4] 8008e28: 4a16 ldr r2, [pc, #88] @ (8008e84 ) 8008e2a: 4293 cmp r3, r2 8008e2c: d00b beq.n 8008e46 8008e2e: 687b ldr r3, [r7, #4] 8008e30: 4a15 ldr r2, [pc, #84] @ (8008e88 ) 8008e32: 4293 cmp r3, r2 8008e34: d007 beq.n 8008e46 8008e36: 687b ldr r3, [r7, #4] 8008e38: 4a14 ldr r2, [pc, #80] @ (8008e8c ) 8008e3a: 4293 cmp r3, r2 8008e3c: d003 beq.n 8008e46 8008e3e: 687b ldr r3, [r7, #4] 8008e40: 4a13 ldr r2, [pc, #76] @ (8008e90 ) 8008e42: 4293 cmp r3, r2 8008e44: d103 bne.n 8008e4e { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8008e46: 683b ldr r3, [r7, #0] 8008e48: 691a ldr r2, [r3, #16] 8008e4a: 687b ldr r3, [r7, #4] 8008e4c: 631a str r2, [r3, #48] @ 0x30 } /* Disable Update Event (UEV) with Update Generation (UG) by changing Update Request Source (URS) to avoid Update flag (UIF) */ SET_BIT(TIMx->CR1, TIM_CR1_URS); 8008e4e: 687b ldr r3, [r7, #4] 8008e50: 681b ldr r3, [r3, #0] 8008e52: f043 0204 orr.w r2, r3, #4 8008e56: 687b ldr r3, [r7, #4] 8008e58: 601a str r2, [r3, #0] /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8008e5a: 687b ldr r3, [r7, #4] 8008e5c: 2201 movs r2, #1 8008e5e: 615a str r2, [r3, #20] TIMx->CR1 = tmpcr1; 8008e60: 687b ldr r3, [r7, #4] 8008e62: 68fa ldr r2, [r7, #12] 8008e64: 601a str r2, [r3, #0] } 8008e66: bf00 nop 8008e68: 3714 adds r7, #20 8008e6a: 46bd mov sp, r7 8008e6c: f85d 7b04 ldr.w r7, [sp], #4 8008e70: 4770 bx lr 8008e72: bf00 nop 8008e74: 40010000 .word 0x40010000 8008e78: 40000400 .word 0x40000400 8008e7c: 40000800 .word 0x40000800 8008e80: 40000c00 .word 0x40000c00 8008e84: 40010400 .word 0x40010400 8008e88: 40014000 .word 0x40014000 8008e8c: 40014400 .word 0x40014400 8008e90: 40014800 .word 0x40014800 08008e94 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8008e94: b480 push {r7} 8008e96: b085 sub sp, #20 8008e98: af00 add r7, sp, #0 8008e9a: 6078 str r0, [r7, #4] 8008e9c: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8008e9e: 687b ldr r3, [r7, #4] 8008ea0: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8008ea4: 2b01 cmp r3, #1 8008ea6: d101 bne.n 8008eac 8008ea8: 2302 movs r3, #2 8008eaa: e06d b.n 8008f88 8008eac: 687b ldr r3, [r7, #4] 8008eae: 2201 movs r2, #1 8008eb0: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8008eb4: 687b ldr r3, [r7, #4] 8008eb6: 2202 movs r2, #2 8008eb8: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8008ebc: 687b ldr r3, [r7, #4] 8008ebe: 681b ldr r3, [r3, #0] 8008ec0: 685b ldr r3, [r3, #4] 8008ec2: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8008ec4: 687b ldr r3, [r7, #4] 8008ec6: 681b ldr r3, [r3, #0] 8008ec8: 689b ldr r3, [r3, #8] 8008eca: 60bb str r3, [r7, #8] /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 8008ecc: 687b ldr r3, [r7, #4] 8008ece: 681b ldr r3, [r3, #0] 8008ed0: 4a30 ldr r2, [pc, #192] @ (8008f94 ) 8008ed2: 4293 cmp r3, r2 8008ed4: d004 beq.n 8008ee0 8008ed6: 687b ldr r3, [r7, #4] 8008ed8: 681b ldr r3, [r3, #0] 8008eda: 4a2f ldr r2, [pc, #188] @ (8008f98 ) 8008edc: 4293 cmp r3, r2 8008ede: d108 bne.n 8008ef2 { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; 8008ee0: 68fb ldr r3, [r7, #12] 8008ee2: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000 8008ee6: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 8008ee8: 683b ldr r3, [r7, #0] 8008eea: 685b ldr r3, [r3, #4] 8008eec: 68fa ldr r2, [r7, #12] 8008eee: 4313 orrs r3, r2 8008ef0: 60fb str r3, [r7, #12] } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8008ef2: 68fb ldr r3, [r7, #12] 8008ef4: f023 0370 bic.w r3, r3, #112 @ 0x70 8008ef8: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8008efa: 683b ldr r3, [r7, #0] 8008efc: 681b ldr r3, [r3, #0] 8008efe: 68fa ldr r2, [r7, #12] 8008f00: 4313 orrs r3, r2 8008f02: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8008f04: 687b ldr r3, [r7, #4] 8008f06: 681b ldr r3, [r3, #0] 8008f08: 68fa ldr r2, [r7, #12] 8008f0a: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8008f0c: 687b ldr r3, [r7, #4] 8008f0e: 681b ldr r3, [r3, #0] 8008f10: 4a20 ldr r2, [pc, #128] @ (8008f94 ) 8008f12: 4293 cmp r3, r2 8008f14: d022 beq.n 8008f5c 8008f16: 687b ldr r3, [r7, #4] 8008f18: 681b ldr r3, [r3, #0] 8008f1a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8008f1e: d01d beq.n 8008f5c 8008f20: 687b ldr r3, [r7, #4] 8008f22: 681b ldr r3, [r3, #0] 8008f24: 4a1d ldr r2, [pc, #116] @ (8008f9c ) 8008f26: 4293 cmp r3, r2 8008f28: d018 beq.n 8008f5c 8008f2a: 687b ldr r3, [r7, #4] 8008f2c: 681b ldr r3, [r3, #0] 8008f2e: 4a1c ldr r2, [pc, #112] @ (8008fa0 ) 8008f30: 4293 cmp r3, r2 8008f32: d013 beq.n 8008f5c 8008f34: 687b ldr r3, [r7, #4] 8008f36: 681b ldr r3, [r3, #0] 8008f38: 4a1a ldr r2, [pc, #104] @ (8008fa4 ) 8008f3a: 4293 cmp r3, r2 8008f3c: d00e beq.n 8008f5c 8008f3e: 687b ldr r3, [r7, #4] 8008f40: 681b ldr r3, [r3, #0] 8008f42: 4a15 ldr r2, [pc, #84] @ (8008f98 ) 8008f44: 4293 cmp r3, r2 8008f46: d009 beq.n 8008f5c 8008f48: 687b ldr r3, [r7, #4] 8008f4a: 681b ldr r3, [r3, #0] 8008f4c: 4a16 ldr r2, [pc, #88] @ (8008fa8 ) 8008f4e: 4293 cmp r3, r2 8008f50: d004 beq.n 8008f5c 8008f52: 687b ldr r3, [r7, #4] 8008f54: 681b ldr r3, [r3, #0] 8008f56: 4a15 ldr r2, [pc, #84] @ (8008fac ) 8008f58: 4293 cmp r3, r2 8008f5a: d10c bne.n 8008f76 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8008f5c: 68bb ldr r3, [r7, #8] 8008f5e: f023 0380 bic.w r3, r3, #128 @ 0x80 8008f62: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8008f64: 683b ldr r3, [r7, #0] 8008f66: 689b ldr r3, [r3, #8] 8008f68: 68ba ldr r2, [r7, #8] 8008f6a: 4313 orrs r3, r2 8008f6c: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8008f6e: 687b ldr r3, [r7, #4] 8008f70: 681b ldr r3, [r3, #0] 8008f72: 68ba ldr r2, [r7, #8] 8008f74: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8008f76: 687b ldr r3, [r7, #4] 8008f78: 2201 movs r2, #1 8008f7a: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8008f7e: 687b ldr r3, [r7, #4] 8008f80: 2200 movs r2, #0 8008f82: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 8008f86: 2300 movs r3, #0 } 8008f88: 4618 mov r0, r3 8008f8a: 3714 adds r7, #20 8008f8c: 46bd mov sp, r7 8008f8e: f85d 7b04 ldr.w r7, [sp], #4 8008f92: 4770 bx lr 8008f94: 40010000 .word 0x40010000 8008f98: 40010400 .word 0x40010400 8008f9c: 40000400 .word 0x40000400 8008fa0: 40000800 .word 0x40000800 8008fa4: 40000c00 .word 0x40000c00 8008fa8: 40001800 .word 0x40001800 8008fac: 40014000 .word 0x40014000 08008fb0 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8008fb0: b480 push {r7} 8008fb2: b083 sub sp, #12 8008fb4: af00 add r7, sp, #0 8008fb6: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8008fb8: bf00 nop 8008fba: 370c adds r7, #12 8008fbc: 46bd mov sp, r7 8008fbe: f85d 7b04 ldr.w r7, [sp], #4 8008fc2: 4770 bx lr 08008fc4 : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8008fc4: b480 push {r7} 8008fc6: b083 sub sp, #12 8008fc8: af00 add r7, sp, #0 8008fca: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 8008fcc: bf00 nop 8008fce: 370c adds r7, #12 8008fd0: 46bd mov sp, r7 8008fd2: f85d 7b04 ldr.w r7, [sp], #4 8008fd6: 4770 bx lr 08008fd8 : * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { 8008fd8: b480 push {r7} 8008fda: b083 sub sp, #12 8008fdc: af00 add r7, sp, #0 8008fde: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } 8008fe0: bf00 nop 8008fe2: 370c adds r7, #12 8008fe4: 46bd mov sp, r7 8008fe6: f85d 7b04 ldr.w r7, [sp], #4 8008fea: 4770 bx lr 08008fec : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8008fec: b580 push {r7, lr} 8008fee: b082 sub sp, #8 8008ff0: af00 add r7, sp, #0 8008ff2: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8008ff4: 687b ldr r3, [r7, #4] 8008ff6: 2b00 cmp r3, #0 8008ff8: d101 bne.n 8008ffe { return HAL_ERROR; 8008ffa: 2301 movs r3, #1 8008ffc: e042 b.n 8009084 { /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } if (huart->gState == HAL_UART_STATE_RESET) 8008ffe: 687b ldr r3, [r7, #4] 8009000: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8009004: 2b00 cmp r3, #0 8009006: d106 bne.n 8009016 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8009008: 687b ldr r3, [r7, #4] 800900a: 2200 movs r2, #0 800900c: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8009010: 6878 ldr r0, [r7, #4] 8009012: f7f8 fa33 bl 800147c #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8009016: 687b ldr r3, [r7, #4] 8009018: 2224 movs r2, #36 @ 0x24 800901a: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UART_DISABLE(huart); 800901e: 687b ldr r3, [r7, #4] 8009020: 681b ldr r3, [r3, #0] 8009022: 681a ldr r2, [r3, #0] 8009024: 687b ldr r3, [r7, #4] 8009026: 681b ldr r3, [r3, #0] 8009028: f022 0201 bic.w r2, r2, #1 800902c: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 800902e: 687b ldr r3, [r7, #4] 8009030: 6a9b ldr r3, [r3, #40] @ 0x28 8009032: 2b00 cmp r3, #0 8009034: d002 beq.n 800903c { UART_AdvFeatureConfig(huart); 8009036: 6878 ldr r0, [r7, #4] 8009038: f001 f986 bl 800a348 } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) 800903c: 6878 ldr r0, [r7, #4] 800903e: f000 fc1b bl 8009878 8009042: 4603 mov r3, r0 8009044: 2b01 cmp r3, #1 8009046: d101 bne.n 800904c { return HAL_ERROR; 8009048: 2301 movs r3, #1 800904a: e01b b.n 8009084 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 800904c: 687b ldr r3, [r7, #4] 800904e: 681b ldr r3, [r3, #0] 8009050: 685a ldr r2, [r3, #4] 8009052: 687b ldr r3, [r7, #4] 8009054: 681b ldr r3, [r3, #0] 8009056: f422 4290 bic.w r2, r2, #18432 @ 0x4800 800905a: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 800905c: 687b ldr r3, [r7, #4] 800905e: 681b ldr r3, [r3, #0] 8009060: 689a ldr r2, [r3, #8] 8009062: 687b ldr r3, [r7, #4] 8009064: 681b ldr r3, [r3, #0] 8009066: f022 022a bic.w r2, r2, #42 @ 0x2a 800906a: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); 800906c: 687b ldr r3, [r7, #4] 800906e: 681b ldr r3, [r3, #0] 8009070: 681a ldr r2, [r3, #0] 8009072: 687b ldr r3, [r7, #4] 8009074: 681b ldr r3, [r3, #0] 8009076: f042 0201 orr.w r2, r2, #1 800907a: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); 800907c: 6878 ldr r0, [r7, #4] 800907e: f001 fa05 bl 800a48c 8009082: 4603 mov r3, r0 } 8009084: 4618 mov r0, r3 8009086: 3708 adds r7, #8 8009088: 46bd mov sp, r7 800908a: bd80 pop {r7, pc} 0800908c : * @brief Handle UART interrupt request. * @param huart UART handle. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 800908c: b580 push {r7, lr} 800908e: b0ba sub sp, #232 @ 0xe8 8009090: af00 add r7, sp, #0 8009092: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->ISR); 8009094: 687b ldr r3, [r7, #4] 8009096: 681b ldr r3, [r3, #0] 8009098: 69db ldr r3, [r3, #28] 800909a: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 800909e: 687b ldr r3, [r7, #4] 80090a0: 681b ldr r3, [r3, #0] 80090a2: 681b ldr r3, [r3, #0] 80090a4: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 80090a8: 687b ldr r3, [r7, #4] 80090aa: 681b ldr r3, [r3, #0] 80090ac: 689b ldr r3, [r3, #8] 80090ae: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags; uint32_t errorcode; /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); 80090b2: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4 80090b6: f640 030f movw r3, #2063 @ 0x80f 80090ba: 4013 ands r3, r2 80090bc: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == 0U) 80090c0: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 80090c4: 2b00 cmp r3, #0 80090c6: d11b bne.n 8009100 { /* UART in mode Receiver ---------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 80090c8: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80090cc: f003 0320 and.w r3, r3, #32 80090d0: 2b00 cmp r3, #0 80090d2: d015 beq.n 8009100 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 80090d4: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80090d8: f003 0320 and.w r3, r3, #32 80090dc: 2b00 cmp r3, #0 80090de: d105 bne.n 80090ec || ((cr3its & USART_CR3_RXFTIE) != 0U))) 80090e0: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80090e4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80090e8: 2b00 cmp r3, #0 80090ea: d009 beq.n 8009100 { if (huart->RxISR != NULL) 80090ec: 687b ldr r3, [r7, #4] 80090ee: 6f5b ldr r3, [r3, #116] @ 0x74 80090f0: 2b00 cmp r3, #0 80090f2: f000 8393 beq.w 800981c { huart->RxISR(huart); 80090f6: 687b ldr r3, [r7, #4] 80090f8: 6f5b ldr r3, [r3, #116] @ 0x74 80090fa: 6878 ldr r0, [r7, #4] 80090fc: 4798 blx r3 } return; 80090fe: e38d b.n 800981c } } /* If some errors occur */ if ((errorflags != 0U) 8009100: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8009104: 2b00 cmp r3, #0 8009106: f000 8123 beq.w 8009350 && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) 800910a: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 800910e: 4b8d ldr r3, [pc, #564] @ (8009344 ) 8009110: 4013 ands r3, r2 8009112: 2b00 cmp r3, #0 8009114: d106 bne.n 8009124 || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) 8009116: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0 800911a: 4b8b ldr r3, [pc, #556] @ (8009348 ) 800911c: 4013 ands r3, r2 800911e: 2b00 cmp r3, #0 8009120: f000 8116 beq.w 8009350 { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8009124: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8009128: f003 0301 and.w r3, r3, #1 800912c: 2b00 cmp r3, #0 800912e: d011 beq.n 8009154 8009130: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8009134: f403 7380 and.w r3, r3, #256 @ 0x100 8009138: 2b00 cmp r3, #0 800913a: d00b beq.n 8009154 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 800913c: 687b ldr r3, [r7, #4] 800913e: 681b ldr r3, [r3, #0] 8009140: 2201 movs r2, #1 8009142: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8009144: 687b ldr r3, [r7, #4] 8009146: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800914a: f043 0201 orr.w r2, r3, #1 800914e: 687b ldr r3, [r7, #4] 8009150: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8009154: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8009158: f003 0302 and.w r3, r3, #2 800915c: 2b00 cmp r3, #0 800915e: d011 beq.n 8009184 8009160: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8009164: f003 0301 and.w r3, r3, #1 8009168: 2b00 cmp r3, #0 800916a: d00b beq.n 8009184 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 800916c: 687b ldr r3, [r7, #4] 800916e: 681b ldr r3, [r3, #0] 8009170: 2202 movs r2, #2 8009172: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8009174: 687b ldr r3, [r7, #4] 8009176: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800917a: f043 0204 orr.w r2, r3, #4 800917e: 687b ldr r3, [r7, #4] 8009180: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8009184: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8009188: f003 0304 and.w r3, r3, #4 800918c: 2b00 cmp r3, #0 800918e: d011 beq.n 80091b4 8009190: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8009194: f003 0301 and.w r3, r3, #1 8009198: 2b00 cmp r3, #0 800919a: d00b beq.n 80091b4 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 800919c: 687b ldr r3, [r7, #4] 800919e: 681b ldr r3, [r3, #0] 80091a0: 2204 movs r2, #4 80091a2: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 80091a4: 687b ldr r3, [r7, #4] 80091a6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80091aa: f043 0202 orr.w r2, r3, #2 80091ae: 687b ldr r3, [r7, #4] 80091b0: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Over-Run interrupt occurred -----------------------------------------*/ if (((isrflags & USART_ISR_ORE) != 0U) 80091b4: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80091b8: f003 0308 and.w r3, r3, #8 80091bc: 2b00 cmp r3, #0 80091be: d017 beq.n 80091f0 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 80091c0: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80091c4: f003 0320 and.w r3, r3, #32 80091c8: 2b00 cmp r3, #0 80091ca: d105 bne.n 80091d8 ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) 80091cc: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 80091d0: 4b5c ldr r3, [pc, #368] @ (8009344 ) 80091d2: 4013 ands r3, r2 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 80091d4: 2b00 cmp r3, #0 80091d6: d00b beq.n 80091f0 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 80091d8: 687b ldr r3, [r7, #4] 80091da: 681b ldr r3, [r3, #0] 80091dc: 2208 movs r2, #8 80091de: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_ORE; 80091e0: 687b ldr r3, [r7, #4] 80091e2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80091e6: f043 0208 orr.w r2, r3, #8 80091ea: 687b ldr r3, [r7, #4] 80091ec: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Receiver Timeout interrupt occurred ---------------------------------*/ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) 80091f0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80091f4: f403 6300 and.w r3, r3, #2048 @ 0x800 80091f8: 2b00 cmp r3, #0 80091fa: d012 beq.n 8009222 80091fc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8009200: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8009204: 2b00 cmp r3, #0 8009206: d00c beq.n 8009222 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8009208: 687b ldr r3, [r7, #4] 800920a: 681b ldr r3, [r3, #0] 800920c: f44f 6200 mov.w r2, #2048 @ 0x800 8009210: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_RTO; 8009212: 687b ldr r3, [r7, #4] 8009214: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8009218: f043 0220 orr.w r2, r3, #32 800921c: 687b ldr r3, [r7, #4] 800921e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8009222: 687b ldr r3, [r7, #4] 8009224: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8009228: 2b00 cmp r3, #0 800922a: f000 82f9 beq.w 8009820 { /* UART in mode Receiver --------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 800922e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8009232: f003 0320 and.w r3, r3, #32 8009236: 2b00 cmp r3, #0 8009238: d013 beq.n 8009262 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 800923a: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 800923e: f003 0320 and.w r3, r3, #32 8009242: 2b00 cmp r3, #0 8009244: d105 bne.n 8009252 || ((cr3its & USART_CR3_RXFTIE) != 0U))) 8009246: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 800924a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800924e: 2b00 cmp r3, #0 8009250: d007 beq.n 8009262 { if (huart->RxISR != NULL) 8009252: 687b ldr r3, [r7, #4] 8009254: 6f5b ldr r3, [r3, #116] @ 0x74 8009256: 2b00 cmp r3, #0 8009258: d003 beq.n 8009262 { huart->RxISR(huart); 800925a: 687b ldr r3, [r7, #4] 800925c: 6f5b ldr r3, [r3, #116] @ 0x74 800925e: 6878 ldr r0, [r7, #4] 8009260: 4798 blx r3 /* If Error is to be considered as blocking : - Receiver Timeout error in Reception - Overrun error in Reception - any error occurs in DMA mode reception */ errorcode = huart->ErrorCode; 8009262: 687b ldr r3, [r7, #4] 8009264: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8009268: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 800926c: 687b ldr r3, [r7, #4] 800926e: 681b ldr r3, [r3, #0] 8009270: 689b ldr r3, [r3, #8] 8009272: f003 0340 and.w r3, r3, #64 @ 0x40 8009276: 2b40 cmp r3, #64 @ 0x40 8009278: d005 beq.n 8009286 ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) 800927a: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 800927e: f003 0328 and.w r3, r3, #40 @ 0x28 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 8009282: 2b00 cmp r3, #0 8009284: d054 beq.n 8009330 { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8009286: 6878 ldr r0, [r7, #4] 8009288: f001 fa18 bl 800a6bc /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 800928c: 687b ldr r3, [r7, #4] 800928e: 681b ldr r3, [r3, #0] 8009290: 689b ldr r3, [r3, #8] 8009292: f003 0340 and.w r3, r3, #64 @ 0x40 8009296: 2b40 cmp r3, #64 @ 0x40 8009298: d146 bne.n 8009328 { /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 800929a: 687b ldr r3, [r7, #4] 800929c: 681b ldr r3, [r3, #0] 800929e: 3308 adds r3, #8 80092a0: f8c7 309c str.w r3, [r7, #156] @ 0x9c */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80092a4: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 80092a8: e853 3f00 ldrex r3, [r3] 80092ac: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 80092b0: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 80092b4: f023 0340 bic.w r3, r3, #64 @ 0x40 80092b8: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 80092bc: 687b ldr r3, [r7, #4] 80092be: 681b ldr r3, [r3, #0] 80092c0: 3308 adds r3, #8 80092c2: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 80092c6: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 80092ca: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80092ce: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 80092d2: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 80092d6: e841 2300 strex r3, r2, [r1] 80092da: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 80092de: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 80092e2: 2b00 cmp r3, #0 80092e4: d1d9 bne.n 800929a /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 80092e6: 687b ldr r3, [r7, #4] 80092e8: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80092ec: 2b00 cmp r3, #0 80092ee: d017 beq.n 8009320 { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 80092f0: 687b ldr r3, [r7, #4] 80092f2: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80092f6: 4a15 ldr r2, [pc, #84] @ (800934c ) 80092f8: 651a str r2, [r3, #80] @ 0x50 /* Abort DMA RX */ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 80092fa: 687b ldr r3, [r7, #4] 80092fc: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8009300: 4618 mov r0, r3 8009302: f7fa f903 bl 800350c 8009306: 4603 mov r3, r0 8009308: 2b00 cmp r3, #0 800930a: d019 beq.n 8009340 { /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 800930c: 687b ldr r3, [r7, #4] 800930e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8009312: 6d1b ldr r3, [r3, #80] @ 0x50 8009314: 687a ldr r2, [r7, #4] 8009316: f8d2 2080 ldr.w r2, [r2, #128] @ 0x80 800931a: 4610 mov r0, r2 800931c: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 800931e: e00f b.n 8009340 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8009320: 6878 ldr r0, [r7, #4] 8009322: f000 fa93 bl 800984c if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8009326: e00b b.n 8009340 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8009328: 6878 ldr r0, [r7, #4] 800932a: f000 fa8f bl 800984c if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 800932e: e007 b.n 8009340 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8009330: 6878 ldr r0, [r7, #4] 8009332: f000 fa8b bl 800984c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8009336: 687b ldr r3, [r7, #4] 8009338: 2200 movs r2, #0 800933a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } return; 800933e: e26f b.n 8009820 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8009340: bf00 nop return; 8009342: e26d b.n 8009820 8009344: 10000001 .word 0x10000001 8009348: 04000120 .word 0x04000120 800934c: 0800a789 .word 0x0800a789 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8009350: 687b ldr r3, [r7, #4] 8009352: 6edb ldr r3, [r3, #108] @ 0x6c 8009354: 2b01 cmp r3, #1 8009356: f040 8203 bne.w 8009760 && ((isrflags & USART_ISR_IDLE) != 0U) 800935a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800935e: f003 0310 and.w r3, r3, #16 8009362: 2b00 cmp r3, #0 8009364: f000 81fc beq.w 8009760 && ((cr1its & USART_ISR_IDLE) != 0U)) 8009368: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 800936c: f003 0310 and.w r3, r3, #16 8009370: 2b00 cmp r3, #0 8009372: f000 81f5 beq.w 8009760 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8009376: 687b ldr r3, [r7, #4] 8009378: 681b ldr r3, [r3, #0] 800937a: 2210 movs r2, #16 800937c: 621a str r2, [r3, #32] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 800937e: 687b ldr r3, [r7, #4] 8009380: 681b ldr r3, [r3, #0] 8009382: 689b ldr r3, [r3, #8] 8009384: f003 0340 and.w r3, r3, #64 @ 0x40 8009388: 2b40 cmp r3, #64 @ 0x40 800938a: f040 816d bne.w 8009668 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 800938e: 687b ldr r3, [r7, #4] 8009390: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8009394: 681b ldr r3, [r3, #0] 8009396: 4aa4 ldr r2, [pc, #656] @ (8009628 ) 8009398: 4293 cmp r3, r2 800939a: d068 beq.n 800946e 800939c: 687b ldr r3, [r7, #4] 800939e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80093a2: 681b ldr r3, [r3, #0] 80093a4: 4aa1 ldr r2, [pc, #644] @ (800962c ) 80093a6: 4293 cmp r3, r2 80093a8: d061 beq.n 800946e 80093aa: 687b ldr r3, [r7, #4] 80093ac: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80093b0: 681b ldr r3, [r3, #0] 80093b2: 4a9f ldr r2, [pc, #636] @ (8009630 ) 80093b4: 4293 cmp r3, r2 80093b6: d05a beq.n 800946e 80093b8: 687b ldr r3, [r7, #4] 80093ba: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80093be: 681b ldr r3, [r3, #0] 80093c0: 4a9c ldr r2, [pc, #624] @ (8009634 ) 80093c2: 4293 cmp r3, r2 80093c4: d053 beq.n 800946e 80093c6: 687b ldr r3, [r7, #4] 80093c8: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80093cc: 681b ldr r3, [r3, #0] 80093ce: 4a9a ldr r2, [pc, #616] @ (8009638 ) 80093d0: 4293 cmp r3, r2 80093d2: d04c beq.n 800946e 80093d4: 687b ldr r3, [r7, #4] 80093d6: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80093da: 681b ldr r3, [r3, #0] 80093dc: 4a97 ldr r2, [pc, #604] @ (800963c ) 80093de: 4293 cmp r3, r2 80093e0: d045 beq.n 800946e 80093e2: 687b ldr r3, [r7, #4] 80093e4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80093e8: 681b ldr r3, [r3, #0] 80093ea: 4a95 ldr r2, [pc, #596] @ (8009640 ) 80093ec: 4293 cmp r3, r2 80093ee: d03e beq.n 800946e 80093f0: 687b ldr r3, [r7, #4] 80093f2: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80093f6: 681b ldr r3, [r3, #0] 80093f8: 4a92 ldr r2, [pc, #584] @ (8009644 ) 80093fa: 4293 cmp r3, r2 80093fc: d037 beq.n 800946e 80093fe: 687b ldr r3, [r7, #4] 8009400: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8009404: 681b ldr r3, [r3, #0] 8009406: 4a90 ldr r2, [pc, #576] @ (8009648 ) 8009408: 4293 cmp r3, r2 800940a: d030 beq.n 800946e 800940c: 687b ldr r3, [r7, #4] 800940e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8009412: 681b ldr r3, [r3, #0] 8009414: 4a8d ldr r2, [pc, #564] @ (800964c ) 8009416: 4293 cmp r3, r2 8009418: d029 beq.n 800946e 800941a: 687b ldr r3, [r7, #4] 800941c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8009420: 681b ldr r3, [r3, #0] 8009422: 4a8b ldr r2, [pc, #556] @ (8009650 ) 8009424: 4293 cmp r3, r2 8009426: d022 beq.n 800946e 8009428: 687b ldr r3, [r7, #4] 800942a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800942e: 681b ldr r3, [r3, #0] 8009430: 4a88 ldr r2, [pc, #544] @ (8009654 ) 8009432: 4293 cmp r3, r2 8009434: d01b beq.n 800946e 8009436: 687b ldr r3, [r7, #4] 8009438: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800943c: 681b ldr r3, [r3, #0] 800943e: 4a86 ldr r2, [pc, #536] @ (8009658 ) 8009440: 4293 cmp r3, r2 8009442: d014 beq.n 800946e 8009444: 687b ldr r3, [r7, #4] 8009446: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800944a: 681b ldr r3, [r3, #0] 800944c: 4a83 ldr r2, [pc, #524] @ (800965c ) 800944e: 4293 cmp r3, r2 8009450: d00d beq.n 800946e 8009452: 687b ldr r3, [r7, #4] 8009454: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8009458: 681b ldr r3, [r3, #0] 800945a: 4a81 ldr r2, [pc, #516] @ (8009660 ) 800945c: 4293 cmp r3, r2 800945e: d006 beq.n 800946e 8009460: 687b ldr r3, [r7, #4] 8009462: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8009466: 681b ldr r3, [r3, #0] 8009468: 4a7e ldr r2, [pc, #504] @ (8009664 ) 800946a: 4293 cmp r3, r2 800946c: d106 bne.n 800947c 800946e: 687b ldr r3, [r7, #4] 8009470: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8009474: 681b ldr r3, [r3, #0] 8009476: 685b ldr r3, [r3, #4] 8009478: b29b uxth r3, r3 800947a: e005 b.n 8009488 800947c: 687b ldr r3, [r7, #4] 800947e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8009482: 681b ldr r3, [r3, #0] 8009484: 685b ldr r3, [r3, #4] 8009486: b29b uxth r3, r3 8009488: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 800948c: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 8009490: 2b00 cmp r3, #0 8009492: f000 80ad beq.w 80095f0 && (nb_remaining_rx_data < huart->RxXferSize)) 8009496: 687b ldr r3, [r7, #4] 8009498: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 800949c: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 80094a0: 429a cmp r2, r3 80094a2: f080 80a5 bcs.w 80095f0 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 80094a6: 687b ldr r3, [r7, #4] 80094a8: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 80094ac: f8a3 205e strh.w r2, [r3, #94] @ 0x5e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 80094b0: 687b ldr r3, [r7, #4] 80094b2: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80094b6: 69db ldr r3, [r3, #28] 80094b8: f5b3 7f80 cmp.w r3, #256 @ 0x100 80094bc: f000 8087 beq.w 80095ce { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 80094c0: 687b ldr r3, [r7, #4] 80094c2: 681b ldr r3, [r3, #0] 80094c4: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80094c8: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 80094cc: e853 3f00 ldrex r3, [r3] 80094d0: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 80094d4: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 80094d8: f423 7380 bic.w r3, r3, #256 @ 0x100 80094dc: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 80094e0: 687b ldr r3, [r7, #4] 80094e2: 681b ldr r3, [r3, #0] 80094e4: 461a mov r2, r3 80094e6: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 80094ea: f8c7 3094 str.w r3, [r7, #148] @ 0x94 80094ee: f8c7 2090 str.w r2, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80094f2: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 80094f6: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 80094fa: e841 2300 strex r3, r2, [r1] 80094fe: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8009502: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8009506: 2b00 cmp r3, #0 8009508: d1da bne.n 80094c0 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800950a: 687b ldr r3, [r7, #4] 800950c: 681b ldr r3, [r3, #0] 800950e: 3308 adds r3, #8 8009510: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8009512: 6f7b ldr r3, [r7, #116] @ 0x74 8009514: e853 3f00 ldrex r3, [r3] 8009518: 673b str r3, [r7, #112] @ 0x70 return(result); 800951a: 6f3b ldr r3, [r7, #112] @ 0x70 800951c: f023 0301 bic.w r3, r3, #1 8009520: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8009524: 687b ldr r3, [r7, #4] 8009526: 681b ldr r3, [r3, #0] 8009528: 3308 adds r3, #8 800952a: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 800952e: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8009532: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8009534: 6ff9 ldr r1, [r7, #124] @ 0x7c 8009536: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 800953a: e841 2300 strex r3, r2, [r1] 800953e: 67bb str r3, [r7, #120] @ 0x78 return(result); 8009540: 6fbb ldr r3, [r7, #120] @ 0x78 8009542: 2b00 cmp r3, #0 8009544: d1e1 bne.n 800950a /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8009546: 687b ldr r3, [r7, #4] 8009548: 681b ldr r3, [r3, #0] 800954a: 3308 adds r3, #8 800954c: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800954e: 6e3b ldr r3, [r7, #96] @ 0x60 8009550: e853 3f00 ldrex r3, [r3] 8009554: 65fb str r3, [r7, #92] @ 0x5c return(result); 8009556: 6dfb ldr r3, [r7, #92] @ 0x5c 8009558: f023 0340 bic.w r3, r3, #64 @ 0x40 800955c: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8009560: 687b ldr r3, [r7, #4] 8009562: 681b ldr r3, [r3, #0] 8009564: 3308 adds r3, #8 8009566: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 800956a: 66fa str r2, [r7, #108] @ 0x6c 800956c: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800956e: 6eb9 ldr r1, [r7, #104] @ 0x68 8009570: 6efa ldr r2, [r7, #108] @ 0x6c 8009572: e841 2300 strex r3, r2, [r1] 8009576: 667b str r3, [r7, #100] @ 0x64 return(result); 8009578: 6e7b ldr r3, [r7, #100] @ 0x64 800957a: 2b00 cmp r3, #0 800957c: d1e3 bne.n 8009546 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800957e: 687b ldr r3, [r7, #4] 8009580: 2220 movs r2, #32 8009582: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8009586: 687b ldr r3, [r7, #4] 8009588: 2200 movs r2, #0 800958a: 66da str r2, [r3, #108] @ 0x6c ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800958c: 687b ldr r3, [r7, #4] 800958e: 681b ldr r3, [r3, #0] 8009590: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8009592: 6cfb ldr r3, [r7, #76] @ 0x4c 8009594: e853 3f00 ldrex r3, [r3] 8009598: 64bb str r3, [r7, #72] @ 0x48 return(result); 800959a: 6cbb ldr r3, [r7, #72] @ 0x48 800959c: f023 0310 bic.w r3, r3, #16 80095a0: f8c7 30ac str.w r3, [r7, #172] @ 0xac 80095a4: 687b ldr r3, [r7, #4] 80095a6: 681b ldr r3, [r3, #0] 80095a8: 461a mov r2, r3 80095aa: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80095ae: 65bb str r3, [r7, #88] @ 0x58 80095b0: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80095b2: 6d79 ldr r1, [r7, #84] @ 0x54 80095b4: 6dba ldr r2, [r7, #88] @ 0x58 80095b6: e841 2300 strex r3, r2, [r1] 80095ba: 653b str r3, [r7, #80] @ 0x50 return(result); 80095bc: 6d3b ldr r3, [r7, #80] @ 0x50 80095be: 2b00 cmp r3, #0 80095c0: d1e4 bne.n 800958c /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 80095c2: 687b ldr r3, [r7, #4] 80095c4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80095c8: 4618 mov r0, r3 80095ca: f7f9 fc81 bl 8002ed0 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 80095ce: 687b ldr r3, [r7, #4] 80095d0: 2202 movs r2, #2 80095d2: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 80095d4: 687b ldr r3, [r7, #4] 80095d6: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 80095da: 687b ldr r3, [r7, #4] 80095dc: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80095e0: b29b uxth r3, r3 80095e2: 1ad3 subs r3, r2, r3 80095e4: b29b uxth r3, r3 80095e6: 4619 mov r1, r3 80095e8: 6878 ldr r0, [r7, #4] 80095ea: f000 f939 bl 8009860 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } } } return; 80095ee: e119 b.n 8009824 if (nb_remaining_rx_data == huart->RxXferSize) 80095f0: 687b ldr r3, [r7, #4] 80095f2: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 80095f6: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 80095fa: 429a cmp r2, r3 80095fc: f040 8112 bne.w 8009824 if (huart->hdmarx->Init.Mode == DMA_CIRCULAR) 8009600: 687b ldr r3, [r7, #4] 8009602: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8009606: 69db ldr r3, [r3, #28] 8009608: f5b3 7f80 cmp.w r3, #256 @ 0x100 800960c: f040 810a bne.w 8009824 huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8009610: 687b ldr r3, [r7, #4] 8009612: 2202 movs r2, #2 8009614: 671a str r2, [r3, #112] @ 0x70 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8009616: 687b ldr r3, [r7, #4] 8009618: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 800961c: 4619 mov r1, r3 800961e: 6878 ldr r0, [r7, #4] 8009620: f000 f91e bl 8009860 return; 8009624: e0fe b.n 8009824 8009626: bf00 nop 8009628: 40020010 .word 0x40020010 800962c: 40020028 .word 0x40020028 8009630: 40020040 .word 0x40020040 8009634: 40020058 .word 0x40020058 8009638: 40020070 .word 0x40020070 800963c: 40020088 .word 0x40020088 8009640: 400200a0 .word 0x400200a0 8009644: 400200b8 .word 0x400200b8 8009648: 40020410 .word 0x40020410 800964c: 40020428 .word 0x40020428 8009650: 40020440 .word 0x40020440 8009654: 40020458 .word 0x40020458 8009658: 40020470 .word 0x40020470 800965c: 40020488 .word 0x40020488 8009660: 400204a0 .word 0x400204a0 8009664: 400204b8 .word 0x400204b8 else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8009668: 687b ldr r3, [r7, #4] 800966a: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 800966e: 687b ldr r3, [r7, #4] 8009670: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8009674: b29b uxth r3, r3 8009676: 1ad3 subs r3, r2, r3 8009678: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 800967c: 687b ldr r3, [r7, #4] 800967e: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8009682: b29b uxth r3, r3 8009684: 2b00 cmp r3, #0 8009686: f000 80cf beq.w 8009828 && (nb_rx_data > 0U)) 800968a: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 800968e: 2b00 cmp r3, #0 8009690: f000 80ca beq.w 8009828 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8009694: 687b ldr r3, [r7, #4] 8009696: 681b ldr r3, [r3, #0] 8009698: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800969a: 6bbb ldr r3, [r7, #56] @ 0x38 800969c: e853 3f00 ldrex r3, [r3] 80096a0: 637b str r3, [r7, #52] @ 0x34 return(result); 80096a2: 6b7b ldr r3, [r7, #52] @ 0x34 80096a4: f423 7390 bic.w r3, r3, #288 @ 0x120 80096a8: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 80096ac: 687b ldr r3, [r7, #4] 80096ae: 681b ldr r3, [r3, #0] 80096b0: 461a mov r2, r3 80096b2: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 80096b6: 647b str r3, [r7, #68] @ 0x44 80096b8: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80096ba: 6c39 ldr r1, [r7, #64] @ 0x40 80096bc: 6c7a ldr r2, [r7, #68] @ 0x44 80096be: e841 2300 strex r3, r2, [r1] 80096c2: 63fb str r3, [r7, #60] @ 0x3c return(result); 80096c4: 6bfb ldr r3, [r7, #60] @ 0x3c 80096c6: 2b00 cmp r3, #0 80096c8: d1e4 bne.n 8009694 /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 80096ca: 687b ldr r3, [r7, #4] 80096cc: 681b ldr r3, [r3, #0] 80096ce: 3308 adds r3, #8 80096d0: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80096d2: 6a7b ldr r3, [r7, #36] @ 0x24 80096d4: e853 3f00 ldrex r3, [r3] 80096d8: 623b str r3, [r7, #32] return(result); 80096da: 6a3a ldr r2, [r7, #32] 80096dc: 4b55 ldr r3, [pc, #340] @ (8009834 ) 80096de: 4013 ands r3, r2 80096e0: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 80096e4: 687b ldr r3, [r7, #4] 80096e6: 681b ldr r3, [r3, #0] 80096e8: 3308 adds r3, #8 80096ea: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 80096ee: 633a str r2, [r7, #48] @ 0x30 80096f0: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80096f2: 6af9 ldr r1, [r7, #44] @ 0x2c 80096f4: 6b3a ldr r2, [r7, #48] @ 0x30 80096f6: e841 2300 strex r3, r2, [r1] 80096fa: 62bb str r3, [r7, #40] @ 0x28 return(result); 80096fc: 6abb ldr r3, [r7, #40] @ 0x28 80096fe: 2b00 cmp r3, #0 8009700: d1e3 bne.n 80096ca /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8009702: 687b ldr r3, [r7, #4] 8009704: 2220 movs r2, #32 8009706: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800970a: 687b ldr r3, [r7, #4] 800970c: 2200 movs r2, #0 800970e: 66da str r2, [r3, #108] @ 0x6c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8009710: 687b ldr r3, [r7, #4] 8009712: 2200 movs r2, #0 8009714: 675a str r2, [r3, #116] @ 0x74 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8009716: 687b ldr r3, [r7, #4] 8009718: 681b ldr r3, [r3, #0] 800971a: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800971c: 693b ldr r3, [r7, #16] 800971e: e853 3f00 ldrex r3, [r3] 8009722: 60fb str r3, [r7, #12] return(result); 8009724: 68fb ldr r3, [r7, #12] 8009726: f023 0310 bic.w r3, r3, #16 800972a: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 800972e: 687b ldr r3, [r7, #4] 8009730: 681b ldr r3, [r3, #0] 8009732: 461a mov r2, r3 8009734: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0 8009738: 61fb str r3, [r7, #28] 800973a: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800973c: 69b9 ldr r1, [r7, #24] 800973e: 69fa ldr r2, [r7, #28] 8009740: e841 2300 strex r3, r2, [r1] 8009744: 617b str r3, [r7, #20] return(result); 8009746: 697b ldr r3, [r7, #20] 8009748: 2b00 cmp r3, #0 800974a: d1e4 bne.n 8009716 /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 800974c: 687b ldr r3, [r7, #4] 800974e: 2202 movs r2, #2 8009750: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8009752: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8009756: 4619 mov r1, r3 8009758: 6878 ldr r0, [r7, #4] 800975a: f000 f881 bl 8009860 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; 800975e: e063 b.n 8009828 } } /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) 8009760: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8009764: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8009768: 2b00 cmp r3, #0 800976a: d00e beq.n 800978a 800976c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8009770: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8009774: 2b00 cmp r3, #0 8009776: d008 beq.n 800978a { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); 8009778: 687b ldr r3, [r7, #4] 800977a: 681b ldr r3, [r3, #0] 800977c: f44f 1280 mov.w r2, #1048576 @ 0x100000 8009780: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Wakeup Callback */ huart->WakeupCallback(huart); #else /* Call legacy weak Wakeup Callback */ HAL_UARTEx_WakeupCallback(huart); 8009782: 6878 ldr r0, [r7, #4] 8009784: f001 f83d bl 800a802 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8009788: e051 b.n 800982e } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) 800978a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800978e: f003 0380 and.w r3, r3, #128 @ 0x80 8009792: 2b00 cmp r3, #0 8009794: d014 beq.n 80097c0 && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) 8009796: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 800979a: f003 0380 and.w r3, r3, #128 @ 0x80 800979e: 2b00 cmp r3, #0 80097a0: d105 bne.n 80097ae || ((cr3its & USART_CR3_TXFTIE) != 0U))) 80097a2: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80097a6: f403 0300 and.w r3, r3, #8388608 @ 0x800000 80097aa: 2b00 cmp r3, #0 80097ac: d008 beq.n 80097c0 { if (huart->TxISR != NULL) 80097ae: 687b ldr r3, [r7, #4] 80097b0: 6f9b ldr r3, [r3, #120] @ 0x78 80097b2: 2b00 cmp r3, #0 80097b4: d03a beq.n 800982c { huart->TxISR(huart); 80097b6: 687b ldr r3, [r7, #4] 80097b8: 6f9b ldr r3, [r3, #120] @ 0x78 80097ba: 6878 ldr r0, [r7, #4] 80097bc: 4798 blx r3 } return; 80097be: e035 b.n 800982c } /* UART in mode Transmitter (transmission end) -----------------------------*/ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) 80097c0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80097c4: f003 0340 and.w r3, r3, #64 @ 0x40 80097c8: 2b00 cmp r3, #0 80097ca: d009 beq.n 80097e0 80097cc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80097d0: f003 0340 and.w r3, r3, #64 @ 0x40 80097d4: 2b00 cmp r3, #0 80097d6: d003 beq.n 80097e0 { UART_EndTransmit_IT(huart); 80097d8: 6878 ldr r0, [r7, #4] 80097da: f000 ffe7 bl 800a7ac return; 80097de: e026 b.n 800982e } /* UART TX Fifo Empty occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) 80097e0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80097e4: f403 0300 and.w r3, r3, #8388608 @ 0x800000 80097e8: 2b00 cmp r3, #0 80097ea: d009 beq.n 8009800 80097ec: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80097f0: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 80097f4: 2b00 cmp r3, #0 80097f6: d003 beq.n 8009800 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Tx Fifo Empty Callback */ huart->TxFifoEmptyCallback(huart); #else /* Call legacy weak Tx Fifo Empty Callback */ HAL_UARTEx_TxFifoEmptyCallback(huart); 80097f8: 6878 ldr r0, [r7, #4] 80097fa: f001 f816 bl 800a82a #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 80097fe: e016 b.n 800982e } /* UART RX Fifo Full occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) 8009800: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8009804: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8009808: 2b00 cmp r3, #0 800980a: d010 beq.n 800982e 800980c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8009810: 2b00 cmp r3, #0 8009812: da0c bge.n 800982e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Rx Fifo Full Callback */ huart->RxFifoFullCallback(huart); #else /* Call legacy weak Rx Fifo Full Callback */ HAL_UARTEx_RxFifoFullCallback(huart); 8009814: 6878 ldr r0, [r7, #4] 8009816: f000 fffe bl 800a816 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 800981a: e008 b.n 800982e return; 800981c: bf00 nop 800981e: e006 b.n 800982e return; 8009820: bf00 nop 8009822: e004 b.n 800982e return; 8009824: bf00 nop 8009826: e002 b.n 800982e return; 8009828: bf00 nop 800982a: e000 b.n 800982e return; 800982c: bf00 nop } } 800982e: 37e8 adds r7, #232 @ 0xe8 8009830: 46bd mov sp, r7 8009832: bd80 pop {r7, pc} 8009834: effffffe .word 0xeffffffe 08009838 : * @brief Tx Transfer completed callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 8009838: b480 push {r7} 800983a: b083 sub sp, #12 800983c: af00 add r7, sp, #0 800983e: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_TxCpltCallback can be implemented in the user file. */ } 8009840: bf00 nop 8009842: 370c adds r7, #12 8009844: 46bd mov sp, r7 8009846: f85d 7b04 ldr.w r7, [sp], #4 800984a: 4770 bx lr 0800984c : * @brief UART error callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 800984c: b480 push {r7} 800984e: b083 sub sp, #12 8009850: af00 add r7, sp, #0 8009852: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback can be implemented in the user file. */ } 8009854: bf00 nop 8009856: 370c adds r7, #12 8009858: 46bd mov sp, r7 800985a: f85d 7b04 ldr.w r7, [sp], #4 800985e: 4770 bx lr 08009860 : * @param Size Number of data available in application reception buffer (indicates a position in * reception buffer until which, data are available) * @retval None */ __weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 8009860: b480 push {r7} 8009862: b083 sub sp, #12 8009864: af00 add r7, sp, #0 8009866: 6078 str r0, [r7, #4] 8009868: 460b mov r3, r1 800986a: 807b strh r3, [r7, #2] UNUSED(Size); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxEventCallback can be implemented in the user file. */ } 800986c: bf00 nop 800986e: 370c adds r7, #12 8009870: 46bd mov sp, r7 8009872: f85d 7b04 ldr.w r7, [sp], #4 8009876: 4770 bx lr 08009878 : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { 8009878: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 800987c: b092 sub sp, #72 @ 0x48 800987e: af00 add r7, sp, #0 8009880: 6178 str r0, [r7, #20] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; 8009882: 2300 movs r3, #0 8009884: f887 3042 strb.w r3, [r7, #66] @ 0x42 * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 8009888: 697b ldr r3, [r7, #20] 800988a: 689a ldr r2, [r3, #8] 800988c: 697b ldr r3, [r7, #20] 800988e: 691b ldr r3, [r3, #16] 8009890: 431a orrs r2, r3 8009892: 697b ldr r3, [r7, #20] 8009894: 695b ldr r3, [r3, #20] 8009896: 431a orrs r2, r3 8009898: 697b ldr r3, [r7, #20] 800989a: 69db ldr r3, [r3, #28] 800989c: 4313 orrs r3, r2 800989e: 647b str r3, [r7, #68] @ 0x44 MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 80098a0: 697b ldr r3, [r7, #20] 80098a2: 681b ldr r3, [r3, #0] 80098a4: 681a ldr r2, [r3, #0] 80098a6: 4bbe ldr r3, [pc, #760] @ (8009ba0 ) 80098a8: 4013 ands r3, r2 80098aa: 697a ldr r2, [r7, #20] 80098ac: 6812 ldr r2, [r2, #0] 80098ae: 6c79 ldr r1, [r7, #68] @ 0x44 80098b0: 430b orrs r3, r1 80098b2: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 80098b4: 697b ldr r3, [r7, #20] 80098b6: 681b ldr r3, [r3, #0] 80098b8: 685b ldr r3, [r3, #4] 80098ba: f423 5140 bic.w r1, r3, #12288 @ 0x3000 80098be: 697b ldr r3, [r7, #20] 80098c0: 68da ldr r2, [r3, #12] 80098c2: 697b ldr r3, [r7, #20] 80098c4: 681b ldr r3, [r3, #0] 80098c6: 430a orrs r2, r1 80098c8: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; 80098ca: 697b ldr r3, [r7, #20] 80098cc: 699b ldr r3, [r3, #24] 80098ce: 647b str r3, [r7, #68] @ 0x44 if (!(UART_INSTANCE_LOWPOWER(huart))) 80098d0: 697b ldr r3, [r7, #20] 80098d2: 681b ldr r3, [r3, #0] 80098d4: 4ab3 ldr r2, [pc, #716] @ (8009ba4 ) 80098d6: 4293 cmp r3, r2 80098d8: d004 beq.n 80098e4 { tmpreg |= huart->Init.OneBitSampling; 80098da: 697b ldr r3, [r7, #20] 80098dc: 6a1b ldr r3, [r3, #32] 80098de: 6c7a ldr r2, [r7, #68] @ 0x44 80098e0: 4313 orrs r3, r2 80098e2: 647b str r3, [r7, #68] @ 0x44 } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 80098e4: 697b ldr r3, [r7, #20] 80098e6: 681b ldr r3, [r3, #0] 80098e8: 689a ldr r2, [r3, #8] 80098ea: 4baf ldr r3, [pc, #700] @ (8009ba8 ) 80098ec: 4013 ands r3, r2 80098ee: 697a ldr r2, [r7, #20] 80098f0: 6812 ldr r2, [r2, #0] 80098f2: 6c79 ldr r1, [r7, #68] @ 0x44 80098f4: 430b orrs r3, r1 80098f6: 6093 str r3, [r2, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); 80098f8: 697b ldr r3, [r7, #20] 80098fa: 681b ldr r3, [r3, #0] 80098fc: 6adb ldr r3, [r3, #44] @ 0x2c 80098fe: f023 010f bic.w r1, r3, #15 8009902: 697b ldr r3, [r7, #20] 8009904: 6a5a ldr r2, [r3, #36] @ 0x24 8009906: 697b ldr r3, [r7, #20] 8009908: 681b ldr r3, [r3, #0] 800990a: 430a orrs r2, r1 800990c: 62da str r2, [r3, #44] @ 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); 800990e: 697b ldr r3, [r7, #20] 8009910: 681b ldr r3, [r3, #0] 8009912: 4aa6 ldr r2, [pc, #664] @ (8009bac ) 8009914: 4293 cmp r3, r2 8009916: d177 bne.n 8009a08 8009918: 4ba5 ldr r3, [pc, #660] @ (8009bb0 ) 800991a: 6d5b ldr r3, [r3, #84] @ 0x54 800991c: f003 0338 and.w r3, r3, #56 @ 0x38 8009920: 2b28 cmp r3, #40 @ 0x28 8009922: d86d bhi.n 8009a00 8009924: a201 add r2, pc, #4 @ (adr r2, 800992c ) 8009926: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800992a: bf00 nop 800992c: 080099d1 .word 0x080099d1 8009930: 08009a01 .word 0x08009a01 8009934: 08009a01 .word 0x08009a01 8009938: 08009a01 .word 0x08009a01 800993c: 08009a01 .word 0x08009a01 8009940: 08009a01 .word 0x08009a01 8009944: 08009a01 .word 0x08009a01 8009948: 08009a01 .word 0x08009a01 800994c: 080099d9 .word 0x080099d9 8009950: 08009a01 .word 0x08009a01 8009954: 08009a01 .word 0x08009a01 8009958: 08009a01 .word 0x08009a01 800995c: 08009a01 .word 0x08009a01 8009960: 08009a01 .word 0x08009a01 8009964: 08009a01 .word 0x08009a01 8009968: 08009a01 .word 0x08009a01 800996c: 080099e1 .word 0x080099e1 8009970: 08009a01 .word 0x08009a01 8009974: 08009a01 .word 0x08009a01 8009978: 08009a01 .word 0x08009a01 800997c: 08009a01 .word 0x08009a01 8009980: 08009a01 .word 0x08009a01 8009984: 08009a01 .word 0x08009a01 8009988: 08009a01 .word 0x08009a01 800998c: 080099e9 .word 0x080099e9 8009990: 08009a01 .word 0x08009a01 8009994: 08009a01 .word 0x08009a01 8009998: 08009a01 .word 0x08009a01 800999c: 08009a01 .word 0x08009a01 80099a0: 08009a01 .word 0x08009a01 80099a4: 08009a01 .word 0x08009a01 80099a8: 08009a01 .word 0x08009a01 80099ac: 080099f1 .word 0x080099f1 80099b0: 08009a01 .word 0x08009a01 80099b4: 08009a01 .word 0x08009a01 80099b8: 08009a01 .word 0x08009a01 80099bc: 08009a01 .word 0x08009a01 80099c0: 08009a01 .word 0x08009a01 80099c4: 08009a01 .word 0x08009a01 80099c8: 08009a01 .word 0x08009a01 80099cc: 080099f9 .word 0x080099f9 80099d0: 2301 movs r3, #1 80099d2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80099d6: e222 b.n 8009e1e 80099d8: 2304 movs r3, #4 80099da: f887 3043 strb.w r3, [r7, #67] @ 0x43 80099de: e21e b.n 8009e1e 80099e0: 2308 movs r3, #8 80099e2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80099e6: e21a b.n 8009e1e 80099e8: 2310 movs r3, #16 80099ea: f887 3043 strb.w r3, [r7, #67] @ 0x43 80099ee: e216 b.n 8009e1e 80099f0: 2320 movs r3, #32 80099f2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80099f6: e212 b.n 8009e1e 80099f8: 2340 movs r3, #64 @ 0x40 80099fa: f887 3043 strb.w r3, [r7, #67] @ 0x43 80099fe: e20e b.n 8009e1e 8009a00: 2380 movs r3, #128 @ 0x80 8009a02: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009a06: e20a b.n 8009e1e 8009a08: 697b ldr r3, [r7, #20] 8009a0a: 681b ldr r3, [r3, #0] 8009a0c: 4a69 ldr r2, [pc, #420] @ (8009bb4 ) 8009a0e: 4293 cmp r3, r2 8009a10: d130 bne.n 8009a74 8009a12: 4b67 ldr r3, [pc, #412] @ (8009bb0 ) 8009a14: 6d5b ldr r3, [r3, #84] @ 0x54 8009a16: f003 0307 and.w r3, r3, #7 8009a1a: 2b05 cmp r3, #5 8009a1c: d826 bhi.n 8009a6c 8009a1e: a201 add r2, pc, #4 @ (adr r2, 8009a24 ) 8009a20: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009a24: 08009a3d .word 0x08009a3d 8009a28: 08009a45 .word 0x08009a45 8009a2c: 08009a4d .word 0x08009a4d 8009a30: 08009a55 .word 0x08009a55 8009a34: 08009a5d .word 0x08009a5d 8009a38: 08009a65 .word 0x08009a65 8009a3c: 2300 movs r3, #0 8009a3e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009a42: e1ec b.n 8009e1e 8009a44: 2304 movs r3, #4 8009a46: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009a4a: e1e8 b.n 8009e1e 8009a4c: 2308 movs r3, #8 8009a4e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009a52: e1e4 b.n 8009e1e 8009a54: 2310 movs r3, #16 8009a56: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009a5a: e1e0 b.n 8009e1e 8009a5c: 2320 movs r3, #32 8009a5e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009a62: e1dc b.n 8009e1e 8009a64: 2340 movs r3, #64 @ 0x40 8009a66: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009a6a: e1d8 b.n 8009e1e 8009a6c: 2380 movs r3, #128 @ 0x80 8009a6e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009a72: e1d4 b.n 8009e1e 8009a74: 697b ldr r3, [r7, #20] 8009a76: 681b ldr r3, [r3, #0] 8009a78: 4a4f ldr r2, [pc, #316] @ (8009bb8 ) 8009a7a: 4293 cmp r3, r2 8009a7c: d130 bne.n 8009ae0 8009a7e: 4b4c ldr r3, [pc, #304] @ (8009bb0 ) 8009a80: 6d5b ldr r3, [r3, #84] @ 0x54 8009a82: f003 0307 and.w r3, r3, #7 8009a86: 2b05 cmp r3, #5 8009a88: d826 bhi.n 8009ad8 8009a8a: a201 add r2, pc, #4 @ (adr r2, 8009a90 ) 8009a8c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009a90: 08009aa9 .word 0x08009aa9 8009a94: 08009ab1 .word 0x08009ab1 8009a98: 08009ab9 .word 0x08009ab9 8009a9c: 08009ac1 .word 0x08009ac1 8009aa0: 08009ac9 .word 0x08009ac9 8009aa4: 08009ad1 .word 0x08009ad1 8009aa8: 2300 movs r3, #0 8009aaa: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009aae: e1b6 b.n 8009e1e 8009ab0: 2304 movs r3, #4 8009ab2: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009ab6: e1b2 b.n 8009e1e 8009ab8: 2308 movs r3, #8 8009aba: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009abe: e1ae b.n 8009e1e 8009ac0: 2310 movs r3, #16 8009ac2: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009ac6: e1aa b.n 8009e1e 8009ac8: 2320 movs r3, #32 8009aca: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009ace: e1a6 b.n 8009e1e 8009ad0: 2340 movs r3, #64 @ 0x40 8009ad2: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009ad6: e1a2 b.n 8009e1e 8009ad8: 2380 movs r3, #128 @ 0x80 8009ada: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009ade: e19e b.n 8009e1e 8009ae0: 697b ldr r3, [r7, #20] 8009ae2: 681b ldr r3, [r3, #0] 8009ae4: 4a35 ldr r2, [pc, #212] @ (8009bbc ) 8009ae6: 4293 cmp r3, r2 8009ae8: d130 bne.n 8009b4c 8009aea: 4b31 ldr r3, [pc, #196] @ (8009bb0 ) 8009aec: 6d5b ldr r3, [r3, #84] @ 0x54 8009aee: f003 0307 and.w r3, r3, #7 8009af2: 2b05 cmp r3, #5 8009af4: d826 bhi.n 8009b44 8009af6: a201 add r2, pc, #4 @ (adr r2, 8009afc ) 8009af8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009afc: 08009b15 .word 0x08009b15 8009b00: 08009b1d .word 0x08009b1d 8009b04: 08009b25 .word 0x08009b25 8009b08: 08009b2d .word 0x08009b2d 8009b0c: 08009b35 .word 0x08009b35 8009b10: 08009b3d .word 0x08009b3d 8009b14: 2300 movs r3, #0 8009b16: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009b1a: e180 b.n 8009e1e 8009b1c: 2304 movs r3, #4 8009b1e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009b22: e17c b.n 8009e1e 8009b24: 2308 movs r3, #8 8009b26: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009b2a: e178 b.n 8009e1e 8009b2c: 2310 movs r3, #16 8009b2e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009b32: e174 b.n 8009e1e 8009b34: 2320 movs r3, #32 8009b36: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009b3a: e170 b.n 8009e1e 8009b3c: 2340 movs r3, #64 @ 0x40 8009b3e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009b42: e16c b.n 8009e1e 8009b44: 2380 movs r3, #128 @ 0x80 8009b46: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009b4a: e168 b.n 8009e1e 8009b4c: 697b ldr r3, [r7, #20] 8009b4e: 681b ldr r3, [r3, #0] 8009b50: 4a1b ldr r2, [pc, #108] @ (8009bc0 ) 8009b52: 4293 cmp r3, r2 8009b54: d142 bne.n 8009bdc 8009b56: 4b16 ldr r3, [pc, #88] @ (8009bb0 ) 8009b58: 6d5b ldr r3, [r3, #84] @ 0x54 8009b5a: f003 0307 and.w r3, r3, #7 8009b5e: 2b05 cmp r3, #5 8009b60: d838 bhi.n 8009bd4 8009b62: a201 add r2, pc, #4 @ (adr r2, 8009b68 ) 8009b64: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009b68: 08009b81 .word 0x08009b81 8009b6c: 08009b89 .word 0x08009b89 8009b70: 08009b91 .word 0x08009b91 8009b74: 08009b99 .word 0x08009b99 8009b78: 08009bc5 .word 0x08009bc5 8009b7c: 08009bcd .word 0x08009bcd 8009b80: 2300 movs r3, #0 8009b82: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009b86: e14a b.n 8009e1e 8009b88: 2304 movs r3, #4 8009b8a: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009b8e: e146 b.n 8009e1e 8009b90: 2308 movs r3, #8 8009b92: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009b96: e142 b.n 8009e1e 8009b98: 2310 movs r3, #16 8009b9a: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009b9e: e13e b.n 8009e1e 8009ba0: cfff69f3 .word 0xcfff69f3 8009ba4: 58000c00 .word 0x58000c00 8009ba8: 11fff4ff .word 0x11fff4ff 8009bac: 40011000 .word 0x40011000 8009bb0: 58024400 .word 0x58024400 8009bb4: 40004400 .word 0x40004400 8009bb8: 40004800 .word 0x40004800 8009bbc: 40004c00 .word 0x40004c00 8009bc0: 40005000 .word 0x40005000 8009bc4: 2320 movs r3, #32 8009bc6: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009bca: e128 b.n 8009e1e 8009bcc: 2340 movs r3, #64 @ 0x40 8009bce: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009bd2: e124 b.n 8009e1e 8009bd4: 2380 movs r3, #128 @ 0x80 8009bd6: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009bda: e120 b.n 8009e1e 8009bdc: 697b ldr r3, [r7, #20] 8009bde: 681b ldr r3, [r3, #0] 8009be0: 4acb ldr r2, [pc, #812] @ (8009f10 ) 8009be2: 4293 cmp r3, r2 8009be4: d176 bne.n 8009cd4 8009be6: 4bcb ldr r3, [pc, #812] @ (8009f14 ) 8009be8: 6d5b ldr r3, [r3, #84] @ 0x54 8009bea: f003 0338 and.w r3, r3, #56 @ 0x38 8009bee: 2b28 cmp r3, #40 @ 0x28 8009bf0: d86c bhi.n 8009ccc 8009bf2: a201 add r2, pc, #4 @ (adr r2, 8009bf8 ) 8009bf4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009bf8: 08009c9d .word 0x08009c9d 8009bfc: 08009ccd .word 0x08009ccd 8009c00: 08009ccd .word 0x08009ccd 8009c04: 08009ccd .word 0x08009ccd 8009c08: 08009ccd .word 0x08009ccd 8009c0c: 08009ccd .word 0x08009ccd 8009c10: 08009ccd .word 0x08009ccd 8009c14: 08009ccd .word 0x08009ccd 8009c18: 08009ca5 .word 0x08009ca5 8009c1c: 08009ccd .word 0x08009ccd 8009c20: 08009ccd .word 0x08009ccd 8009c24: 08009ccd .word 0x08009ccd 8009c28: 08009ccd .word 0x08009ccd 8009c2c: 08009ccd .word 0x08009ccd 8009c30: 08009ccd .word 0x08009ccd 8009c34: 08009ccd .word 0x08009ccd 8009c38: 08009cad .word 0x08009cad 8009c3c: 08009ccd .word 0x08009ccd 8009c40: 08009ccd .word 0x08009ccd 8009c44: 08009ccd .word 0x08009ccd 8009c48: 08009ccd .word 0x08009ccd 8009c4c: 08009ccd .word 0x08009ccd 8009c50: 08009ccd .word 0x08009ccd 8009c54: 08009ccd .word 0x08009ccd 8009c58: 08009cb5 .word 0x08009cb5 8009c5c: 08009ccd .word 0x08009ccd 8009c60: 08009ccd .word 0x08009ccd 8009c64: 08009ccd .word 0x08009ccd 8009c68: 08009ccd .word 0x08009ccd 8009c6c: 08009ccd .word 0x08009ccd 8009c70: 08009ccd .word 0x08009ccd 8009c74: 08009ccd .word 0x08009ccd 8009c78: 08009cbd .word 0x08009cbd 8009c7c: 08009ccd .word 0x08009ccd 8009c80: 08009ccd .word 0x08009ccd 8009c84: 08009ccd .word 0x08009ccd 8009c88: 08009ccd .word 0x08009ccd 8009c8c: 08009ccd .word 0x08009ccd 8009c90: 08009ccd .word 0x08009ccd 8009c94: 08009ccd .word 0x08009ccd 8009c98: 08009cc5 .word 0x08009cc5 8009c9c: 2301 movs r3, #1 8009c9e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009ca2: e0bc b.n 8009e1e 8009ca4: 2304 movs r3, #4 8009ca6: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009caa: e0b8 b.n 8009e1e 8009cac: 2308 movs r3, #8 8009cae: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009cb2: e0b4 b.n 8009e1e 8009cb4: 2310 movs r3, #16 8009cb6: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009cba: e0b0 b.n 8009e1e 8009cbc: 2320 movs r3, #32 8009cbe: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009cc2: e0ac b.n 8009e1e 8009cc4: 2340 movs r3, #64 @ 0x40 8009cc6: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009cca: e0a8 b.n 8009e1e 8009ccc: 2380 movs r3, #128 @ 0x80 8009cce: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009cd2: e0a4 b.n 8009e1e 8009cd4: 697b ldr r3, [r7, #20] 8009cd6: 681b ldr r3, [r3, #0] 8009cd8: 4a8f ldr r2, [pc, #572] @ (8009f18 ) 8009cda: 4293 cmp r3, r2 8009cdc: d130 bne.n 8009d40 8009cde: 4b8d ldr r3, [pc, #564] @ (8009f14 ) 8009ce0: 6d5b ldr r3, [r3, #84] @ 0x54 8009ce2: f003 0307 and.w r3, r3, #7 8009ce6: 2b05 cmp r3, #5 8009ce8: d826 bhi.n 8009d38 8009cea: a201 add r2, pc, #4 @ (adr r2, 8009cf0 ) 8009cec: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009cf0: 08009d09 .word 0x08009d09 8009cf4: 08009d11 .word 0x08009d11 8009cf8: 08009d19 .word 0x08009d19 8009cfc: 08009d21 .word 0x08009d21 8009d00: 08009d29 .word 0x08009d29 8009d04: 08009d31 .word 0x08009d31 8009d08: 2300 movs r3, #0 8009d0a: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009d0e: e086 b.n 8009e1e 8009d10: 2304 movs r3, #4 8009d12: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009d16: e082 b.n 8009e1e 8009d18: 2308 movs r3, #8 8009d1a: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009d1e: e07e b.n 8009e1e 8009d20: 2310 movs r3, #16 8009d22: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009d26: e07a b.n 8009e1e 8009d28: 2320 movs r3, #32 8009d2a: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009d2e: e076 b.n 8009e1e 8009d30: 2340 movs r3, #64 @ 0x40 8009d32: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009d36: e072 b.n 8009e1e 8009d38: 2380 movs r3, #128 @ 0x80 8009d3a: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009d3e: e06e b.n 8009e1e 8009d40: 697b ldr r3, [r7, #20] 8009d42: 681b ldr r3, [r3, #0] 8009d44: 4a75 ldr r2, [pc, #468] @ (8009f1c ) 8009d46: 4293 cmp r3, r2 8009d48: d130 bne.n 8009dac 8009d4a: 4b72 ldr r3, [pc, #456] @ (8009f14 ) 8009d4c: 6d5b ldr r3, [r3, #84] @ 0x54 8009d4e: f003 0307 and.w r3, r3, #7 8009d52: 2b05 cmp r3, #5 8009d54: d826 bhi.n 8009da4 8009d56: a201 add r2, pc, #4 @ (adr r2, 8009d5c ) 8009d58: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009d5c: 08009d75 .word 0x08009d75 8009d60: 08009d7d .word 0x08009d7d 8009d64: 08009d85 .word 0x08009d85 8009d68: 08009d8d .word 0x08009d8d 8009d6c: 08009d95 .word 0x08009d95 8009d70: 08009d9d .word 0x08009d9d 8009d74: 2300 movs r3, #0 8009d76: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009d7a: e050 b.n 8009e1e 8009d7c: 2304 movs r3, #4 8009d7e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009d82: e04c b.n 8009e1e 8009d84: 2308 movs r3, #8 8009d86: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009d8a: e048 b.n 8009e1e 8009d8c: 2310 movs r3, #16 8009d8e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009d92: e044 b.n 8009e1e 8009d94: 2320 movs r3, #32 8009d96: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009d9a: e040 b.n 8009e1e 8009d9c: 2340 movs r3, #64 @ 0x40 8009d9e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009da2: e03c b.n 8009e1e 8009da4: 2380 movs r3, #128 @ 0x80 8009da6: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009daa: e038 b.n 8009e1e 8009dac: 697b ldr r3, [r7, #20] 8009dae: 681b ldr r3, [r3, #0] 8009db0: 4a5b ldr r2, [pc, #364] @ (8009f20 ) 8009db2: 4293 cmp r3, r2 8009db4: d130 bne.n 8009e18 8009db6: 4b57 ldr r3, [pc, #348] @ (8009f14 ) 8009db8: 6d9b ldr r3, [r3, #88] @ 0x58 8009dba: f003 0307 and.w r3, r3, #7 8009dbe: 2b05 cmp r3, #5 8009dc0: d826 bhi.n 8009e10 8009dc2: a201 add r2, pc, #4 @ (adr r2, 8009dc8 ) 8009dc4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009dc8: 08009de1 .word 0x08009de1 8009dcc: 08009de9 .word 0x08009de9 8009dd0: 08009df1 .word 0x08009df1 8009dd4: 08009df9 .word 0x08009df9 8009dd8: 08009e01 .word 0x08009e01 8009ddc: 08009e09 .word 0x08009e09 8009de0: 2302 movs r3, #2 8009de2: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009de6: e01a b.n 8009e1e 8009de8: 2304 movs r3, #4 8009dea: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009dee: e016 b.n 8009e1e 8009df0: 2308 movs r3, #8 8009df2: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009df6: e012 b.n 8009e1e 8009df8: 2310 movs r3, #16 8009dfa: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009dfe: e00e b.n 8009e1e 8009e00: 2320 movs r3, #32 8009e02: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009e06: e00a b.n 8009e1e 8009e08: 2340 movs r3, #64 @ 0x40 8009e0a: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009e0e: e006 b.n 8009e1e 8009e10: 2380 movs r3, #128 @ 0x80 8009e12: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009e16: e002 b.n 8009e1e 8009e18: 2380 movs r3, #128 @ 0x80 8009e1a: f887 3043 strb.w r3, [r7, #67] @ 0x43 /* Check LPUART instance */ if (UART_INSTANCE_LOWPOWER(huart)) 8009e1e: 697b ldr r3, [r7, #20] 8009e20: 681b ldr r3, [r3, #0] 8009e22: 4a3f ldr r2, [pc, #252] @ (8009f20 ) 8009e24: 4293 cmp r3, r2 8009e26: f040 80f8 bne.w 800a01a { /* Retrieve frequency clock */ switch (clocksource) 8009e2a: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 8009e2e: 2b20 cmp r3, #32 8009e30: dc46 bgt.n 8009ec0 8009e32: 2b02 cmp r3, #2 8009e34: f2c0 8082 blt.w 8009f3c 8009e38: 3b02 subs r3, #2 8009e3a: 2b1e cmp r3, #30 8009e3c: d87e bhi.n 8009f3c 8009e3e: a201 add r2, pc, #4 @ (adr r2, 8009e44 ) 8009e40: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009e44: 08009ec7 .word 0x08009ec7 8009e48: 08009f3d .word 0x08009f3d 8009e4c: 08009ecf .word 0x08009ecf 8009e50: 08009f3d .word 0x08009f3d 8009e54: 08009f3d .word 0x08009f3d 8009e58: 08009f3d .word 0x08009f3d 8009e5c: 08009edf .word 0x08009edf 8009e60: 08009f3d .word 0x08009f3d 8009e64: 08009f3d .word 0x08009f3d 8009e68: 08009f3d .word 0x08009f3d 8009e6c: 08009f3d .word 0x08009f3d 8009e70: 08009f3d .word 0x08009f3d 8009e74: 08009f3d .word 0x08009f3d 8009e78: 08009f3d .word 0x08009f3d 8009e7c: 08009eef .word 0x08009eef 8009e80: 08009f3d .word 0x08009f3d 8009e84: 08009f3d .word 0x08009f3d 8009e88: 08009f3d .word 0x08009f3d 8009e8c: 08009f3d .word 0x08009f3d 8009e90: 08009f3d .word 0x08009f3d 8009e94: 08009f3d .word 0x08009f3d 8009e98: 08009f3d .word 0x08009f3d 8009e9c: 08009f3d .word 0x08009f3d 8009ea0: 08009f3d .word 0x08009f3d 8009ea4: 08009f3d .word 0x08009f3d 8009ea8: 08009f3d .word 0x08009f3d 8009eac: 08009f3d .word 0x08009f3d 8009eb0: 08009f3d .word 0x08009f3d 8009eb4: 08009f3d .word 0x08009f3d 8009eb8: 08009f3d .word 0x08009f3d 8009ebc: 08009f2f .word 0x08009f2f 8009ec0: 2b40 cmp r3, #64 @ 0x40 8009ec2: d037 beq.n 8009f34 8009ec4: e03a b.n 8009f3c { case UART_CLOCKSOURCE_D3PCLK1: pclk = HAL_RCCEx_GetD3PCLK1Freq(); 8009ec6: f7fe f841 bl 8007f4c 8009eca: 63f8 str r0, [r7, #60] @ 0x3c break; 8009ecc: e03c b.n 8009f48 case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8009ece: f107 0324 add.w r3, r7, #36 @ 0x24 8009ed2: 4618 mov r0, r3 8009ed4: f7fe f850 bl 8007f78 pclk = pll2_clocks.PLL2_Q_Frequency; 8009ed8: 6abb ldr r3, [r7, #40] @ 0x28 8009eda: 63fb str r3, [r7, #60] @ 0x3c break; 8009edc: e034 b.n 8009f48 case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8009ede: f107 0318 add.w r3, r7, #24 8009ee2: 4618 mov r0, r3 8009ee4: f7fe f99c bl 8008220 pclk = pll3_clocks.PLL3_Q_Frequency; 8009ee8: 69fb ldr r3, [r7, #28] 8009eea: 63fb str r3, [r7, #60] @ 0x3c break; 8009eec: e02c b.n 8009f48 case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8009eee: 4b09 ldr r3, [pc, #36] @ (8009f14 ) 8009ef0: 681b ldr r3, [r3, #0] 8009ef2: f003 0320 and.w r3, r3, #32 8009ef6: 2b00 cmp r3, #0 8009ef8: d016 beq.n 8009f28 { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 8009efa: 4b06 ldr r3, [pc, #24] @ (8009f14 ) 8009efc: 681b ldr r3, [r3, #0] 8009efe: 08db lsrs r3, r3, #3 8009f00: f003 0303 and.w r3, r3, #3 8009f04: 4a07 ldr r2, [pc, #28] @ (8009f24 ) 8009f06: fa22 f303 lsr.w r3, r2, r3 8009f0a: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 8009f0c: e01c b.n 8009f48 8009f0e: bf00 nop 8009f10: 40011400 .word 0x40011400 8009f14: 58024400 .word 0x58024400 8009f18: 40007800 .word 0x40007800 8009f1c: 40007c00 .word 0x40007c00 8009f20: 58000c00 .word 0x58000c00 8009f24: 03d09000 .word 0x03d09000 pclk = (uint32_t) HSI_VALUE; 8009f28: 4b9d ldr r3, [pc, #628] @ (800a1a0 ) 8009f2a: 63fb str r3, [r7, #60] @ 0x3c break; 8009f2c: e00c b.n 8009f48 case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 8009f2e: 4b9d ldr r3, [pc, #628] @ (800a1a4 ) 8009f30: 63fb str r3, [r7, #60] @ 0x3c break; 8009f32: e009 b.n 8009f48 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8009f34: f44f 4300 mov.w r3, #32768 @ 0x8000 8009f38: 63fb str r3, [r7, #60] @ 0x3c break; 8009f3a: e005 b.n 8009f48 default: pclk = 0U; 8009f3c: 2300 movs r3, #0 8009f3e: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 8009f40: 2301 movs r3, #1 8009f42: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 8009f46: bf00 nop } /* If proper clock source reported */ if (pclk != 0U) 8009f48: 6bfb ldr r3, [r7, #60] @ 0x3c 8009f4a: 2b00 cmp r3, #0 8009f4c: f000 81de beq.w 800a30c { /* Compute clock after Prescaler */ lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); 8009f50: 697b ldr r3, [r7, #20] 8009f52: 6a5b ldr r3, [r3, #36] @ 0x24 8009f54: 4a94 ldr r2, [pc, #592] @ (800a1a8 ) 8009f56: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8009f5a: 461a mov r2, r3 8009f5c: 6bfb ldr r3, [r7, #60] @ 0x3c 8009f5e: fbb3 f3f2 udiv r3, r3, r2 8009f62: 633b str r3, [r7, #48] @ 0x30 /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 8009f64: 697b ldr r3, [r7, #20] 8009f66: 685a ldr r2, [r3, #4] 8009f68: 4613 mov r3, r2 8009f6a: 005b lsls r3, r3, #1 8009f6c: 4413 add r3, r2 8009f6e: 6b3a ldr r2, [r7, #48] @ 0x30 8009f70: 429a cmp r2, r3 8009f72: d305 bcc.n 8009f80 (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) 8009f74: 697b ldr r3, [r7, #20] 8009f76: 685b ldr r3, [r3, #4] 8009f78: 031b lsls r3, r3, #12 if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 8009f7a: 6b3a ldr r2, [r7, #48] @ 0x30 8009f7c: 429a cmp r2, r3 8009f7e: d903 bls.n 8009f88 { ret = HAL_ERROR; 8009f80: 2301 movs r3, #1 8009f82: f887 3042 strb.w r3, [r7, #66] @ 0x42 8009f86: e1c1 b.n 800a30c } else { /* Check computed UsartDiv value is in allocated range (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 8009f88: 6bfb ldr r3, [r7, #60] @ 0x3c 8009f8a: 2200 movs r2, #0 8009f8c: 60bb str r3, [r7, #8] 8009f8e: 60fa str r2, [r7, #12] 8009f90: 697b ldr r3, [r7, #20] 8009f92: 6a5b ldr r3, [r3, #36] @ 0x24 8009f94: 4a84 ldr r2, [pc, #528] @ (800a1a8 ) 8009f96: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8009f9a: b29b uxth r3, r3 8009f9c: 2200 movs r2, #0 8009f9e: 603b str r3, [r7, #0] 8009fa0: 607a str r2, [r7, #4] 8009fa2: e9d7 2300 ldrd r2, r3, [r7] 8009fa6: e9d7 0102 ldrd r0, r1, [r7, #8] 8009faa: f7f6 f995 bl 80002d8 <__aeabi_uldivmod> 8009fae: 4602 mov r2, r0 8009fb0: 460b mov r3, r1 8009fb2: 4610 mov r0, r2 8009fb4: 4619 mov r1, r3 8009fb6: f04f 0200 mov.w r2, #0 8009fba: f04f 0300 mov.w r3, #0 8009fbe: 020b lsls r3, r1, #8 8009fc0: ea43 6310 orr.w r3, r3, r0, lsr #24 8009fc4: 0202 lsls r2, r0, #8 8009fc6: 6979 ldr r1, [r7, #20] 8009fc8: 6849 ldr r1, [r1, #4] 8009fca: 0849 lsrs r1, r1, #1 8009fcc: 2000 movs r0, #0 8009fce: 460c mov r4, r1 8009fd0: 4605 mov r5, r0 8009fd2: eb12 0804 adds.w r8, r2, r4 8009fd6: eb43 0905 adc.w r9, r3, r5 8009fda: 697b ldr r3, [r7, #20] 8009fdc: 685b ldr r3, [r3, #4] 8009fde: 2200 movs r2, #0 8009fe0: 469a mov sl, r3 8009fe2: 4693 mov fp, r2 8009fe4: 4652 mov r2, sl 8009fe6: 465b mov r3, fp 8009fe8: 4640 mov r0, r8 8009fea: 4649 mov r1, r9 8009fec: f7f6 f974 bl 80002d8 <__aeabi_uldivmod> 8009ff0: 4602 mov r2, r0 8009ff2: 460b mov r3, r1 8009ff4: 4613 mov r3, r2 8009ff6: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) 8009ff8: 6bbb ldr r3, [r7, #56] @ 0x38 8009ffa: f5b3 7f40 cmp.w r3, #768 @ 0x300 8009ffe: d308 bcc.n 800a012 800a000: 6bbb ldr r3, [r7, #56] @ 0x38 800a002: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800a006: d204 bcs.n 800a012 { huart->Instance->BRR = usartdiv; 800a008: 697b ldr r3, [r7, #20] 800a00a: 681b ldr r3, [r3, #0] 800a00c: 6bba ldr r2, [r7, #56] @ 0x38 800a00e: 60da str r2, [r3, #12] 800a010: e17c b.n 800a30c } else { ret = HAL_ERROR; 800a012: 2301 movs r3, #1 800a014: f887 3042 strb.w r3, [r7, #66] @ 0x42 800a018: e178 b.n 800a30c } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 800a01a: 697b ldr r3, [r7, #20] 800a01c: 69db ldr r3, [r3, #28] 800a01e: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800a022: f040 80c5 bne.w 800a1b0 { switch (clocksource) 800a026: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 800a02a: 2b20 cmp r3, #32 800a02c: dc48 bgt.n 800a0c0 800a02e: 2b00 cmp r3, #0 800a030: db7b blt.n 800a12a 800a032: 2b20 cmp r3, #32 800a034: d879 bhi.n 800a12a 800a036: a201 add r2, pc, #4 @ (adr r2, 800a03c ) 800a038: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800a03c: 0800a0c7 .word 0x0800a0c7 800a040: 0800a0cf .word 0x0800a0cf 800a044: 0800a12b .word 0x0800a12b 800a048: 0800a12b .word 0x0800a12b 800a04c: 0800a0d7 .word 0x0800a0d7 800a050: 0800a12b .word 0x0800a12b 800a054: 0800a12b .word 0x0800a12b 800a058: 0800a12b .word 0x0800a12b 800a05c: 0800a0e7 .word 0x0800a0e7 800a060: 0800a12b .word 0x0800a12b 800a064: 0800a12b .word 0x0800a12b 800a068: 0800a12b .word 0x0800a12b 800a06c: 0800a12b .word 0x0800a12b 800a070: 0800a12b .word 0x0800a12b 800a074: 0800a12b .word 0x0800a12b 800a078: 0800a12b .word 0x0800a12b 800a07c: 0800a0f7 .word 0x0800a0f7 800a080: 0800a12b .word 0x0800a12b 800a084: 0800a12b .word 0x0800a12b 800a088: 0800a12b .word 0x0800a12b 800a08c: 0800a12b .word 0x0800a12b 800a090: 0800a12b .word 0x0800a12b 800a094: 0800a12b .word 0x0800a12b 800a098: 0800a12b .word 0x0800a12b 800a09c: 0800a12b .word 0x0800a12b 800a0a0: 0800a12b .word 0x0800a12b 800a0a4: 0800a12b .word 0x0800a12b 800a0a8: 0800a12b .word 0x0800a12b 800a0ac: 0800a12b .word 0x0800a12b 800a0b0: 0800a12b .word 0x0800a12b 800a0b4: 0800a12b .word 0x0800a12b 800a0b8: 0800a12b .word 0x0800a12b 800a0bc: 0800a11d .word 0x0800a11d 800a0c0: 2b40 cmp r3, #64 @ 0x40 800a0c2: d02e beq.n 800a122 800a0c4: e031 b.n 800a12a { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 800a0c6: f7fb ff8b bl 8005fe0 800a0ca: 63f8 str r0, [r7, #60] @ 0x3c break; 800a0cc: e033 b.n 800a136 case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 800a0ce: f7fb ff9d bl 800600c 800a0d2: 63f8 str r0, [r7, #60] @ 0x3c break; 800a0d4: e02f b.n 800a136 case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800a0d6: f107 0324 add.w r3, r7, #36 @ 0x24 800a0da: 4618 mov r0, r3 800a0dc: f7fd ff4c bl 8007f78 pclk = pll2_clocks.PLL2_Q_Frequency; 800a0e0: 6abb ldr r3, [r7, #40] @ 0x28 800a0e2: 63fb str r3, [r7, #60] @ 0x3c break; 800a0e4: e027 b.n 800a136 case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800a0e6: f107 0318 add.w r3, r7, #24 800a0ea: 4618 mov r0, r3 800a0ec: f7fe f898 bl 8008220 pclk = pll3_clocks.PLL3_Q_Frequency; 800a0f0: 69fb ldr r3, [r7, #28] 800a0f2: 63fb str r3, [r7, #60] @ 0x3c break; 800a0f4: e01f b.n 800a136 case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800a0f6: 4b2d ldr r3, [pc, #180] @ (800a1ac ) 800a0f8: 681b ldr r3, [r3, #0] 800a0fa: f003 0320 and.w r3, r3, #32 800a0fe: 2b00 cmp r3, #0 800a100: d009 beq.n 800a116 { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 800a102: 4b2a ldr r3, [pc, #168] @ (800a1ac ) 800a104: 681b ldr r3, [r3, #0] 800a106: 08db lsrs r3, r3, #3 800a108: f003 0303 and.w r3, r3, #3 800a10c: 4a24 ldr r2, [pc, #144] @ (800a1a0 ) 800a10e: fa22 f303 lsr.w r3, r2, r3 800a112: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 800a114: e00f b.n 800a136 pclk = (uint32_t) HSI_VALUE; 800a116: 4b22 ldr r3, [pc, #136] @ (800a1a0 ) 800a118: 63fb str r3, [r7, #60] @ 0x3c break; 800a11a: e00c b.n 800a136 case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 800a11c: 4b21 ldr r3, [pc, #132] @ (800a1a4 ) 800a11e: 63fb str r3, [r7, #60] @ 0x3c break; 800a120: e009 b.n 800a136 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 800a122: f44f 4300 mov.w r3, #32768 @ 0x8000 800a126: 63fb str r3, [r7, #60] @ 0x3c break; 800a128: e005 b.n 800a136 default: pclk = 0U; 800a12a: 2300 movs r3, #0 800a12c: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 800a12e: 2301 movs r3, #1 800a130: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 800a134: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) 800a136: 6bfb ldr r3, [r7, #60] @ 0x3c 800a138: 2b00 cmp r3, #0 800a13a: f000 80e7 beq.w 800a30c { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 800a13e: 697b ldr r3, [r7, #20] 800a140: 6a5b ldr r3, [r3, #36] @ 0x24 800a142: 4a19 ldr r2, [pc, #100] @ (800a1a8 ) 800a144: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 800a148: 461a mov r2, r3 800a14a: 6bfb ldr r3, [r7, #60] @ 0x3c 800a14c: fbb3 f3f2 udiv r3, r3, r2 800a150: 005a lsls r2, r3, #1 800a152: 697b ldr r3, [r7, #20] 800a154: 685b ldr r3, [r3, #4] 800a156: 085b lsrs r3, r3, #1 800a158: 441a add r2, r3 800a15a: 697b ldr r3, [r7, #20] 800a15c: 685b ldr r3, [r3, #4] 800a15e: fbb2 f3f3 udiv r3, r2, r3 800a162: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 800a164: 6bbb ldr r3, [r7, #56] @ 0x38 800a166: 2b0f cmp r3, #15 800a168: d916 bls.n 800a198 800a16a: 6bbb ldr r3, [r7, #56] @ 0x38 800a16c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800a170: d212 bcs.n 800a198 { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 800a172: 6bbb ldr r3, [r7, #56] @ 0x38 800a174: b29b uxth r3, r3 800a176: f023 030f bic.w r3, r3, #15 800a17a: 86fb strh r3, [r7, #54] @ 0x36 brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 800a17c: 6bbb ldr r3, [r7, #56] @ 0x38 800a17e: 085b lsrs r3, r3, #1 800a180: b29b uxth r3, r3 800a182: f003 0307 and.w r3, r3, #7 800a186: b29a uxth r2, r3 800a188: 8efb ldrh r3, [r7, #54] @ 0x36 800a18a: 4313 orrs r3, r2 800a18c: 86fb strh r3, [r7, #54] @ 0x36 huart->Instance->BRR = brrtemp; 800a18e: 697b ldr r3, [r7, #20] 800a190: 681b ldr r3, [r3, #0] 800a192: 8efa ldrh r2, [r7, #54] @ 0x36 800a194: 60da str r2, [r3, #12] 800a196: e0b9 b.n 800a30c } else { ret = HAL_ERROR; 800a198: 2301 movs r3, #1 800a19a: f887 3042 strb.w r3, [r7, #66] @ 0x42 800a19e: e0b5 b.n 800a30c 800a1a0: 03d09000 .word 0x03d09000 800a1a4: 003d0900 .word 0x003d0900 800a1a8: 0800aacc .word 0x0800aacc 800a1ac: 58024400 .word 0x58024400 } } } else { switch (clocksource) 800a1b0: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 800a1b4: 2b20 cmp r3, #32 800a1b6: dc49 bgt.n 800a24c 800a1b8: 2b00 cmp r3, #0 800a1ba: db7c blt.n 800a2b6 800a1bc: 2b20 cmp r3, #32 800a1be: d87a bhi.n 800a2b6 800a1c0: a201 add r2, pc, #4 @ (adr r2, 800a1c8 ) 800a1c2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800a1c6: bf00 nop 800a1c8: 0800a253 .word 0x0800a253 800a1cc: 0800a25b .word 0x0800a25b 800a1d0: 0800a2b7 .word 0x0800a2b7 800a1d4: 0800a2b7 .word 0x0800a2b7 800a1d8: 0800a263 .word 0x0800a263 800a1dc: 0800a2b7 .word 0x0800a2b7 800a1e0: 0800a2b7 .word 0x0800a2b7 800a1e4: 0800a2b7 .word 0x0800a2b7 800a1e8: 0800a273 .word 0x0800a273 800a1ec: 0800a2b7 .word 0x0800a2b7 800a1f0: 0800a2b7 .word 0x0800a2b7 800a1f4: 0800a2b7 .word 0x0800a2b7 800a1f8: 0800a2b7 .word 0x0800a2b7 800a1fc: 0800a2b7 .word 0x0800a2b7 800a200: 0800a2b7 .word 0x0800a2b7 800a204: 0800a2b7 .word 0x0800a2b7 800a208: 0800a283 .word 0x0800a283 800a20c: 0800a2b7 .word 0x0800a2b7 800a210: 0800a2b7 .word 0x0800a2b7 800a214: 0800a2b7 .word 0x0800a2b7 800a218: 0800a2b7 .word 0x0800a2b7 800a21c: 0800a2b7 .word 0x0800a2b7 800a220: 0800a2b7 .word 0x0800a2b7 800a224: 0800a2b7 .word 0x0800a2b7 800a228: 0800a2b7 .word 0x0800a2b7 800a22c: 0800a2b7 .word 0x0800a2b7 800a230: 0800a2b7 .word 0x0800a2b7 800a234: 0800a2b7 .word 0x0800a2b7 800a238: 0800a2b7 .word 0x0800a2b7 800a23c: 0800a2b7 .word 0x0800a2b7 800a240: 0800a2b7 .word 0x0800a2b7 800a244: 0800a2b7 .word 0x0800a2b7 800a248: 0800a2a9 .word 0x0800a2a9 800a24c: 2b40 cmp r3, #64 @ 0x40 800a24e: d02e beq.n 800a2ae 800a250: e031 b.n 800a2b6 { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 800a252: f7fb fec5 bl 8005fe0 800a256: 63f8 str r0, [r7, #60] @ 0x3c break; 800a258: e033 b.n 800a2c2 case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 800a25a: f7fb fed7 bl 800600c 800a25e: 63f8 str r0, [r7, #60] @ 0x3c break; 800a260: e02f b.n 800a2c2 case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800a262: f107 0324 add.w r3, r7, #36 @ 0x24 800a266: 4618 mov r0, r3 800a268: f7fd fe86 bl 8007f78 pclk = pll2_clocks.PLL2_Q_Frequency; 800a26c: 6abb ldr r3, [r7, #40] @ 0x28 800a26e: 63fb str r3, [r7, #60] @ 0x3c break; 800a270: e027 b.n 800a2c2 case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800a272: f107 0318 add.w r3, r7, #24 800a276: 4618 mov r0, r3 800a278: f7fd ffd2 bl 8008220 pclk = pll3_clocks.PLL3_Q_Frequency; 800a27c: 69fb ldr r3, [r7, #28] 800a27e: 63fb str r3, [r7, #60] @ 0x3c break; 800a280: e01f b.n 800a2c2 case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800a282: 4b2d ldr r3, [pc, #180] @ (800a338 ) 800a284: 681b ldr r3, [r3, #0] 800a286: f003 0320 and.w r3, r3, #32 800a28a: 2b00 cmp r3, #0 800a28c: d009 beq.n 800a2a2 { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 800a28e: 4b2a ldr r3, [pc, #168] @ (800a338 ) 800a290: 681b ldr r3, [r3, #0] 800a292: 08db lsrs r3, r3, #3 800a294: f003 0303 and.w r3, r3, #3 800a298: 4a28 ldr r2, [pc, #160] @ (800a33c ) 800a29a: fa22 f303 lsr.w r3, r2, r3 800a29e: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 800a2a0: e00f b.n 800a2c2 pclk = (uint32_t) HSI_VALUE; 800a2a2: 4b26 ldr r3, [pc, #152] @ (800a33c ) 800a2a4: 63fb str r3, [r7, #60] @ 0x3c break; 800a2a6: e00c b.n 800a2c2 case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 800a2a8: 4b25 ldr r3, [pc, #148] @ (800a340 ) 800a2aa: 63fb str r3, [r7, #60] @ 0x3c break; 800a2ac: e009 b.n 800a2c2 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 800a2ae: f44f 4300 mov.w r3, #32768 @ 0x8000 800a2b2: 63fb str r3, [r7, #60] @ 0x3c break; 800a2b4: e005 b.n 800a2c2 default: pclk = 0U; 800a2b6: 2300 movs r3, #0 800a2b8: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 800a2ba: 2301 movs r3, #1 800a2bc: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 800a2c0: bf00 nop } if (pclk != 0U) 800a2c2: 6bfb ldr r3, [r7, #60] @ 0x3c 800a2c4: 2b00 cmp r3, #0 800a2c6: d021 beq.n 800a30c { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 800a2c8: 697b ldr r3, [r7, #20] 800a2ca: 6a5b ldr r3, [r3, #36] @ 0x24 800a2cc: 4a1d ldr r2, [pc, #116] @ (800a344 ) 800a2ce: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 800a2d2: 461a mov r2, r3 800a2d4: 6bfb ldr r3, [r7, #60] @ 0x3c 800a2d6: fbb3 f2f2 udiv r2, r3, r2 800a2da: 697b ldr r3, [r7, #20] 800a2dc: 685b ldr r3, [r3, #4] 800a2de: 085b lsrs r3, r3, #1 800a2e0: 441a add r2, r3 800a2e2: 697b ldr r3, [r7, #20] 800a2e4: 685b ldr r3, [r3, #4] 800a2e6: fbb2 f3f3 udiv r3, r2, r3 800a2ea: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 800a2ec: 6bbb ldr r3, [r7, #56] @ 0x38 800a2ee: 2b0f cmp r3, #15 800a2f0: d909 bls.n 800a306 800a2f2: 6bbb ldr r3, [r7, #56] @ 0x38 800a2f4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800a2f8: d205 bcs.n 800a306 { huart->Instance->BRR = (uint16_t)usartdiv; 800a2fa: 6bbb ldr r3, [r7, #56] @ 0x38 800a2fc: b29a uxth r2, r3 800a2fe: 697b ldr r3, [r7, #20] 800a300: 681b ldr r3, [r3, #0] 800a302: 60da str r2, [r3, #12] 800a304: e002 b.n 800a30c } else { ret = HAL_ERROR; 800a306: 2301 movs r3, #1 800a308: f887 3042 strb.w r3, [r7, #66] @ 0x42 } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; 800a30c: 697b ldr r3, [r7, #20] 800a30e: 2201 movs r2, #1 800a310: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1; 800a314: 697b ldr r3, [r7, #20] 800a316: 2201 movs r2, #1 800a318: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 /* Clear ISR function pointers */ huart->RxISR = NULL; 800a31c: 697b ldr r3, [r7, #20] 800a31e: 2200 movs r2, #0 800a320: 675a str r2, [r3, #116] @ 0x74 huart->TxISR = NULL; 800a322: 697b ldr r3, [r7, #20] 800a324: 2200 movs r2, #0 800a326: 679a str r2, [r3, #120] @ 0x78 return ret; 800a328: f897 3042 ldrb.w r3, [r7, #66] @ 0x42 } 800a32c: 4618 mov r0, r3 800a32e: 3748 adds r7, #72 @ 0x48 800a330: 46bd mov sp, r7 800a332: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 800a336: bf00 nop 800a338: 58024400 .word 0x58024400 800a33c: 03d09000 .word 0x03d09000 800a340: 003d0900 .word 0x003d0900 800a344: 0800aacc .word 0x0800aacc 0800a348 : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { 800a348: b480 push {r7} 800a34a: b083 sub sp, #12 800a34c: af00 add r7, sp, #0 800a34e: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 800a350: 687b ldr r3, [r7, #4] 800a352: 6a9b ldr r3, [r3, #40] @ 0x28 800a354: f003 0308 and.w r3, r3, #8 800a358: 2b00 cmp r3, #0 800a35a: d00a beq.n 800a372 { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); 800a35c: 687b ldr r3, [r7, #4] 800a35e: 681b ldr r3, [r3, #0] 800a360: 685b ldr r3, [r3, #4] 800a362: f423 4100 bic.w r1, r3, #32768 @ 0x8000 800a366: 687b ldr r3, [r7, #4] 800a368: 6b9a ldr r2, [r3, #56] @ 0x38 800a36a: 687b ldr r3, [r7, #4] 800a36c: 681b ldr r3, [r3, #0] 800a36e: 430a orrs r2, r1 800a370: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) 800a372: 687b ldr r3, [r7, #4] 800a374: 6a9b ldr r3, [r3, #40] @ 0x28 800a376: f003 0301 and.w r3, r3, #1 800a37a: 2b00 cmp r3, #0 800a37c: d00a beq.n 800a394 { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); 800a37e: 687b ldr r3, [r7, #4] 800a380: 681b ldr r3, [r3, #0] 800a382: 685b ldr r3, [r3, #4] 800a384: f423 3100 bic.w r1, r3, #131072 @ 0x20000 800a388: 687b ldr r3, [r7, #4] 800a38a: 6ada ldr r2, [r3, #44] @ 0x2c 800a38c: 687b ldr r3, [r7, #4] 800a38e: 681b ldr r3, [r3, #0] 800a390: 430a orrs r2, r1 800a392: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) 800a394: 687b ldr r3, [r7, #4] 800a396: 6a9b ldr r3, [r3, #40] @ 0x28 800a398: f003 0302 and.w r3, r3, #2 800a39c: 2b00 cmp r3, #0 800a39e: d00a beq.n 800a3b6 { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); 800a3a0: 687b ldr r3, [r7, #4] 800a3a2: 681b ldr r3, [r3, #0] 800a3a4: 685b ldr r3, [r3, #4] 800a3a6: f423 3180 bic.w r1, r3, #65536 @ 0x10000 800a3aa: 687b ldr r3, [r7, #4] 800a3ac: 6b1a ldr r2, [r3, #48] @ 0x30 800a3ae: 687b ldr r3, [r7, #4] 800a3b0: 681b ldr r3, [r3, #0] 800a3b2: 430a orrs r2, r1 800a3b4: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) 800a3b6: 687b ldr r3, [r7, #4] 800a3b8: 6a9b ldr r3, [r3, #40] @ 0x28 800a3ba: f003 0304 and.w r3, r3, #4 800a3be: 2b00 cmp r3, #0 800a3c0: d00a beq.n 800a3d8 { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); 800a3c2: 687b ldr r3, [r7, #4] 800a3c4: 681b ldr r3, [r3, #0] 800a3c6: 685b ldr r3, [r3, #4] 800a3c8: f423 2180 bic.w r1, r3, #262144 @ 0x40000 800a3cc: 687b ldr r3, [r7, #4] 800a3ce: 6b5a ldr r2, [r3, #52] @ 0x34 800a3d0: 687b ldr r3, [r7, #4] 800a3d2: 681b ldr r3, [r3, #0] 800a3d4: 430a orrs r2, r1 800a3d6: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) 800a3d8: 687b ldr r3, [r7, #4] 800a3da: 6a9b ldr r3, [r3, #40] @ 0x28 800a3dc: f003 0310 and.w r3, r3, #16 800a3e0: 2b00 cmp r3, #0 800a3e2: d00a beq.n 800a3fa { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); 800a3e4: 687b ldr r3, [r7, #4] 800a3e6: 681b ldr r3, [r3, #0] 800a3e8: 689b ldr r3, [r3, #8] 800a3ea: f423 5180 bic.w r1, r3, #4096 @ 0x1000 800a3ee: 687b ldr r3, [r7, #4] 800a3f0: 6bda ldr r2, [r3, #60] @ 0x3c 800a3f2: 687b ldr r3, [r7, #4] 800a3f4: 681b ldr r3, [r3, #0] 800a3f6: 430a orrs r2, r1 800a3f8: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) 800a3fa: 687b ldr r3, [r7, #4] 800a3fc: 6a9b ldr r3, [r3, #40] @ 0x28 800a3fe: f003 0320 and.w r3, r3, #32 800a402: 2b00 cmp r3, #0 800a404: d00a beq.n 800a41c { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); 800a406: 687b ldr r3, [r7, #4] 800a408: 681b ldr r3, [r3, #0] 800a40a: 689b ldr r3, [r3, #8] 800a40c: f423 5100 bic.w r1, r3, #8192 @ 0x2000 800a410: 687b ldr r3, [r7, #4] 800a412: 6c1a ldr r2, [r3, #64] @ 0x40 800a414: 687b ldr r3, [r7, #4] 800a416: 681b ldr r3, [r3, #0] 800a418: 430a orrs r2, r1 800a41a: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) 800a41c: 687b ldr r3, [r7, #4] 800a41e: 6a9b ldr r3, [r3, #40] @ 0x28 800a420: f003 0340 and.w r3, r3, #64 @ 0x40 800a424: 2b00 cmp r3, #0 800a426: d01a beq.n 800a45e { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 800a428: 687b ldr r3, [r7, #4] 800a42a: 681b ldr r3, [r3, #0] 800a42c: 685b ldr r3, [r3, #4] 800a42e: f423 1180 bic.w r1, r3, #1048576 @ 0x100000 800a432: 687b ldr r3, [r7, #4] 800a434: 6c5a ldr r2, [r3, #68] @ 0x44 800a436: 687b ldr r3, [r7, #4] 800a438: 681b ldr r3, [r3, #0] 800a43a: 430a orrs r2, r1 800a43c: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 800a43e: 687b ldr r3, [r7, #4] 800a440: 6c5b ldr r3, [r3, #68] @ 0x44 800a442: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800a446: d10a bne.n 800a45e { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); 800a448: 687b ldr r3, [r7, #4] 800a44a: 681b ldr r3, [r3, #0] 800a44c: 685b ldr r3, [r3, #4] 800a44e: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000 800a452: 687b ldr r3, [r7, #4] 800a454: 6c9a ldr r2, [r3, #72] @ 0x48 800a456: 687b ldr r3, [r7, #4] 800a458: 681b ldr r3, [r3, #0] 800a45a: 430a orrs r2, r1 800a45c: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) 800a45e: 687b ldr r3, [r7, #4] 800a460: 6a9b ldr r3, [r3, #40] @ 0x28 800a462: f003 0380 and.w r3, r3, #128 @ 0x80 800a466: 2b00 cmp r3, #0 800a468: d00a beq.n 800a480 { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); 800a46a: 687b ldr r3, [r7, #4] 800a46c: 681b ldr r3, [r3, #0] 800a46e: 685b ldr r3, [r3, #4] 800a470: f423 2100 bic.w r1, r3, #524288 @ 0x80000 800a474: 687b ldr r3, [r7, #4] 800a476: 6cda ldr r2, [r3, #76] @ 0x4c 800a478: 687b ldr r3, [r7, #4] 800a47a: 681b ldr r3, [r3, #0] 800a47c: 430a orrs r2, r1 800a47e: 605a str r2, [r3, #4] } } 800a480: bf00 nop 800a482: 370c adds r7, #12 800a484: 46bd mov sp, r7 800a486: f85d 7b04 ldr.w r7, [sp], #4 800a48a: 4770 bx lr 0800a48c : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { 800a48c: b580 push {r7, lr} 800a48e: b098 sub sp, #96 @ 0x60 800a490: af02 add r7, sp, #8 800a492: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 800a494: 687b ldr r3, [r7, #4] 800a496: 2200 movs r2, #0 800a498: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 800a49c: f7f7 f922 bl 80016e4 800a4a0: 6578 str r0, [r7, #84] @ 0x54 /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 800a4a2: 687b ldr r3, [r7, #4] 800a4a4: 681b ldr r3, [r3, #0] 800a4a6: 681b ldr r3, [r3, #0] 800a4a8: f003 0308 and.w r3, r3, #8 800a4ac: 2b08 cmp r3, #8 800a4ae: d12f bne.n 800a510 { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 800a4b0: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 800a4b4: 9300 str r3, [sp, #0] 800a4b6: 6d7b ldr r3, [r7, #84] @ 0x54 800a4b8: 2200 movs r2, #0 800a4ba: f44f 1100 mov.w r1, #2097152 @ 0x200000 800a4be: 6878 ldr r0, [r7, #4] 800a4c0: f000 f88e bl 800a5e0 800a4c4: 4603 mov r3, r0 800a4c6: 2b00 cmp r3, #0 800a4c8: d022 beq.n 800a510 { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); 800a4ca: 687b ldr r3, [r7, #4] 800a4cc: 681b ldr r3, [r3, #0] 800a4ce: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a4d0: 6bbb ldr r3, [r7, #56] @ 0x38 800a4d2: e853 3f00 ldrex r3, [r3] 800a4d6: 637b str r3, [r7, #52] @ 0x34 return(result); 800a4d8: 6b7b ldr r3, [r7, #52] @ 0x34 800a4da: f023 0380 bic.w r3, r3, #128 @ 0x80 800a4de: 653b str r3, [r7, #80] @ 0x50 800a4e0: 687b ldr r3, [r7, #4] 800a4e2: 681b ldr r3, [r3, #0] 800a4e4: 461a mov r2, r3 800a4e6: 6d3b ldr r3, [r7, #80] @ 0x50 800a4e8: 647b str r3, [r7, #68] @ 0x44 800a4ea: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a4ec: 6c39 ldr r1, [r7, #64] @ 0x40 800a4ee: 6c7a ldr r2, [r7, #68] @ 0x44 800a4f0: e841 2300 strex r3, r2, [r1] 800a4f4: 63fb str r3, [r7, #60] @ 0x3c return(result); 800a4f6: 6bfb ldr r3, [r7, #60] @ 0x3c 800a4f8: 2b00 cmp r3, #0 800a4fa: d1e6 bne.n 800a4ca huart->gState = HAL_UART_STATE_READY; 800a4fc: 687b ldr r3, [r7, #4] 800a4fe: 2220 movs r2, #32 800a500: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UNLOCK(huart); 800a504: 687b ldr r3, [r7, #4] 800a506: 2200 movs r2, #0 800a508: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 800a50c: 2303 movs r3, #3 800a50e: e063 b.n 800a5d8 } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 800a510: 687b ldr r3, [r7, #4] 800a512: 681b ldr r3, [r3, #0] 800a514: 681b ldr r3, [r3, #0] 800a516: f003 0304 and.w r3, r3, #4 800a51a: 2b04 cmp r3, #4 800a51c: d149 bne.n 800a5b2 { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 800a51e: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 800a522: 9300 str r3, [sp, #0] 800a524: 6d7b ldr r3, [r7, #84] @ 0x54 800a526: 2200 movs r2, #0 800a528: f44f 0180 mov.w r1, #4194304 @ 0x400000 800a52c: 6878 ldr r0, [r7, #4] 800a52e: f000 f857 bl 800a5e0 800a532: 4603 mov r3, r0 800a534: 2b00 cmp r3, #0 800a536: d03c beq.n 800a5b2 { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 800a538: 687b ldr r3, [r7, #4] 800a53a: 681b ldr r3, [r3, #0] 800a53c: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a53e: 6a7b ldr r3, [r7, #36] @ 0x24 800a540: e853 3f00 ldrex r3, [r3] 800a544: 623b str r3, [r7, #32] return(result); 800a546: 6a3b ldr r3, [r7, #32] 800a548: f423 7390 bic.w r3, r3, #288 @ 0x120 800a54c: 64fb str r3, [r7, #76] @ 0x4c 800a54e: 687b ldr r3, [r7, #4] 800a550: 681b ldr r3, [r3, #0] 800a552: 461a mov r2, r3 800a554: 6cfb ldr r3, [r7, #76] @ 0x4c 800a556: 633b str r3, [r7, #48] @ 0x30 800a558: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a55a: 6af9 ldr r1, [r7, #44] @ 0x2c 800a55c: 6b3a ldr r2, [r7, #48] @ 0x30 800a55e: e841 2300 strex r3, r2, [r1] 800a562: 62bb str r3, [r7, #40] @ 0x28 return(result); 800a564: 6abb ldr r3, [r7, #40] @ 0x28 800a566: 2b00 cmp r3, #0 800a568: d1e6 bne.n 800a538 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800a56a: 687b ldr r3, [r7, #4] 800a56c: 681b ldr r3, [r3, #0] 800a56e: 3308 adds r3, #8 800a570: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a572: 693b ldr r3, [r7, #16] 800a574: e853 3f00 ldrex r3, [r3] 800a578: 60fb str r3, [r7, #12] return(result); 800a57a: 68fb ldr r3, [r7, #12] 800a57c: f023 0301 bic.w r3, r3, #1 800a580: 64bb str r3, [r7, #72] @ 0x48 800a582: 687b ldr r3, [r7, #4] 800a584: 681b ldr r3, [r3, #0] 800a586: 3308 adds r3, #8 800a588: 6cba ldr r2, [r7, #72] @ 0x48 800a58a: 61fa str r2, [r7, #28] 800a58c: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a58e: 69b9 ldr r1, [r7, #24] 800a590: 69fa ldr r2, [r7, #28] 800a592: e841 2300 strex r3, r2, [r1] 800a596: 617b str r3, [r7, #20] return(result); 800a598: 697b ldr r3, [r7, #20] 800a59a: 2b00 cmp r3, #0 800a59c: d1e5 bne.n 800a56a huart->RxState = HAL_UART_STATE_READY; 800a59e: 687b ldr r3, [r7, #4] 800a5a0: 2220 movs r2, #32 800a5a2: f8c3 208c str.w r2, [r3, #140] @ 0x8c __HAL_UNLOCK(huart); 800a5a6: 687b ldr r3, [r7, #4] 800a5a8: 2200 movs r2, #0 800a5aa: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 800a5ae: 2303 movs r3, #3 800a5b0: e012 b.n 800a5d8 } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; 800a5b2: 687b ldr r3, [r7, #4] 800a5b4: 2220 movs r2, #32 800a5b6: f8c3 2088 str.w r2, [r3, #136] @ 0x88 huart->RxState = HAL_UART_STATE_READY; 800a5ba: 687b ldr r3, [r7, #4] 800a5bc: 2220 movs r2, #32 800a5be: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800a5c2: 687b ldr r3, [r7, #4] 800a5c4: 2200 movs r2, #0 800a5c6: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 800a5c8: 687b ldr r3, [r7, #4] 800a5ca: 2200 movs r2, #0 800a5cc: 671a str r2, [r3, #112] @ 0x70 __HAL_UNLOCK(huart); 800a5ce: 687b ldr r3, [r7, #4] 800a5d0: 2200 movs r2, #0 800a5d2: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 800a5d6: 2300 movs r3, #0 } 800a5d8: 4618 mov r0, r3 800a5da: 3758 adds r7, #88 @ 0x58 800a5dc: 46bd mov sp, r7 800a5de: bd80 pop {r7, pc} 0800a5e0 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 800a5e0: b580 push {r7, lr} 800a5e2: b084 sub sp, #16 800a5e4: af00 add r7, sp, #0 800a5e6: 60f8 str r0, [r7, #12] 800a5e8: 60b9 str r1, [r7, #8] 800a5ea: 603b str r3, [r7, #0] 800a5ec: 4613 mov r3, r2 800a5ee: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 800a5f0: e04f b.n 800a692 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 800a5f2: 69bb ldr r3, [r7, #24] 800a5f4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800a5f8: d04b beq.n 800a692 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 800a5fa: f7f7 f873 bl 80016e4 800a5fe: 4602 mov r2, r0 800a600: 683b ldr r3, [r7, #0] 800a602: 1ad3 subs r3, r2, r3 800a604: 69ba ldr r2, [r7, #24] 800a606: 429a cmp r2, r3 800a608: d302 bcc.n 800a610 800a60a: 69bb ldr r3, [r7, #24] 800a60c: 2b00 cmp r3, #0 800a60e: d101 bne.n 800a614 { return HAL_TIMEOUT; 800a610: 2303 movs r3, #3 800a612: e04e b.n 800a6b2 } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 800a614: 68fb ldr r3, [r7, #12] 800a616: 681b ldr r3, [r3, #0] 800a618: 681b ldr r3, [r3, #0] 800a61a: f003 0304 and.w r3, r3, #4 800a61e: 2b00 cmp r3, #0 800a620: d037 beq.n 800a692 800a622: 68bb ldr r3, [r7, #8] 800a624: 2b80 cmp r3, #128 @ 0x80 800a626: d034 beq.n 800a692 800a628: 68bb ldr r3, [r7, #8] 800a62a: 2b40 cmp r3, #64 @ 0x40 800a62c: d031 beq.n 800a692 { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 800a62e: 68fb ldr r3, [r7, #12] 800a630: 681b ldr r3, [r3, #0] 800a632: 69db ldr r3, [r3, #28] 800a634: f003 0308 and.w r3, r3, #8 800a638: 2b08 cmp r3, #8 800a63a: d110 bne.n 800a65e { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 800a63c: 68fb ldr r3, [r7, #12] 800a63e: 681b ldr r3, [r3, #0] 800a640: 2208 movs r2, #8 800a642: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 800a644: 68f8 ldr r0, [r7, #12] 800a646: f000 f839 bl 800a6bc huart->ErrorCode = HAL_UART_ERROR_ORE; 800a64a: 68fb ldr r3, [r7, #12] 800a64c: 2208 movs r2, #8 800a64e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 800a652: 68fb ldr r3, [r7, #12] 800a654: 2200 movs r2, #0 800a656: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_ERROR; 800a65a: 2301 movs r3, #1 800a65c: e029 b.n 800a6b2 } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 800a65e: 68fb ldr r3, [r7, #12] 800a660: 681b ldr r3, [r3, #0] 800a662: 69db ldr r3, [r3, #28] 800a664: f403 6300 and.w r3, r3, #2048 @ 0x800 800a668: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800a66c: d111 bne.n 800a692 { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 800a66e: 68fb ldr r3, [r7, #12] 800a670: 681b ldr r3, [r3, #0] 800a672: f44f 6200 mov.w r2, #2048 @ 0x800 800a676: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 800a678: 68f8 ldr r0, [r7, #12] 800a67a: f000 f81f bl 800a6bc huart->ErrorCode = HAL_UART_ERROR_RTO; 800a67e: 68fb ldr r3, [r7, #12] 800a680: 2220 movs r2, #32 800a682: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 800a686: 68fb ldr r3, [r7, #12] 800a688: 2200 movs r2, #0 800a68a: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_TIMEOUT; 800a68e: 2303 movs r3, #3 800a690: e00f b.n 800a6b2 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 800a692: 68fb ldr r3, [r7, #12] 800a694: 681b ldr r3, [r3, #0] 800a696: 69da ldr r2, [r3, #28] 800a698: 68bb ldr r3, [r7, #8] 800a69a: 4013 ands r3, r2 800a69c: 68ba ldr r2, [r7, #8] 800a69e: 429a cmp r2, r3 800a6a0: bf0c ite eq 800a6a2: 2301 moveq r3, #1 800a6a4: 2300 movne r3, #0 800a6a6: b2db uxtb r3, r3 800a6a8: 461a mov r2, r3 800a6aa: 79fb ldrb r3, [r7, #7] 800a6ac: 429a cmp r2, r3 800a6ae: d0a0 beq.n 800a5f2 } } } } return HAL_OK; 800a6b0: 2300 movs r3, #0 } 800a6b2: 4618 mov r0, r3 800a6b4: 3710 adds r7, #16 800a6b6: 46bd mov sp, r7 800a6b8: bd80 pop {r7, pc} ... 0800a6bc : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 800a6bc: b480 push {r7} 800a6be: b095 sub sp, #84 @ 0x54 800a6c0: af00 add r7, sp, #0 800a6c2: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 800a6c4: 687b ldr r3, [r7, #4] 800a6c6: 681b ldr r3, [r3, #0] 800a6c8: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a6ca: 6b7b ldr r3, [r7, #52] @ 0x34 800a6cc: e853 3f00 ldrex r3, [r3] 800a6d0: 633b str r3, [r7, #48] @ 0x30 return(result); 800a6d2: 6b3b ldr r3, [r7, #48] @ 0x30 800a6d4: f423 7390 bic.w r3, r3, #288 @ 0x120 800a6d8: 64fb str r3, [r7, #76] @ 0x4c 800a6da: 687b ldr r3, [r7, #4] 800a6dc: 681b ldr r3, [r3, #0] 800a6de: 461a mov r2, r3 800a6e0: 6cfb ldr r3, [r7, #76] @ 0x4c 800a6e2: 643b str r3, [r7, #64] @ 0x40 800a6e4: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a6e6: 6bf9 ldr r1, [r7, #60] @ 0x3c 800a6e8: 6c3a ldr r2, [r7, #64] @ 0x40 800a6ea: e841 2300 strex r3, r2, [r1] 800a6ee: 63bb str r3, [r7, #56] @ 0x38 return(result); 800a6f0: 6bbb ldr r3, [r7, #56] @ 0x38 800a6f2: 2b00 cmp r3, #0 800a6f4: d1e6 bne.n 800a6c4 ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 800a6f6: 687b ldr r3, [r7, #4] 800a6f8: 681b ldr r3, [r3, #0] 800a6fa: 3308 adds r3, #8 800a6fc: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a6fe: 6a3b ldr r3, [r7, #32] 800a700: e853 3f00 ldrex r3, [r3] 800a704: 61fb str r3, [r7, #28] return(result); 800a706: 69fa ldr r2, [r7, #28] 800a708: 4b1e ldr r3, [pc, #120] @ (800a784 ) 800a70a: 4013 ands r3, r2 800a70c: 64bb str r3, [r7, #72] @ 0x48 800a70e: 687b ldr r3, [r7, #4] 800a710: 681b ldr r3, [r3, #0] 800a712: 3308 adds r3, #8 800a714: 6cba ldr r2, [r7, #72] @ 0x48 800a716: 62fa str r2, [r7, #44] @ 0x2c 800a718: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a71a: 6ab9 ldr r1, [r7, #40] @ 0x28 800a71c: 6afa ldr r2, [r7, #44] @ 0x2c 800a71e: e841 2300 strex r3, r2, [r1] 800a722: 627b str r3, [r7, #36] @ 0x24 return(result); 800a724: 6a7b ldr r3, [r7, #36] @ 0x24 800a726: 2b00 cmp r3, #0 800a728: d1e5 bne.n 800a6f6 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800a72a: 687b ldr r3, [r7, #4] 800a72c: 6edb ldr r3, [r3, #108] @ 0x6c 800a72e: 2b01 cmp r3, #1 800a730: d118 bne.n 800a764 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800a732: 687b ldr r3, [r7, #4] 800a734: 681b ldr r3, [r3, #0] 800a736: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a738: 68fb ldr r3, [r7, #12] 800a73a: e853 3f00 ldrex r3, [r3] 800a73e: 60bb str r3, [r7, #8] return(result); 800a740: 68bb ldr r3, [r7, #8] 800a742: f023 0310 bic.w r3, r3, #16 800a746: 647b str r3, [r7, #68] @ 0x44 800a748: 687b ldr r3, [r7, #4] 800a74a: 681b ldr r3, [r3, #0] 800a74c: 461a mov r2, r3 800a74e: 6c7b ldr r3, [r7, #68] @ 0x44 800a750: 61bb str r3, [r7, #24] 800a752: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a754: 6979 ldr r1, [r7, #20] 800a756: 69ba ldr r2, [r7, #24] 800a758: e841 2300 strex r3, r2, [r1] 800a75c: 613b str r3, [r7, #16] return(result); 800a75e: 693b ldr r3, [r7, #16] 800a760: 2b00 cmp r3, #0 800a762: d1e6 bne.n 800a732 } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800a764: 687b ldr r3, [r7, #4] 800a766: 2220 movs r2, #32 800a768: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800a76c: 687b ldr r3, [r7, #4] 800a76e: 2200 movs r2, #0 800a770: 66da str r2, [r3, #108] @ 0x6c /* Reset RxIsr function pointer */ huart->RxISR = NULL; 800a772: 687b ldr r3, [r7, #4] 800a774: 2200 movs r2, #0 800a776: 675a str r2, [r3, #116] @ 0x74 } 800a778: bf00 nop 800a77a: 3754 adds r7, #84 @ 0x54 800a77c: 46bd mov sp, r7 800a77e: f85d 7b04 ldr.w r7, [sp], #4 800a782: 4770 bx lr 800a784: effffffe .word 0xeffffffe 0800a788 : * (To be called at end of DMA Abort procedure following error occurrence). * @param hdma DMA handle. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 800a788: b580 push {r7, lr} 800a78a: b084 sub sp, #16 800a78c: af00 add r7, sp, #0 800a78e: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 800a790: 687b ldr r3, [r7, #4] 800a792: 6b9b ldr r3, [r3, #56] @ 0x38 800a794: 60fb str r3, [r7, #12] huart->RxXferCount = 0U; 800a796: 68fb ldr r3, [r7, #12] 800a798: 2200 movs r2, #0 800a79a: f8a3 205e strh.w r2, [r3, #94] @ 0x5e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 800a79e: 68f8 ldr r0, [r7, #12] 800a7a0: f7ff f854 bl 800984c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 800a7a4: bf00 nop 800a7a6: 3710 adds r7, #16 800a7a8: 46bd mov sp, r7 800a7aa: bd80 pop {r7, pc} 0800a7ac : * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 800a7ac: b580 push {r7, lr} 800a7ae: b088 sub sp, #32 800a7b0: af00 add r7, sp, #0 800a7b2: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); 800a7b4: 687b ldr r3, [r7, #4] 800a7b6: 681b ldr r3, [r3, #0] 800a7b8: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a7ba: 68fb ldr r3, [r7, #12] 800a7bc: e853 3f00 ldrex r3, [r3] 800a7c0: 60bb str r3, [r7, #8] return(result); 800a7c2: 68bb ldr r3, [r7, #8] 800a7c4: f023 0340 bic.w r3, r3, #64 @ 0x40 800a7c8: 61fb str r3, [r7, #28] 800a7ca: 687b ldr r3, [r7, #4] 800a7cc: 681b ldr r3, [r3, #0] 800a7ce: 461a mov r2, r3 800a7d0: 69fb ldr r3, [r7, #28] 800a7d2: 61bb str r3, [r7, #24] 800a7d4: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a7d6: 6979 ldr r1, [r7, #20] 800a7d8: 69ba ldr r2, [r7, #24] 800a7da: e841 2300 strex r3, r2, [r1] 800a7de: 613b str r3, [r7, #16] return(result); 800a7e0: 693b ldr r3, [r7, #16] 800a7e2: 2b00 cmp r3, #0 800a7e4: d1e6 bne.n 800a7b4 /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 800a7e6: 687b ldr r3, [r7, #4] 800a7e8: 2220 movs r2, #32 800a7ea: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Cleat TxISR function pointer */ huart->TxISR = NULL; 800a7ee: 687b ldr r3, [r7, #4] 800a7f0: 2200 movs r2, #0 800a7f2: 679a str r2, [r3, #120] @ 0x78 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 800a7f4: 6878 ldr r0, [r7, #4] 800a7f6: f7ff f81f bl 8009838 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 800a7fa: bf00 nop 800a7fc: 3720 adds r7, #32 800a7fe: 46bd mov sp, r7 800a800: bd80 pop {r7, pc} 0800a802 : * @brief UART wakeup from Stop mode callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) { 800a802: b480 push {r7} 800a804: b083 sub sp, #12 800a806: af00 add r7, sp, #0 800a808: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_WakeupCallback can be implemented in the user file. */ } 800a80a: bf00 nop 800a80c: 370c adds r7, #12 800a80e: 46bd mov sp, r7 800a810: f85d 7b04 ldr.w r7, [sp], #4 800a814: 4770 bx lr 0800a816 : * @brief UART RX Fifo full callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) { 800a816: b480 push {r7} 800a818: b083 sub sp, #12 800a81a: af00 add r7, sp, #0 800a81c: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. */ } 800a81e: bf00 nop 800a820: 370c adds r7, #12 800a822: 46bd mov sp, r7 800a824: f85d 7b04 ldr.w r7, [sp], #4 800a828: 4770 bx lr 0800a82a : * @brief UART TX Fifo empty callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) { 800a82a: b480 push {r7} 800a82c: b083 sub sp, #12 800a82e: af00 add r7, sp, #0 800a830: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. */ } 800a832: bf00 nop 800a834: 370c adds r7, #12 800a836: 46bd mov sp, r7 800a838: f85d 7b04 ldr.w r7, [sp], #4 800a83c: 4770 bx lr 0800a83e : * @brief Disable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { 800a83e: b480 push {r7} 800a840: b085 sub sp, #20 800a842: af00 add r7, sp, #0 800a844: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); 800a846: 687b ldr r3, [r7, #4] 800a848: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 800a84c: 2b01 cmp r3, #1 800a84e: d101 bne.n 800a854 800a850: 2302 movs r3, #2 800a852: e027 b.n 800a8a4 800a854: 687b ldr r3, [r7, #4] 800a856: 2201 movs r2, #1 800a858: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 800a85c: 687b ldr r3, [r7, #4] 800a85e: 2224 movs r2, #36 @ 0x24 800a860: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 800a864: 687b ldr r3, [r7, #4] 800a866: 681b ldr r3, [r3, #0] 800a868: 681b ldr r3, [r3, #0] 800a86a: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 800a86c: 687b ldr r3, [r7, #4] 800a86e: 681b ldr r3, [r3, #0] 800a870: 681a ldr r2, [r3, #0] 800a872: 687b ldr r3, [r7, #4] 800a874: 681b ldr r3, [r3, #0] 800a876: f022 0201 bic.w r2, r2, #1 800a87a: 601a str r2, [r3, #0] /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); 800a87c: 68fb ldr r3, [r7, #12] 800a87e: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000 800a882: 60fb str r3, [r7, #12] huart->FifoMode = UART_FIFOMODE_DISABLE; 800a884: 687b ldr r3, [r7, #4] 800a886: 2200 movs r2, #0 800a888: 665a str r2, [r3, #100] @ 0x64 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 800a88a: 687b ldr r3, [r7, #4] 800a88c: 681b ldr r3, [r3, #0] 800a88e: 68fa ldr r2, [r7, #12] 800a890: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 800a892: 687b ldr r3, [r7, #4] 800a894: 2220 movs r2, #32 800a896: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 800a89a: 687b ldr r3, [r7, #4] 800a89c: 2200 movs r2, #0 800a89e: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 800a8a2: 2300 movs r3, #0 } 800a8a4: 4618 mov r0, r3 800a8a6: 3714 adds r7, #20 800a8a8: 46bd mov sp, r7 800a8aa: f85d 7b04 ldr.w r7, [sp], #4 800a8ae: 4770 bx lr 0800a8b0 : * @arg @ref UART_TXFIFO_THRESHOLD_7_8 * @arg @ref UART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 800a8b0: b580 push {r7, lr} 800a8b2: b084 sub sp, #16 800a8b4: af00 add r7, sp, #0 800a8b6: 6078 str r0, [r7, #4] 800a8b8: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 800a8ba: 687b ldr r3, [r7, #4] 800a8bc: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 800a8c0: 2b01 cmp r3, #1 800a8c2: d101 bne.n 800a8c8 800a8c4: 2302 movs r3, #2 800a8c6: e02d b.n 800a924 800a8c8: 687b ldr r3, [r7, #4] 800a8ca: 2201 movs r2, #1 800a8cc: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 800a8d0: 687b ldr r3, [r7, #4] 800a8d2: 2224 movs r2, #36 @ 0x24 800a8d4: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 800a8d8: 687b ldr r3, [r7, #4] 800a8da: 681b ldr r3, [r3, #0] 800a8dc: 681b ldr r3, [r3, #0] 800a8de: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 800a8e0: 687b ldr r3, [r7, #4] 800a8e2: 681b ldr r3, [r3, #0] 800a8e4: 681a ldr r2, [r3, #0] 800a8e6: 687b ldr r3, [r7, #4] 800a8e8: 681b ldr r3, [r3, #0] 800a8ea: f022 0201 bic.w r2, r2, #1 800a8ee: 601a str r2, [r3, #0] /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); 800a8f0: 687b ldr r3, [r7, #4] 800a8f2: 681b ldr r3, [r3, #0] 800a8f4: 689b ldr r3, [r3, #8] 800a8f6: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000 800a8fa: 687b ldr r3, [r7, #4] 800a8fc: 681b ldr r3, [r3, #0] 800a8fe: 683a ldr r2, [r7, #0] 800a900: 430a orrs r2, r1 800a902: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 800a904: 6878 ldr r0, [r7, #4] 800a906: f000 f84f bl 800a9a8 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 800a90a: 687b ldr r3, [r7, #4] 800a90c: 681b ldr r3, [r3, #0] 800a90e: 68fa ldr r2, [r7, #12] 800a910: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 800a912: 687b ldr r3, [r7, #4] 800a914: 2220 movs r2, #32 800a916: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 800a91a: 687b ldr r3, [r7, #4] 800a91c: 2200 movs r2, #0 800a91e: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 800a922: 2300 movs r3, #0 } 800a924: 4618 mov r0, r3 800a926: 3710 adds r7, #16 800a928: 46bd mov sp, r7 800a92a: bd80 pop {r7, pc} 0800a92c : * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 800a92c: b580 push {r7, lr} 800a92e: b084 sub sp, #16 800a930: af00 add r7, sp, #0 800a932: 6078 str r0, [r7, #4] 800a934: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 800a936: 687b ldr r3, [r7, #4] 800a938: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 800a93c: 2b01 cmp r3, #1 800a93e: d101 bne.n 800a944 800a940: 2302 movs r3, #2 800a942: e02d b.n 800a9a0 800a944: 687b ldr r3, [r7, #4] 800a946: 2201 movs r2, #1 800a948: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 800a94c: 687b ldr r3, [r7, #4] 800a94e: 2224 movs r2, #36 @ 0x24 800a950: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 800a954: 687b ldr r3, [r7, #4] 800a956: 681b ldr r3, [r3, #0] 800a958: 681b ldr r3, [r3, #0] 800a95a: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 800a95c: 687b ldr r3, [r7, #4] 800a95e: 681b ldr r3, [r3, #0] 800a960: 681a ldr r2, [r3, #0] 800a962: 687b ldr r3, [r7, #4] 800a964: 681b ldr r3, [r3, #0] 800a966: f022 0201 bic.w r2, r2, #1 800a96a: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); 800a96c: 687b ldr r3, [r7, #4] 800a96e: 681b ldr r3, [r3, #0] 800a970: 689b ldr r3, [r3, #8] 800a972: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000 800a976: 687b ldr r3, [r7, #4] 800a978: 681b ldr r3, [r3, #0] 800a97a: 683a ldr r2, [r7, #0] 800a97c: 430a orrs r2, r1 800a97e: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 800a980: 6878 ldr r0, [r7, #4] 800a982: f000 f811 bl 800a9a8 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 800a986: 687b ldr r3, [r7, #4] 800a988: 681b ldr r3, [r3, #0] 800a98a: 68fa ldr r2, [r7, #12] 800a98c: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 800a98e: 687b ldr r3, [r7, #4] 800a990: 2220 movs r2, #32 800a992: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 800a996: 687b ldr r3, [r7, #4] 800a998: 2200 movs r2, #0 800a99a: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 800a99e: 2300 movs r3, #0 } 800a9a0: 4618 mov r0, r3 800a9a2: 3710 adds r7, #16 800a9a4: 46bd mov sp, r7 800a9a6: bd80 pop {r7, pc} 0800a9a8 : * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { 800a9a8: b480 push {r7} 800a9aa: b085 sub sp, #20 800a9ac: af00 add r7, sp, #0 800a9ae: 6078 str r0, [r7, #4] uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) 800a9b0: 687b ldr r3, [r7, #4] 800a9b2: 6e5b ldr r3, [r3, #100] @ 0x64 800a9b4: 2b00 cmp r3, #0 800a9b6: d108 bne.n 800a9ca { huart->NbTxDataToProcess = 1U; 800a9b8: 687b ldr r3, [r7, #4] 800a9ba: 2201 movs r2, #1 800a9bc: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1U; 800a9c0: 687b ldr r3, [r7, #4] 800a9c2: 2201 movs r2, #1 800a9c4: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } 800a9c8: e031 b.n 800aa2e rx_fifo_depth = RX_FIFO_DEPTH; 800a9ca: 2310 movs r3, #16 800a9cc: 73fb strb r3, [r7, #15] tx_fifo_depth = TX_FIFO_DEPTH; 800a9ce: 2310 movs r3, #16 800a9d0: 73bb strb r3, [r7, #14] rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); 800a9d2: 687b ldr r3, [r7, #4] 800a9d4: 681b ldr r3, [r3, #0] 800a9d6: 689b ldr r3, [r3, #8] 800a9d8: 0e5b lsrs r3, r3, #25 800a9da: b2db uxtb r3, r3 800a9dc: f003 0307 and.w r3, r3, #7 800a9e0: 737b strb r3, [r7, #13] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 800a9e2: 687b ldr r3, [r7, #4] 800a9e4: 681b ldr r3, [r3, #0] 800a9e6: 689b ldr r3, [r3, #8] 800a9e8: 0f5b lsrs r3, r3, #29 800a9ea: b2db uxtb r3, r3 800a9ec: f003 0307 and.w r3, r3, #7 800a9f0: 733b strb r3, [r7, #12] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 800a9f2: 7bbb ldrb r3, [r7, #14] 800a9f4: 7b3a ldrb r2, [r7, #12] 800a9f6: 4911 ldr r1, [pc, #68] @ (800aa3c ) 800a9f8: 5c8a ldrb r2, [r1, r2] 800a9fa: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[tx_fifo_threshold]; 800a9fe: 7b3a ldrb r2, [r7, #12] 800aa00: 490f ldr r1, [pc, #60] @ (800aa40 ) 800aa02: 5c8a ldrb r2, [r1, r2] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 800aa04: fb93 f3f2 sdiv r3, r3, r2 800aa08: b29a uxth r2, r3 800aa0a: 687b ldr r3, [r7, #4] 800aa0c: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 800aa10: 7bfb ldrb r3, [r7, #15] 800aa12: 7b7a ldrb r2, [r7, #13] 800aa14: 4909 ldr r1, [pc, #36] @ (800aa3c ) 800aa16: 5c8a ldrb r2, [r1, r2] 800aa18: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[rx_fifo_threshold]; 800aa1c: 7b7a ldrb r2, [r7, #13] 800aa1e: 4908 ldr r1, [pc, #32] @ (800aa40 ) 800aa20: 5c8a ldrb r2, [r1, r2] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 800aa22: fb93 f3f2 sdiv r3, r3, r2 800aa26: b29a uxth r2, r3 800aa28: 687b ldr r3, [r7, #4] 800aa2a: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 } 800aa2e: bf00 nop 800aa30: 3714 adds r7, #20 800aa32: 46bd mov sp, r7 800aa34: f85d 7b04 ldr.w r7, [sp], #4 800aa38: 4770 bx lr 800aa3a: bf00 nop 800aa3c: 0800aae4 .word 0x0800aae4 800aa40: 0800aaec .word 0x0800aaec 0800aa44 : 800aa44: 4402 add r2, r0 800aa46: 4603 mov r3, r0 800aa48: 4293 cmp r3, r2 800aa4a: d100 bne.n 800aa4e 800aa4c: 4770 bx lr 800aa4e: f803 1b01 strb.w r1, [r3], #1 800aa52: e7f9 b.n 800aa48 0800aa54 <__libc_init_array>: 800aa54: b570 push {r4, r5, r6, lr} 800aa56: 4d0d ldr r5, [pc, #52] @ (800aa8c <__libc_init_array+0x38>) 800aa58: 4c0d ldr r4, [pc, #52] @ (800aa90 <__libc_init_array+0x3c>) 800aa5a: 1b64 subs r4, r4, r5 800aa5c: 10a4 asrs r4, r4, #2 800aa5e: 2600 movs r6, #0 800aa60: 42a6 cmp r6, r4 800aa62: d109 bne.n 800aa78 <__libc_init_array+0x24> 800aa64: 4d0b ldr r5, [pc, #44] @ (800aa94 <__libc_init_array+0x40>) 800aa66: 4c0c ldr r4, [pc, #48] @ (800aa98 <__libc_init_array+0x44>) 800aa68: f000 f818 bl 800aa9c <_init> 800aa6c: 1b64 subs r4, r4, r5 800aa6e: 10a4 asrs r4, r4, #2 800aa70: 2600 movs r6, #0 800aa72: 42a6 cmp r6, r4 800aa74: d105 bne.n 800aa82 <__libc_init_array+0x2e> 800aa76: bd70 pop {r4, r5, r6, pc} 800aa78: f855 3b04 ldr.w r3, [r5], #4 800aa7c: 4798 blx r3 800aa7e: 3601 adds r6, #1 800aa80: e7ee b.n 800aa60 <__libc_init_array+0xc> 800aa82: f855 3b04 ldr.w r3, [r5], #4 800aa86: 4798 blx r3 800aa88: 3601 adds r6, #1 800aa8a: e7f2 b.n 800aa72 <__libc_init_array+0x1e> 800aa8c: 0800aafc .word 0x0800aafc 800aa90: 0800aafc .word 0x0800aafc 800aa94: 0800aafc .word 0x0800aafc 800aa98: 0800ab00 .word 0x0800ab00 0800aa9c <_init>: 800aa9c: b5f8 push {r3, r4, r5, r6, r7, lr} 800aa9e: bf00 nop 800aaa0: bcf8 pop {r3, r4, r5, r6, r7} 800aaa2: bc08 pop {r3} 800aaa4: 469e mov lr, r3 800aaa6: 4770 bx lr 0800aaa8 <_fini>: 800aaa8: b5f8 push {r3, r4, r5, r6, r7, lr} 800aaaa: bf00 nop 800aaac: bcf8 pop {r3, r4, r5, r6, r7} 800aaae: bc08 pop {r3} 800aab0: 469e mov lr, r3 800aab2: 4770 bx lr